Enable RV32A testing with riscv-arch-test

Modify the setup script to enable RV32A testing in conjunction with
riscv-arch-test. With this update, the testing infrastructure is
configured to support RV32A tests, enhancing the compatibility and
validation capabilities of the environment.

Author: visitorckw

mk/riscv-arch-test.mk

@@ -3,7 +3,7 @@ ARCH_TEST_SUITE ?= $(ARCH_TEST_DIR)/riscv-test-suite
 export RISCV_TARGET := tests/arch-test-target
 export TARGETDIR := $(shell pwd)
 export WORK := $(TARGETDIR)/build/arch-test
-export RISCV_DEVICE ?= IMCZicsrZifencei
+export RISCV_DEVICE ?= IMACFZicsrZifencei
 
 ifeq ($(RISCV_DEVICE),FCZicsr)
 ARCH_TEST_SUITE := tests/rv32fc-test-suite

tests/arch-test-target/constants.py

@@ -6,6 +6,7 @@
 root = os.path.abspath(os.path.dirname(__file__))
 cwd = os.getcwd()
 
+misa_A = (1 << 0)
 misa_C = (1 << 2)
 misa_F = (1 << 5)
 misa_M = (1 << 12)

tests/arch-test-target/setup.py

@@ -15,6 +15,9 @@ def setup_testlist(riscv_device):
     if 'M' in riscv_device:
         misa |= constants.misa_M
         ISA += 'M'
+    if 'A' in riscv_device:
+        misa |= constants.misa_A
+        ISA += 'A'
     if 'F' in riscv_device:
         misa |= constants.misa_F
         ISA += 'F'
@@ -55,7 +58,7 @@ def setup_config():
 if __name__=="__main__":
     parser = argparse.ArgumentParser()
     parser.add_argument('--riscv_device', help='the ISA will test',
-                        default='IMCZicsrZifencei')
+                        default='IMACZicsrZifencei')
     args = parser.parse_args()
 
     setup_testlist(args.riscv_device)