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Remove insn_len field in IR structure
1 parent d08dd05 commit 15ead60

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4 files changed

+10
-14
lines changed

4 files changed

+10
-14
lines changed

src/decode.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1726,10 +1726,9 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)
17261726
/* If the last 2-bit is one of 0b00, 0b01, and 0b10, it is
17271727
* a 16-bit instruction.
17281728
*/
1729-
if ((insn & FC_OPCODE) != 3) {
1729+
if (is_compressed(insn)) {
17301730
insn &= 0x0000FFFF;
17311731
const uint16_t c_index = (insn & FC_FUNC3) >> 11 | (insn & FC_OPCODE);
1732-
ir->insn_len = INSN_16;
17331732

17341733
/* decode instruction (compressed instructions) */
17351734
const decode_t op = rvc_jump_table[c_index];
@@ -1740,7 +1739,6 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)
17401739

17411740
/* standard uncompressed instruction */
17421741
const uint32_t index = (insn & INSN_6_2) >> 2;
1743-
ir->insn_len = INSN_32;
17441742

17451743
/* decode instruction */
17461744
const decode_t op = rv_jump_table[index];

src/decode.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -246,11 +246,6 @@ enum {
246246
};
247247
/* clang-format on */
248248

249-
enum {
250-
INSN_16 = 2,
251-
INSN_32 = 4,
252-
};
253-
254249
typedef struct {
255250
int32_t imm;
256251
uint8_t rd, rs1, rs2;
@@ -275,9 +270,6 @@ typedef struct rv_insn {
275270

276271
uint32_t pc;
277272

278-
/* instruction length */
279-
uint8_t insn_len;
280-
281273
/* Tail-call optimization (TCO) allows a C function to replace a function
282274
* call to another function or itself, followed by a simple return of the
283275
* function's result, with a direct jump to the target function. This

src/emulate.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ enum {
6161

6262
static void rv_exception_default_handler(riscv_t *rv)
6363
{
64-
rv->csr_mepc += rv->compressed ? INSN_16 : INSN_32;
64+
rv->csr_mepc += rv->compressed ? 2 : 4;
6565
rv->PC = rv->csr_mepc; /* mret */
6666
}
6767

@@ -628,14 +628,14 @@ static void block_translate(riscv_t *rv, block_map_t *map, block_t *block)
628628

629629
/* decode the instruction */
630630
if (!rv_decode(ir, insn)) {
631-
rv->compressed = (ir->insn_len == INSN_16);
631+
rv->compressed = is_compressed(insn);
632632
rv_except_illegal_insn(rv, insn);
633633
break;
634634
}
635635
ir->impl = dispatch_table[ir->opcode];
636636
ir->pc = block->pc_end;
637637
/* compute the end of pc */
638-
block->pc_end += ir->insn_len;
638+
block->pc_end += is_compressed(insn) ? 2 : 4;
639639
block->n_insn++;
640640
prev_ir = ir;
641641
/* stop on branch */

src/riscv_private.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,3 +139,9 @@ FORCE_INLINE uint32_t sign_extend_b(const uint32_t x)
139139
{
140140
return (int32_t) ((int8_t) x);
141141
}
142+
143+
/* Detect the instruction is RV32C or not */
144+
FORCE_INLINE bool is_compressed(uint32_t insn)
145+
{
146+
return (insn & FC_OPCODE) != 3;
147+
}

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