Implement vector masking

Modified the compute logic in `V*_LOOP` and `V*_LOOP` left, feature
vector vector.Since the vector mask will update the vector for example:
vector config:sew = 8,
--------------------------
v12[0] |3a|07|6f|0e
--------------------------
v11[0] |11|33|90|81
--------------------------
mask   |0 |1 |0 |0
--------------------------
vadd.vi v12, v11, 0, v0.t
--------------------------
result |3a|33|6f|0e
--------------------------

If corresponding mask bit is 0, the value of the destination vector
register is preserved. So the procedure will be:
1. Copy the destination register.
2. Clear the amount of bits corresponding to `vl`.
3. Use `ans` to record the compute result.
4. Update the destination vector register with `ans`.

Notice that if `ir->vm == 0` it activates vector masking.

Add `tests/riscv-vector-tests/` to `.gitignore`

Author: vestata

.gitignore

@@ -29,6 +29,7 @@ tests/**/*.elf
 tests/arch-test-target/config.ini
 tests/arch-test-target/sail_cSim/riscv_sim_RV32
 tests/scimark2/
+tests/riscv-vector-tests/
 __pycache__/
 src/rv32_jit.c
 src/minimal_dtb.h