Add "ieeelib" and ENABLE_PREBUILT option

Author: vacantron

.github/workflows/build-artifact.yml

@@ -26,7 +26,7 @@ jobs:
       - name: Set alias
         id: has_files_changed
         run: |
-          if [[ ${{ steps.files-changed.outputs.any_changed }} == true ]]; then
+          if [[ ${{ steps.files-changed.outputs.any_modified }} == true ]]; then
             echo "has_files_changed=true" >> $GITHUB_OUTPUT
           else
             echo "has_files_changed=false" >> $GITHUB_OUTPUT
@@ -48,19 +48,37 @@ jobs:
           sudo apt-get update -q -y
           sudo apt-get upgrade -q -y
           sudo apt-get install -q -y gcc-multilib g++-multilib
+          sudo apt-get install -q -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev
           .ci/riscv-toolchain-install.sh
           echo "$PWD/toolchain/bin" >> $GITHUB_PATH
       - name: Build binaries
         run: |
-          make artifact USE_PREBUILT=0
+          make artifact ENABLE_PREBUILT=0
+          mkdir -p /tmp/rv32emu-prebuilt
+          mv build/linux-x86-softfp build/riscv32 /tmp/rv32emu-prebuilt
+      - name: Buile Sail model
+        run: |
+          cd /tmp
+          opam init -y --disable-sandboxing
+          opam switch create ocaml-base-compiler.4.06.1
+          opam install sail -y
+          eval $(opam config env)
+          git clone https://github.com/riscv/sail-riscv.git
+          cd sail-riscv
+          git checkout 9547a30bf84572c458476591b569a95f5232c1c7
+          ARCH=RV32 make -j
+          mkdir -p /tmp/rv32emu-prebuilt/sail_cSim
+          mv c_emulator/riscv_sim_RV32 /tmp/rv32emu-prebuilt/sail_cSim
       - name: Create tarball
         run: |
-          tar -C build -zcf rv32emu-prebuilt.tar.gz linux-x64 riscv32
+          cd /tmp
+          tar -zcvf rv32emu-prebuilt.tar.gz rv32emu-prebuilt
       - name: Create GitHub Release
         env:
           GH_TOKEN: ${{ secrets.RV32EMU_PREBUILT_TOKEN }}
         run: |
           RELEASE_TAG=$(date +'%Y.%m.%d')
+          cd /tmp
           gh release create $RELEASE_TAG \
             --repo sysprog21/rv32emu-prebuilt \
             --title "$RELEASE_TAG""-nightly"

.gitignore

@@ -16,11 +16,14 @@ build/softfloat
 build/cache/
 build/map/
 build/path/
-build/linux-x64/
+build/linux-x86-softfp/
 build/riscv32/
+build/sail_cSim/
+*.a
 *.o
 *.o.d
 tests/**/*.elf
 tests/arch-test-target/config.ini
+tests/arch-test-target/sail_cSim/riscv_sim_RV32
 __pycache__/
 src/rv32_jit.c

.gitmodules

@@ -19,3 +19,7 @@
 	path = tests/rv8-bench
 	url = https://github.com/sysprog21/rv8-bench
 	shallow = true
+[submodule "src/ieeelib"]
+	path = src/ieeelib
+	url = https://github.com/sysprog21/ieeelib
+	shallow = true

docs/prebuilt.md

@@ -1,8 +1,6 @@
 # Prebuilt Binaries
 
-There are some prebuilt binaries placed in [rv32emu-prebuilt](https://github.com/sysprog21/rv32emu-prebuilt).
-When invoking testing or benchmarking, the prebuilt binaries will be pulled into `build/linux-x64/` and `build/riscv32/` directory in default.
-The RISC-V binaries are built from [xPack RISC-V GCC toolchain](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack) with `-march=rv32im -mabi=ilp32` options.
+The prebuilt binaries for [rv32emu](https://github.com/sysprog21/rv32emu) are prepared primarily because the [RISC-V Sail Model](https://github.com/riscv/sail-riscv) executable is required for the [RISC-V Architecture Test](https://github.com/riscv-non-isa/riscv-arch-test), and selected RISC-V ELF files are useful for ISA simulation validation and testing. Some of these prebuilt binaries are stored in [rv32emu-prebuilt](https://github.com/sysprog21/rv32emu-prebuilt). During testing or benchmarking, these binaries are automatically downloaded into the `build/linux-x86-softfp/` and `build/riscv32/` directories by default. The RISC-V binaries are compiled using the [xPack RISC-V GCC toolchain](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack) with the options `-march=rv32im -mabi=ilp32`.
 
 To fetch the prebuilt binaries manually, run:
 
@@ -13,18 +11,18 @@ $ make artifact
 Or build the binaries from scratch (the RISC-V cross-compiler is required):
 
 ```shell
-$ make artifact USE_PREBUILT=0 [CROSS_COMPILE=<COMPILER_PREFIX>]
+$ make artifact ENABLE_PREBUILT=0 [CROSS_COMPILE=<COMPILER_PREFIX>]
 ```
 
 The compiler prefix varies according to the used toolchain, such as `riscv-none-elf-`, `riscv32-unknwon-elf-`, etc.
 
 The prebuilt binaries in `rv32emu-prebuilt` are built from the following repositories and resources:
 
-- [ansibench](https://github.com/nfinit/ansibench)
+- [ansibench](https://github.com/sysprog21/ansibench)
     - coremark
     - stream
     - nbench
-- [rv8-bench](https://github.com/michaeljclark/rv8-bench)
+- [rv8-bench](https://github.com/sysprog21/rv8-bench)
     - aes
     - dhrystone
     - miniz
@@ -51,8 +49,6 @@ The prebuilt binaries in `rv32emu-prebuilt` are built from the following reposit
 - `spirograph` : See [tests/spirograph.c](tests/spirograph.c)
 - `uaes` : See [tests/uaes.c](tests/uaes.c)
 
----
-
 There are still some prebuilt standalone RISC-V binaries under `build/` directory only for testing purpose:
 
 - `hello.elf` : See [tests/asm-hello](tests/asm-hello)

mk/artifact.mk

@@ -1,4 +1,4 @@
-USE_PREBUILT ?= 1
+ENABLE_PREBUILT ?= 1
 
 CC ?= gcc
 CROSS_COMPILE ?= riscv-none-elf-
@@ -16,7 +16,6 @@ TESTBENCHES += \
 	donut \
 	fcalc \
 	hamilton \
-	$(ieee754) \
 	jit \
 	lena \
 	line \
@@ -29,29 +28,41 @@ TESTBENCHES += \
 	qrcode \
 	richards \
 	rvsim \
-	$(smolnes) \
 	spirograph \
-	$(ticks) \
 	uaes
 
-ifeq ($(USE_PREBUILT),1)
+SHELL_HACK := $(shell mkdir -p $(BINDIR)/linux-x86-softfp $(BINDIR)/riscv32)
+
+ifeq ($(call has, PREBUILT), 1)
   LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases/latest -O- | grep -Po '(?<="tag_name": ").+(?=",)')
+else
+  CFLAGS := -m32 -mno-sse -mno-sse2 -msoft-float -O2 -L$(BINDIR)
+  LDFLAGS := -lsoft-fp -lm
+
+  CFLAGS_CROSS := -march=rv32im -mabi=ilp32 -O2
+  LDFLAGS_CROSS := -lm -lsemihost
 endif
 
 .PHONY: artifact
 
 artifact:
-ifeq ($(USE_PREBUILT),1)
-	@echo "Fetching prebuilt executables in \"rv32emu-prebuilt\"..."
-	@wget -q --show-progress https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/rv32emu-prebuilt.tar.gz -O- | tar -C build -xz
+ifeq ($(call has, PREBUILT), 1)
+	$(Q)$(PRINTF) "Fetching prebuilt executables from \"rv32emu-prebuilt\" ...\n"
+	$(Q)wget -q --show-progress https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/rv32emu-prebuilt.tar.gz -O- | tar -C build --strip-components=1 -xz
 else
-	@$(foreach tb,$(TEST_SUITES), \
-	    git submodule update --init ./tests/$(tb) &&) true
-	@$(foreach tb,$(TEST_SUITES), \
-		$(MAKE) -C ./tests/$(tb) all BINDIR=$(BINDIR) &&) true
-	@$(foreach tb,$(TESTBENCHES), \
-	    $(CC) -m32 -O2 -Wno-unused-result -o $(BINDIR)/linux-x64/$(tb) tests/$(tb).c -lm &&) true
-	@$(foreach tb,$(TESTBENCHES), \
-	    $(CROSS_COMPILE)gcc -march=rv32im -mabi=ilp32 -O2 -Wno-unused-result -Wno-implicit-function-declaration \
-		    -o $(BINDIR)/riscv32/$(tb) tests/$(tb).c -lm -lsemihost &&) true
+	git submodule update --init ./src/ieeelib $(addprefix ./tests/,$(foreach tb,$(TEST_SUITES),$(tb)))
+	$(Q)$(MAKE) -C ./src/ieeelib CC=$(CC) CFLAGS="$(CFLAGS)" BINDIR=$(BINDIR)
+	$(Q)for tb in $(TEST_SUITES); do \
+	    CC=$(CC) CFLAGS="$(CFLAGS)" LDFLAGS="$(LDFLAGS)" BINDIR=$(BINDIR)/linux-x86-softfp $(MAKE) -C ./tests/$$tb; \
+	done
+	$(Q)for tb in $(TEST_SUITES); do \
+	    CC=$(CROSS_COMPILE)gcc CFLAGS="$(CFLAGS_CROSS)" LDFLAGS="$(LDFLAGS_CROSS)" BINDIR=$(BINDIR)/riscv32 $(MAKE) -C ./tests/$$tb; \
+	done
+	$(Q)$(PRINTF) "Building standalone testbenches ...\n"
+	$(Q)for tb in $(TESTBENCHES); do \
+	    $(CC) $(CFLAGS) -Wno-unused-result -o $(BINDIR)/linux-x86-softfp/$$tb ./tests/$$tb.c $(LDFLAGS); \
+	done
+	$(Q)for tb in $(TESTBENCHES); do \
+	    $(CROSS_COMPILE)gcc $(CFLAGS_CROSS) -o $(BINDIR)/riscv32/$$tb ./tests/$$tb.c $(LDFLAGS_CROSS); \
+	done
 endif

mk/riscv-arch-test.mk

@@ -14,6 +14,7 @@ ifeq ($(CROSS_COMPILE),)
 	$(error GNU Toolchain for RISC-V is required to build architecture tests. Please check package installation)
 endif
 	git submodule update --init $(dir $(ARCH_TEST_DIR))
+	$(Q)cp $(OUT)/sail_cSim/riscv_sim_RV32 tests/arch-test-target/sail_cSim/riscv_sim_RV32
 	$(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE)
 	$(Q)riscof run --work-dir=$(WORK) \
 			--config=$(RISCV_TARGET)/config.ini \