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Manipulate csr_cycle, PC and insn_len by register
To eliminate the overhead of memory operation on frequently used rv fields and ir fields, we pass csr_cycle and PC as parameter and assigin insn_len as constant value. * Before 000000000000b1f0 <do_nop>: b1f0: 48 83 87 a8 01 00 00 addq $0x1,0x1a8(%rdi) b1f7: 01 b1f8: c7 47 58 00 00 00 00 movl $0x0,0x58(%rdi) b1ff: 0f b6 46 1c movzbl 0x1c(%rsi),%eax b203: 01 87 d8 00 00 00 add %eax,0xd8(%rdi) b209: 0f b6 46 1d movzbl 0x1d(%rsi),%eax b20d: 0a 87 10 01 00 00 or 0x110(%rdi),%al b213: 75 0b jne b220 <do_nop+0x30> b215: 48 8b 76 38 mov 0x38(%rsi),%rsi b219: ff 66 20 jmpq *0x20(%rsi) b21c: 0f 1f 40 00 nopl 0x0(%rax) b220: c3 retq b221: 66 66 2e 0f 1f 84 00 data16 nopw %cs:0x0(%rax,%rax,1) b228: 00 00 00 00 b22c: 0f 1f 40 00 nopl 0x0(%rax) * After 000000000000a6d0 <do_nop>: a6d0: c7 47 58 00 00 00 00 movl $0x0,0x58(%rdi) a6d7: 0f b6 46 1d movzbl 0x1d(%rsi),%eax a6db: 48 83 c2 01 add $0x1,%rdx a6df: 83 c1 04 add $0x4,%ecx a6e2: 0a 87 10 01 00 00 or 0x110(%rdi),%al a6e8: 75 0e jne a6f8 <do_nop+0x28> a6ea: 48 8b 76 38 mov 0x38(%rsi),%rsi a6ee: ff 66 20 jmp *0x20(%rsi) a6f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) a6f8: 48 89 97 a8 01 00 00 mov %rdx,0x1a8(%rdi) a6ff: 89 8f d8 00 00 00 mov %ecx,0xd8(%rdi) a705: c3 ret a706: 66 2e 0f 1f 84 00 00 cs nopw 0x0(%rax,%rax,1) a70d: 00 00 00 The operands of two x86 add instructions for csr_cycle, PC and insn_len are all registers, instead of memory location. Close: #241
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‎src/decode.h

Lines changed: 148 additions & 147 deletions
Original file line numberDiff line numberDiff line change
@@ -28,160 +28,161 @@ enum op_field {
2828
#define ENC_GEN(X, A) ENCN(X, A)
2929
#define ENC(...) ENC_GEN(ENC, COUNT_VARARGS(__VA_ARGS__))(__VA_ARGS__)
3030

31-
/* RISC-V instruction list in format _(instruction-name, can-branch, reg-mask)
31+
/* RISC-V instruction list in format _(instruction-name, can-branch, insn_len,
32+
* reg-mask)
3233
*/
3334
/* clang-format off */
34-
#define RV_INSN_LIST \
35-
_(nop, 0, ENC(rs1, rd)) \
36-
/* RV32I Base Instruction Set */ \
37-
_(lui, 0, ENC(rd)) \
38-
_(auipc, 0, ENC(rd)) \
39-
_(jal, 1, ENC(rd)) \
40-
_(jalr, 1, ENC(rs1, rd)) \
41-
_(beq, 1, ENC(rs1, rs2)) \
42-
_(bne, 1, ENC(rs1, rs2)) \
43-
_(blt, 1, ENC(rs1, rs2)) \
44-
_(bge, 1, ENC(rs1, rs2)) \
45-
_(bltu, 1, ENC(rs1, rs2)) \
46-
_(bgeu, 1, ENC(rs1, rs2)) \
47-
_(lb, 0, ENC(rs1, rd)) \
48-
_(lh, 0, ENC(rs1, rd)) \
49-
_(lw, 0, ENC(rs1, rd)) \
50-
_(lbu, 0, ENC(rs1, rd)) \
51-
_(lhu, 0, ENC(rs1, rd)) \
52-
_(sb, 0, ENC(rs1, rs2)) \
53-
_(sh, 0, ENC(rs1, rs2)) \
54-
_(sw, 0, ENC(rs1, rs2)) \
55-
_(addi, 0, ENC(rs1, rd)) \
56-
_(slti, 0, ENC(rs1, rd)) \
57-
_(sltiu, 0, ENC(rs1, rd)) \
58-
_(xori, 0, ENC(rs1, rd)) \
59-
_(ori, 0, ENC(rs1, rd)) \
60-
_(andi, 0, ENC(rs1, rd)) \
61-
_(slli, 0, ENC(rs1, rd)) \
62-
_(srli, 0, ENC(rs1, rd)) \
63-
_(srai, 0, ENC(rs1, rd)) \
64-
_(add, 0, ENC(rs1, rs2, rd)) \
65-
_(sub, 0, ENC(rs1, rs2, rd)) \
66-
_(sll, 0, ENC(rs1, rs2, rd)) \
67-
_(slt, 0, ENC(rs1, rs2, rd)) \
68-
_(sltu, 0, ENC(rs1, rs2, rd)) \
69-
_(xor, 0, ENC(rs1, rs2, rd)) \
70-
_(srl, 0, ENC(rs1, rs2, rd)) \
71-
_(sra, 0, ENC(rs1, rs2, rd)) \
72-
_(or, 0, ENC(rs1, rs2, rd)) \
73-
_(and, 0, ENC(rs1, rs2, rd)) \
74-
_(ecall, 1, ENC(rs1, rd)) \
75-
_(ebreak, 1, ENC(rs1, rd)) \
76-
/* RISC-V Privileged Instruction */ \
77-
_(wfi, 0, ENC(rs1, rd)) \
78-
_(uret, 0, ENC(rs1, rd)) \
79-
_(sret, 0, ENC(rs1, rd)) \
80-
_(hret, 0, ENC(rs1, rd)) \
81-
_(mret, 1, ENC(rs1, rd)) \
82-
/* RV32 Zifencei Standard Extension */ \
83-
IIF(RV32_HAS(Zifencei))( \
84-
_(fencei, 1, ENC(rs1, rd)) \
85-
) \
86-
/* RV32 Zicsr Standard Extension */ \
87-
IIF(RV32_HAS(Zicsr))( \
88-
_(csrrw, 0, ENC(rs1, rd)) \
89-
_(csrrs, 0, ENC(rs1, rd)) \
90-
_(csrrc, 0, ENC(rs1, rd)) \
91-
_(csrrwi, 0, ENC(rs1, rd)) \
92-
_(csrrsi, 0, ENC(rs1, rd)) \
93-
_(csrrci, 0, ENC(rs1, rd)) \
94-
) \
95-
/* RV32M Standard Extension */ \
96-
IIF(RV32_HAS(EXT_M))( \
97-
_(mul, 0, ENC(rs1, rs2, rd)) \
98-
_(mulh, 0, ENC(rs1, rs2, rd)) \
99-
_(mulhsu, 0, ENC(rs1, rs2, rd)) \
100-
_(mulhu, 0, ENC(rs1, rs2, rd)) \
101-
_(div, 0, ENC(rs1, rs2, rd)) \
102-
_(divu, 0, ENC(rs1, rs2, rd)) \
103-
_(rem, 0, ENC(rs1, rs2, rd)) \
104-
_(remu, 0, ENC(rs1, rs2, rd)) \
105-
) \
106-
/* RV32A Standard Extension */ \
107-
IIF(RV32_HAS(EXT_A))( \
108-
_(lrw, 0, ENC(rs1, rs2, rd)) \
109-
_(scw, 0, ENC(rs1, rs2, rd)) \
110-
_(amoswapw, 0, ENC(rs1, rs2, rd)) \
111-
_(amoaddw, 0, ENC(rs1, rs2, rd)) \
112-
_(amoxorw, 0, ENC(rs1, rs2, rd)) \
113-
_(amoandw, 0, ENC(rs1, rs2, rd)) \
114-
_(amoorw, 0, ENC(rs1, rs2, rd)) \
115-
_(amominw, 0, ENC(rs1, rs2, rd)) \
116-
_(amomaxw, 0, ENC(rs1, rs2, rd)) \
117-
_(amominuw, 0, ENC(rs1, rs2, rd)) \
118-
_(amomaxuw, 0, ENC(rs1, rs2, rd)) \
119-
) \
120-
/* RV32F Standard Extension */ \
121-
IIF(RV32_HAS(EXT_F))( \
122-
_(flw, 0, ENC(rs1, rd)) \
123-
_(fsw, 0, ENC(rs1, rs2)) \
124-
_(fmadds, 0, ENC(rs1, rs2, rs3, rd)) \
125-
_(fmsubs, 0, ENC(rs1, rs2, rs3, rd)) \
126-
_(fnmsubs, 0, ENC(rs1, rs2, rs3, rd)) \
127-
_(fnmadds, 0, ENC(rs1, rs2, rs3, rd)) \
128-
_(fadds, 0, ENC(rs1, rs2, rd)) \
129-
_(fsubs, 0, ENC(rs1, rs2, rd)) \
130-
_(fmuls, 0, ENC(rs1, rs2, rd)) \
131-
_(fdivs, 0, ENC(rs1, rs2, rd)) \
132-
_(fsqrts, 0, ENC(rs1, rs2, rd)) \
133-
_(fsgnjs, 0, ENC(rs1, rs2, rd)) \
134-
_(fsgnjns, 0, ENC(rs1, rs2, rd)) \
135-
_(fsgnjxs, 0, ENC(rs1, rs2, rd)) \
136-
_(fmins, 0, ENC(rs1, rs2, rd)) \
137-
_(fmaxs, 0, ENC(rs1, rs2, rd)) \
138-
_(fcvtws, 0, ENC(rs1, rs2, rd)) \
139-
_(fcvtwus, 0, ENC(rs1, rs2, rd)) \
140-
_(fmvxw, 0, ENC(rs1, rs2, rd)) \
141-
_(feqs, 0, ENC(rs1, rs2, rd)) \
142-
_(flts, 0, ENC(rs1, rs2, rd)) \
143-
_(fles, 0, ENC(rs1, rs2, rd)) \
144-
_(fclasss, 0, ENC(rs1, rs2, rd)) \
145-
_(fcvtsw, 0, ENC(rs1, rs2, rd)) \
146-
_(fcvtswu, 0, ENC(rs1, rs2, rd)) \
147-
_(fmvwx, 0, ENC(rs1, rs2, rd)) \
148-
) \
149-
/* RV32C Standard Extension */ \
150-
IIF(RV32_HAS(EXT_C))( \
151-
_(caddi4spn, 0, ENC(rd)) \
152-
_(clw, 0, ENC(rs1, rd)) \
153-
_(csw, 0, ENC(rs1, rs2)) \
154-
/* cnop is mapped to nop */ \
155-
_(caddi, 0, ENC(rd)) \
156-
_(cjal, 1, ENC()) \
157-
_(cli, 0, ENC(rd)) \
158-
_(caddi16sp, 0, ENC()) \
159-
_(clui, 0, ENC(rd)) \
160-
_(csrli, 0, ENC(rs1)) \
161-
_(csrai, 0, ENC(rs1)) \
162-
_(candi, 0, ENC(rs1)) \
163-
_(csub, 0, ENC(rs1, rs2, rd)) \
164-
_(cxor, 0, ENC(rs1, rs2, rd)) \
165-
_(cor, 0, ENC(rs1, rs2, rd)) \
166-
_(cand, 0, ENC(rs1, rs2, rd)) \
167-
_(cj, 1, ENC()) \
168-
_(cbeqz, 1, ENC(rs1)) \
169-
_(cbnez, 1, ENC(rs1)) \
170-
_(cslli, 0, ENC(rd)) \
171-
_(clwsp, 0, ENC(rd)) \
172-
_(cjr, 1, ENC(rs1, rs2, rd)) \
173-
_(cmv, 0, ENC(rs1, rs2, rd)) \
174-
_(cebreak, 1, ENC(rs1, rs2, rd)) \
175-
_(cjalr, 1, ENC(rs1, rs2, rd)) \
176-
_(cadd, 0, ENC(rs1, rs2, rd)) \
177-
_(cswsp, 0, ENC(rs2)) \
35+
#define RV_INSN_LIST \
36+
_(nop, 0, 4, ENC(rs1, rd)) \
37+
/* RV32I Base Instruction Set */ \
38+
_(lui, 0, 4, ENC(rd)) \
39+
_(auipc, 0, 4, ENC(rd)) \
40+
_(jal, 1, 4, ENC(rd)) \
41+
_(jalr, 1, 4, ENC(rs1, rd)) \
42+
_(beq, 1, 4, ENC(rs1, rs2)) \
43+
_(bne, 1, 4, ENC(rs1, rs2)) \
44+
_(blt, 1, 4, ENC(rs1, rs2)) \
45+
_(bge, 1, 4, ENC(rs1, rs2)) \
46+
_(bltu, 1, 4, ENC(rs1, rs2)) \
47+
_(bgeu, 1, 4, ENC(rs1, rs2)) \
48+
_(lb, 0, 4, ENC(rs1, rd)) \
49+
_(lh, 0, 4, ENC(rs1, rd)) \
50+
_(lw, 0, 4, ENC(rs1, rd)) \
51+
_(lbu, 0, 4, ENC(rs1, rd)) \
52+
_(lhu, 0, 4, ENC(rs1, rd)) \
53+
_(sb, 0, 4, ENC(rs1, rs2)) \
54+
_(sh, 0, 4, ENC(rs1, rs2)) \
55+
_(sw, 0, 4, ENC(rs1, rs2)) \
56+
_(addi, 0, 4, ENC(rs1, rd)) \
57+
_(slti, 0, 4, ENC(rs1, rd)) \
58+
_(sltiu, 0, 4, ENC(rs1, rd)) \
59+
_(xori, 0, 4, ENC(rs1, rd)) \
60+
_(ori, 0, 4, ENC(rs1, rd)) \
61+
_(andi, 0, 4, ENC(rs1, rd)) \
62+
_(slli, 0, 4, ENC(rs1, rd)) \
63+
_(srli, 0, 4, ENC(rs1, rd)) \
64+
_(srai, 0, 4, ENC(rs1, rd)) \
65+
_(add, 0, 4, ENC(rs1, rs2, rd)) \
66+
_(sub, 0, 4, ENC(rs1, rs2, rd)) \
67+
_(sll, 0, 4, ENC(rs1, rs2, rd)) \
68+
_(slt, 0, 4, ENC(rs1, rs2, rd)) \
69+
_(sltu, 0, 4, ENC(rs1, rs2, rd)) \
70+
_(xor, 0, 4, ENC(rs1, rs2, rd)) \
71+
_(srl, 0, 4, ENC(rs1, rs2, rd)) \
72+
_(sra, 0, 4, ENC(rs1, rs2, rd)) \
73+
_(or, 0, 4, ENC(rs1, rs2, rd)) \
74+
_(and, 0, 4, ENC(rs1, rs2, rd)) \
75+
_(ecall, 1, 4, ENC(rs1, rd)) \
76+
_(ebreak, 1, 4, ENC(rs1, rd)) \
77+
/* RISC-V Privileged Instruction */ \
78+
_(wfi, 0, 4, ENC(rs1, rd)) \
79+
_(uret, 0, 4, ENC(rs1, rd)) \
80+
_(sret, 0, 4, ENC(rs1, rd)) \
81+
_(hret, 0, 4, ENC(rs1, rd)) \
82+
_(mret, 1, 4, ENC(rs1, rd)) \
83+
/* RV32 Zifencei Standard Extension */ \
84+
IIF(RV32_HAS(Zifencei))( \
85+
_(fencei, 1, 4, ENC(rs1, rd)) \
86+
) \
87+
/* RV32 Zicsr Standard Extension */ \
88+
IIF(RV32_HAS(Zicsr))( \
89+
_(csrrw, 0, 4, ENC(rs1, rd)) \
90+
_(csrrs, 0, 4, ENC(rs1, rd)) \
91+
_(csrrc, 0, 4, ENC(rs1, rd)) \
92+
_(csrrwi, 0, 4, ENC(rs1, rd)) \
93+
_(csrrsi, 0, 4, ENC(rs1, rd)) \
94+
_(csrrci, 0, 4, ENC(rs1, rd)) \
95+
) \
96+
/* RV32M Standard Extension */ \
97+
IIF(RV32_HAS(EXT_M))( \
98+
_(mul, 0, 4, ENC(rs1, rs2, rd)) \
99+
_(mulh, 0, 4, ENC(rs1, rs2, rd)) \
100+
_(mulhsu, 0, 4, ENC(rs1, rs2, rd)) \
101+
_(mulhu, 0, 4, ENC(rs1, rs2, rd)) \
102+
_(div, 0, 4, ENC(rs1, rs2, rd)) \
103+
_(divu, 0, 4, ENC(rs1, rs2, rd)) \
104+
_(rem, 0, 4, ENC(rs1, rs2, rd)) \
105+
_(remu, 0, 4, ENC(rs1, rs2, rd)) \
106+
) \
107+
/* RV32A Standard Extension */ \
108+
IIF(RV32_HAS(EXT_A))( \
109+
_(lrw, 0, 4, ENC(rs1, rs2, rd)) \
110+
_(scw, 0, 4, ENC(rs1, rs2, rd)) \
111+
_(amoswapw, 0, 4, ENC(rs1, rs2, rd)) \
112+
_(amoaddw, 0, 4, ENC(rs1, rs2, rd)) \
113+
_(amoxorw, 0, 4, ENC(rs1, rs2, rd)) \
114+
_(amoandw, 0, 4, ENC(rs1, rs2, rd)) \
115+
_(amoorw, 0, 4, ENC(rs1, rs2, rd)) \
116+
_(amominw, 0, 4, ENC(rs1, rs2, rd)) \
117+
_(amomaxw, 0, 4, ENC(rs1, rs2, rd)) \
118+
_(amominuw, 0, 4, ENC(rs1, rs2, rd)) \
119+
_(amomaxuw, 0, 4, ENC(rs1, rs2, rd)) \
120+
) \
121+
/* RV32F Standard Extension */ \
122+
IIF(RV32_HAS(EXT_F))( \
123+
_(flw, 0, 4, ENC(rs1, rd)) \
124+
_(fsw, 0, 4, ENC(rs1, rs2)) \
125+
_(fmadds, 0, 4, ENC(rs1, rs2, rs3, rd)) \
126+
_(fmsubs, 0, 4, ENC(rs1, rs2, rs3, rd)) \
127+
_(fnmsubs, 0, 4, ENC(rs1, rs2, rs3, rd)) \
128+
_(fnmadds, 0, 4, ENC(rs1, rs2, rs3, rd)) \
129+
_(fadds, 0, 4, ENC(rs1, rs2, rd)) \
130+
_(fsubs, 0, 4, ENC(rs1, rs2, rd)) \
131+
_(fmuls, 0, 4, ENC(rs1, rs2, rd)) \
132+
_(fdivs, 0, 4, ENC(rs1, rs2, rd)) \
133+
_(fsqrts, 0, 4, ENC(rs1, rs2, rd)) \
134+
_(fsgnjs, 0, 4, ENC(rs1, rs2, rd)) \
135+
_(fsgnjns, 0, 4, ENC(rs1, rs2, rd)) \
136+
_(fsgnjxs, 0, 4, ENC(rs1, rs2, rd)) \
137+
_(fmins, 0, 4, ENC(rs1, rs2, rd)) \
138+
_(fmaxs, 0, 4, ENC(rs1, rs2, rd)) \
139+
_(fcvtws, 0, 4, ENC(rs1, rs2, rd)) \
140+
_(fcvtwus, 0, 4, ENC(rs1, rs2, rd)) \
141+
_(fmvxw, 0, 4, ENC(rs1, rs2, rd)) \
142+
_(feqs, 0, 4, ENC(rs1, rs2, rd)) \
143+
_(flts, 0, 4, ENC(rs1, rs2, rd)) \
144+
_(fles, 0, 4, ENC(rs1, rs2, rd)) \
145+
_(fclasss, 0, 4, ENC(rs1, rs2, rd)) \
146+
_(fcvtsw, 0, 4, ENC(rs1, rs2, rd)) \
147+
_(fcvtswu, 0, 4, ENC(rs1, rs2, rd)) \
148+
_(fmvwx, 0, 4, ENC(rs1, rs2, rd)) \
149+
) \
150+
/* RV32C Standard Extension */ \
151+
IIF(RV32_HAS(EXT_C))( \
152+
_(caddi4spn, 0, 2, ENC(rd)) \
153+
_(clw, 0, 2, ENC(rs1, rd)) \
154+
_(csw, 0, 2, ENC(rs1, rs2)) \
155+
/* cnop is mapped to nop */ \
156+
_(caddi, 0, 2, ENC(rd)) \
157+
_(cjal, 1, 2, ENC()) \
158+
_(cli, 0, 2, ENC(rd)) \
159+
_(caddi16sp, 0, 2, ENC()) \
160+
_(clui, 0, 2, ENC(rd)) \
161+
_(csrli, 0, 2, ENC(rs1)) \
162+
_(csrai, 0, 2, ENC(rs1)) \
163+
_(candi, 0, 2, ENC(rs1)) \
164+
_(csub, 0, 2, ENC(rs1, rs2, rd)) \
165+
_(cxor, 0, 2, ENC(rs1, rs2, rd)) \
166+
_(cor, 0, 2, ENC(rs1, rs2, rd)) \
167+
_(cand, 0, 2, ENC(rs1, rs2, rd)) \
168+
_(cj, 1, 2, ENC()) \
169+
_(cbeqz, 1, 2, ENC(rs1)) \
170+
_(cbnez, 1, 2, ENC(rs1)) \
171+
_(cslli, 0, 2, ENC(rd)) \
172+
_(clwsp, 0, 2, ENC(rd)) \
173+
_(cjr, 1, 2, ENC(rs1, rs2, rd)) \
174+
_(cmv, 0, 2, ENC(rs1, rs2, rd)) \
175+
_(cebreak, 1, 2, ENC(rs1, rs2, rd)) \
176+
_(cjalr, 1, 2, ENC(rs1, rs2, rd)) \
177+
_(cadd, 0, 2, ENC(rs1, rs2, rd)) \
178+
_(cswsp, 0, 2, ENC(rs2)) \
178179
)
179180
/* clang-format on */
180181

181182
/* clang-format off */
182183
/* IR list */
183184
enum {
184-
#define _(inst, can_branch, reg_mask) rv_insn_##inst,
185+
#define _(inst, can_branch, insn_len, reg_mask) rv_insn_##inst,
185186
RV_INSN_LIST
186187
#undef _
187188
N_RV_INSNS
@@ -291,7 +292,7 @@ typedef struct rv_insn {
291292
* self-recursive version, enabling the compiler to leverage TCO.
292293
*/
293294
struct rv_insn *next;
294-
bool (*impl)(riscv_t *, const struct rv_insn *);
295+
bool (*impl)(riscv_t *, const struct rv_insn *, uint64_t, uint32_t);
295296

296297
/* Two pointers, 'branch_taken' and 'branch_untaken', are employed to
297298
* avoid the overhead associated with aggressive memory copying. Instead

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