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Merge pull request #324 from visitorckw/fix-signed-integer-overflow
Fix signed integer overflow in RV32IM
2 parents 6dad720 + 32895fb commit 7dec1c1

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2 files changed

+14
-14
lines changed

2 files changed

+14
-14
lines changed

src/rv32_constopt.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,7 @@ CONSTOPT(srai, {
233233
CONSTOPT(add, {
234234
if (info->is_constant[ir->rs1] && info->is_constant[ir->rs2]) {
235235
info->is_constant[ir->rd] = true;
236-
ir->imm = (int32_t) info->const_val[ir->rs1] +
237-
(int32_t) info->const_val[ir->rs2];
236+
ir->imm = info->const_val[ir->rs1] + info->const_val[ir->rs2];
238237
info->const_val[ir->rd] = ir->imm;
239238
ir->opcode = rv_insn_lui;
240239
ir->impl = dispatch_table[ir->opcode];
@@ -246,8 +245,7 @@ CONSTOPT(add, {
246245
CONSTOPT(sub, {
247246
if (info->is_constant[ir->rs1] && info->is_constant[ir->rs2]) {
248247
info->is_constant[ir->rd] = true;
249-
ir->imm = (int32_t) info->const_val[ir->rs1] -
250-
(int32_t) info->const_val[ir->rs2];
248+
ir->imm = info->const_val[ir->rs1] - info->const_val[ir->rs2];
251249
info->const_val[ir->rd] = ir->imm;
252250
ir->opcode = rv_insn_lui;
253251
ir->impl = dispatch_table[ir->opcode];
@@ -410,8 +408,9 @@ CONSTOPT(csrrci, { info->is_constant[ir->rd] = false; })
410408
CONSTOPT(mul, {
411409
if (info->is_constant[ir->rs1] && info->is_constant[ir->rs2]) {
412410
info->is_constant[ir->rd] = true;
413-
ir->imm = (int32_t) info->const_val[ir->rs1] *
414-
(int32_t) info->const_val[ir->rs2];
411+
const int64_t multiplicand = (int32_t) info->const_val[ir->rs1];
412+
const int64_t multiplier = (int32_t) info->const_val[ir->rs2];
413+
ir->imm = ((uint64_t) (multiplicand * multiplier)) & ((1ULL << 32) - 1);
415414
info->const_val[ir->rd] = ir->imm;
416415
ir->opcode = rv_insn_lui;
417416
ir->impl = dispatch_table[ir->opcode];

src/rv32_template.c

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -603,7 +603,7 @@ RVOP(
603603
*/
604604
RVOP(
605605
addi,
606-
{ rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) + ir->imm; },
606+
{ rv->X[ir->rd] = rv->X[ir->rs1] + ir->imm; },
607607
GEN({
608608
ld, S32, TMP0, X, rs1;
609609
alu32_imm, 32, 0x81, 0, TMP0, imm;
@@ -732,9 +732,7 @@ RVOP(
732732
/* ADD */
733733
RVOP(
734734
add,
735-
{
736-
rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) + (int32_t) (rv->X[ir->rs2]);
737-
},
735+
{ rv->X[ir->rd] = rv->X[ir->rs1] + rv->X[ir->rs2]; },
738736
GEN({
739737
ld, S32, TMP0, X, rs1;
740738
ld, S32, TMP1, X, rs2;
@@ -745,9 +743,7 @@ RVOP(
745743
/* SUB: Substract */
746744
RVOP(
747745
sub,
748-
{
749-
rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) - (int32_t) (rv->X[ir->rs2]);
750-
},
746+
{ rv->X[ir->rd] = rv->X[ir->rs1] - rv->X[ir->rs2]; },
751747
GEN({
752748
ld, S32, TMP0, X, rs1;
753749
ld, S32, TMP1, X, rs2;
@@ -1051,7 +1047,12 @@ RVOP(
10511047
/* MUL: Multiply */
10521048
RVOP(
10531049
mul,
1054-
{ rv->X[ir->rd] = (int32_t) rv->X[ir->rs1] * (int32_t) rv->X[ir->rs2]; },
1050+
{
1051+
const int64_t multiplicand = (int32_t) rv->X[ir->rs1];
1052+
const int64_t multiplier = (int32_t) rv->X[ir->rs2];
1053+
rv->X[ir->rd] =
1054+
((uint64_t) (multiplicand * multiplier)) & ((1ULL << 32) - 1);
1055+
},
10551056
GEN({
10561057
ld, S32, TMP0, X, rs1;
10571058
ld, S32, TMP1, X, rs2;

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