@@ -65,6 +65,22 @@ static void rv_exception_default_handler(riscv_t *rv)
65
65
rv -> PC = rv -> csr_mepc ; /* mret */
66
66
}
67
67
68
+ /* When a trap occurs in M-mode, mtval is either initialized to zero or
69
+ * populated with exception-specific details to assist software in managing
70
+ * the trap. Otherwise, the implementation never modifies mtval, although
71
+ * software can explicitly write to it. The hardware platform will define
72
+ * which exceptions are required to informatively set mtval and which may
73
+ * consistently set it to zero.
74
+ *
75
+ * When a hardware breakpoint is triggered or an exception like address
76
+ * misalignment, access fault, or page fault occurs during an instruction
77
+ * fetch, load, or store operation, mtval is updated with the virtual address
78
+ * that caused the fault. In the case of an illegal instruction trap, mtval
79
+ * might be updated with the first XLEN or ILEN bits of the offending
80
+ * instruction. For all other traps, mtval is simply set to zero. However,
81
+ * it is worth noting that a future standard could redefine how mtval is
82
+ * handled for different types of traps.
83
+ */
68
84
#define EXCEPTION_HANDLER_IMPL (type , code ) \
69
85
static void rv_except_##type(riscv_t *rv, uint32_t mtval) \
70
86
{ \
0 commit comments