@@ -132,45 +132,45 @@ typedef enum {
132132 AS_SUB = 2 ,
133133 AS_SUBS = 3 ,
134134 /* LogicalOpcode */
135- LOG_AND = 0x00000000U , // 0000_0000_0000_0000_0000_0000_0000_0000
136- LOG_ORR = 0x20000000U , // 0010_0000_0000_0000_0000_0000_0000_0000
137- LOG_ORN = 0x20200000U , // 0010_0000_0010_0000_0000_0000_0000_0000
138- LOG_EOR = 0x40000000U , // 0100_0000_0000_0000_0000_0000_0000_0000
135+ LOG_AND = 0x00000000U , /* 0000_0000_0000_0000_0000_0000_0000_0000 */
136+ LOG_ORR = 0x20000000U , /* 0010_0000_0000_0000_0000_0000_0000_0000 */
137+ LOG_ORN = 0x20200000U , /* 0010_0000_0010_0000_0000_0000_0000_0000 */
138+ LOG_EOR = 0x40000000U , /* 0100_0000_0000_0000_0000_0000_0000_0000 */
139139 /* LoadStoreOpcode */
140- LS_STRB = 0x00000000U , // 0000_0000_0000_0000_0000_0000_0000_0000
141- LS_LDRB = 0x00400000U , // 0000_0000_0100_0000_0000_0000_0000_0000
142- LS_LDRSBW = 0x00c00000U , // 0000_0000_1100_0000_0000_0000_0000_0000
143- LS_STRH = 0x40000000U , // 0100_0000_0000_0000_0000_0000_0000_0000
144- LS_LDRH = 0x40400000U , // 0100_0000_0100_0000_0000_0000_0000_0000
145- LS_LDRSHW = 0x40c00000U , // 0100_0000_1100_0000_0000_0000_0000_0000
146- LS_STRW = 0x80000000U , // 1000_0000_0000_0000_0000_0000_0000_0000
147- LS_LDRW = 0x80400000U , // 1000_0000_0100_0000_0000_0000_0000_0000
148- LS_LDRSW = 0x80800000U , // 1000_0000_1000_0000_0000_0000_0000_0000
149- LS_STRX = 0xc0000000U , // 1100_0000_0000_0000_0000_0000_0000_0000
150- LS_LDRX = 0xc0400000U , // 1100_0000_0100_0000_0000_0000_0000_0000
140+ LS_STRB = 0x00000000U , /* 0000_0000_0000_0000_0000_0000_0000_0000 */
141+ LS_LDRB = 0x00400000U , /* 0000_0000_0100_0000_0000_0000_0000_0000 */
142+ LS_LDRSBW = 0x00c00000U , /* 0000_0000_1100_0000_0000_0000_0000_0000 */
143+ LS_STRH = 0x40000000U , /* 0100_0000_0000_0000_0000_0000_0000_0000 */
144+ LS_LDRH = 0x40400000U , /* 0100_0000_0100_0000_0000_0000_0000_0000 */
145+ LS_LDRSHW = 0x40c00000U , /* 0100_0000_1100_0000_0000_0000_0000_0000 */
146+ LS_STRW = 0x80000000U , /* 1000_0000_0000_0000_0000_0000_0000_0000 */
147+ LS_LDRW = 0x80400000U , /* 1000_0000_0100_0000_0000_0000_0000_0000 */
148+ LS_LDRSW = 0x80800000U , /* 1000_0000_1000_0000_0000_0000_0000_0000 */
149+ LS_STRX = 0xc0000000U , /* 1100_0000_0000_0000_0000_0000_0000_0000 */
150+ LS_LDRX = 0xc0400000U , /* 1100_0000_0100_0000_0000_0000_0000_0000 */
151151 /* LoadStorePairOpcode */
152- LSP_STPX = 0xa9000000U , // 1010_1001_0000_0000_0000_0000_0000_0000
153- LSP_LDPX = 0xa9400000U , // 1010_1001_0100_0000_0000_0000_0000_0000
152+ LSP_STPX = 0xa9000000U , /* 1010_1001_0000_0000_0000_0000_0000_0000 */
153+ LSP_LDPX = 0xa9400000U , /* 1010_1001_0100_0000_0000_0000_0000_0000 */
154154 /* UnconditionalBranchOpcode */
155- BR_BR = 0xd61f0000U , // 1101_0110_0001_1111_0000_0000_0000_0000
156- BR_BLR = 0xd63f0000U , // 1101_0110_0011_1111_0000_0000_0000_0000
157- BR_RET = 0xd65f0000U , // 1101_0110_0101_1111_0000_0000_0000_0000
155+ BR_BR = 0xd61f0000U , /* 1101_0110_0001_1111_0000_0000_0000_0000 */
156+ BR_BLR = 0xd63f0000U , /* 1101_0110_0011_1111_0000_0000_0000_0000 */
157+ BR_RET = 0xd65f0000U , /* 1101_0110_0101_1111_0000_0000_0000_0000 */
158158 /* UnconditionalBranchImmediateOpcode */
159- UBR_B = 0x14000000U , // 0001_0100_0000_0000_0000_0000_0000_0000
159+ UBR_B = 0x14000000U , /* 0001_0100_0000_0000_0000_0000_0000_0000 */
160160 /* ConditionalBranchImmediateOpcode */
161161 BR_Bcond = 0x54000000U ,
162162 /* DP2Opcode */
163- DP2_UDIV = 0x1ac00800U , // 0001_1010_1100_0000_0000_1000_0000_0000
164- DP2_LSLV = 0x1ac02000U , // 0001_1010_1100_0000_0010_0000_0000_0000
165- DP2_LSRV = 0x1ac02400U , // 0001_1010_1100_0000_0010_0100_0000_0000
166- DP2_ASRV = 0x1ac02800U , // 0001_1010_1100_0000_0010_1000_0000_0000
163+ DP2_UDIV = 0x1ac00800U , /* 0001_1010_1100_0000_0000_1000_0000_0000 */
164+ DP2_LSLV = 0x1ac02000U , /* 0001_1010_1100_0000_0010_0000_0000_0000 */
165+ DP2_LSRV = 0x1ac02400U , /* 0001_1010_1100_0000_0010_0100_0000_0000 */
166+ DP2_ASRV = 0x1ac02800U , /* 0001_1010_1100_0000_0010_1000_0000_0000 */
167167 /* DP3Opcode */
168- DP3_MADD = 0x1b000000U , // 0001_1011_0000_0000_0000_0000_0000_0000
169- DP3_MSUB = 0x1b008000U , // 0001_1011_0000_0000_1000_0000_0000_0000
168+ DP3_MADD = 0x1b000000U , /* 0001_1011_0000_0000_0000_0000_0000_0000 */
169+ DP3_MSUB = 0x1b008000U , /* 0001_1011_0000_0000_1000_0000_0000_0000 */
170170 /* MoveWideOpcode */
171- MW_MOVN = 0x12800000U , // 0001_0010_1000_0000_0000_0000_0000_0000
172- MW_MOVZ = 0x52800000U , // 0101_0010_1000_0000_0000_0000_0000_0000
173- MW_MOVK = 0x72800000U , // 0111_0010_1000_0000_0000_0000_0000_0000
171+ MW_MOVN = 0x12800000U , /* 0001_0010_1000_0000_0000_0000_0000_0000 */
172+ MW_MOVZ = 0x52800000U , /* 0101_0010_1000_0000_0000_0000_0000_0000 */
173+ MW_MOVK = 0x72800000U , /* 0111_0010_1000_0000_0000_0000_0000_0000 */
174174} a64opcode_t ;
175175
176176enum condition {
@@ -219,21 +219,21 @@ static int temp_reg = RCX;
219219#endif
220220#elif defined(__aarch64__ )
221221/* callee_reg - this must be a multiple of two because of how we save the stack
222- * later on. */
222+ * later on.
223+ */
223224static const int callee_reg [] = {R19 , R20 , R21 , R22 , R23 , R24 , R25 , R26 };
224225/* parameter_reg (Caller saved registers) */
225226static const int parameter_reg [] = {R0 , R1 , R2 , R3 , R4 };
226227static int temp_reg = R8 ;
227228
228- /* Register assignments:
229- * Arm64 Usage
230- * r0 - r4 Function parameters, caller-saved
231- * r6 - r8 Temp - used for storing calculated value during execution
232- * r19 - r23 Callee-saved registers
233- * r24 Temp - used for generating 32-bit immediates
234- * r25 Temp - used for modulous calculations
229+ /* Register assignments:
230+ * Arm64 Usage
231+ * r0 - r4 Function parameters, caller-saved
232+ * r6 - r8 Temp - used for storing calculated value during execution
233+ * r19 - r23 Callee-saved registers
234+ * r24 Temp - used for generating 32-bit immediates
235+ * r25 Temp - used for modulous calculations
235236 */
236-
237237static const int register_map [] = {
238238 R5 , R6 , R7 , R9 , R11 , R12 , R13 , R14 , R15 , R16 , R17 , R18 , R26 ,
239239};
@@ -435,7 +435,8 @@ static inline void emit_movewide_imm(struct jit_state *state,
435435 }
436436
437437 /* Iterate over 16-bit elements of imm, outputting an appropriate move
438- * instruction. */
438+ * instruction.
439+ */
439440 bool invert = (count0000 < countffff );
440441 a64opcode_t op = invert ? MW_MOVN : MW_MOVZ ;
441442 uint64_t skip_pattern = invert ? 0xffff : 0 ;
@@ -453,9 +454,8 @@ static inline void emit_movewide_imm(struct jit_state *state,
453454 }
454455
455456 /* Tidy up for the case imm = 0 or imm == -1. */
456- if (op != MW_MOVK ) {
457+ if (op != MW_MOVK )
457458 emit_a64 (state , sz (is64 ) | op | (0 << 21 ) | (0 << 5 ) | rd );
458- }
459459}
460460
461461/* [ARM-A]: C4.1.66: Load/store register (unscaled immediate). */
@@ -527,7 +527,7 @@ static void update_branch_imm(struct jit_state *state,
527527 memcpy (& insn , state -> buf + offset , sizeof (uint32_t ));
528528 if ((insn & 0xfe000000U ) == 0x54000000U /* Conditional branch immediate. */
529529 || (insn & 0x7e000000U ) ==
530- 0x34000000U ) { /* Compare and branch immediate. */
530+ 0x34000000U ) { /* Compare and branch immediate. */
531531 assert ((imm >> 19 ) == INT64_C (-1 ) || (imm >> 19 ) == 0 );
532532 insn |= (imm & 0x7ffff ) << 5 ;
533533 } else if ((insn & 0x7c000000U ) == 0x14000000U ) {
@@ -1206,9 +1206,8 @@ static int vm_reg[3] = {0};
12061206static void reset_reg ()
12071207{
12081208 count = 0 ;
1209- for (int i = 0 ; i < 32 ; i ++ ) {
1209+ for (int i = 0 ; i < 32 ; i ++ )
12101210 reg_table [i ] = -1 ;
1211- }
12121211}
12131212
12141213static void store_back (struct jit_state * state )
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