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ChinYikMingChinYikMing
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test
1 parent 25c3298 commit aeda753

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3 files changed

+52
-49
lines changed

3 files changed

+52
-49
lines changed

‎src/emulate.c

Lines changed: 21 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -176,8 +176,8 @@ RV_TRAP_LIST
176176
rv->compressed = compress; \
177177
rv->csr_cycle = cycle; \
178178
rv->PC = PC; \
179-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, type##_MISALIGNED, \
180-
IIF(IO)(addr, mask_or_pc)); \
179+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, type##_MISALIGNED, \
180+
IIF(IO)(addr, mask_or_pc)); \
181181
return false; \
182182
}
183183

@@ -667,7 +667,7 @@ static void block_translate(riscv_t *rv, block_t *block)
667667
/* decode the instruction */
668668
if (!rv_decode(ir, insn)) {
669669
rv->compressed = is_compressed(insn);
670-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, INSN_MISALIGNED, insn);
670+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, INSN_MISALIGNED, insn);
671671
break;
672672
}
673673
ir->impl = dispatch_table[ir->opcode];
@@ -1138,41 +1138,45 @@ static void __trap_handler(riscv_t *rv)
11381138

11391139
static void _trap_handler(riscv_t *rv)
11401140
{
1141-
uint32_t scause = rv->csr_scause;
1142-
uint32_t stval = rv->csr_stval;
1141+
uint32_t cause =
1142+
rv->priv_mode == RV_PRIV_S_MODE ? rv->csr_scause : rv->csr_mcause;
1143+
uint32_t tval =
1144+
rv->priv_mode == RV_PRIV_S_MODE ? rv->csr_stval : rv->csr_mtval;
11431145

1144-
switch (scause) {
1146+
switch (cause) {
11451147
#if !RV32_HAS(EXT_C)
11461148
case INSN_MISALIGNED:
1147-
rv_trap_insn_misaligned(rv, stval);
1149+
rv_trap_insn_misaligned(rv, tval);
11481150
break;
11491151
#endif /* EXT_C */
11501152
case ILLEGAL_INSN:
1151-
rv_trap_illegal_insn(rv, stval);
1153+
rv_trap_illegal_insn(rv, tval);
11521154
break;
11531155
case BREAKPOINT:
1154-
rv_trap_breakpoint(rv, stval);
1156+
rv_trap_breakpoint(rv, tval);
11551157
break;
11561158
case LOAD_MISALIGNED:
1157-
rv_trap_load_misaligned(rv, stval);
1159+
rv_trap_load_misaligned(rv, tval);
11581160
break;
11591161
case STORE_MISALIGNED:
1160-
rv_trap_store_misaligned(rv, stval);
1162+
rv_trap_store_misaligned(rv, tval);
11611163
break;
11621164
#if RV32_HAS(SYSTEM)
11631165
case PAGEFAULT_INSN:
1164-
rv_trap_pagefault_insn(rv, stval);
1166+
rv_trap_pagefault_insn(rv, tval);
11651167
break;
11661168
case PAGEFAULT_LOAD:
1167-
rv_trap_pagefault_load(rv, stval);
1169+
rv_trap_pagefault_load(rv, tval);
11681170
break;
11691171
case PAGEFAULT_STORE:
1170-
rv_trap_pagefault_store(rv, stval);
1172+
rv_trap_pagefault_store(rv, tval);
11711173
break;
11721174
#endif /* SYSTEM */
1175+
#if !RV32_HAS(SYSTEM)
11731176
case ECALL_M:
1174-
rv_trap_ecall_M(rv, stval);
1177+
rv_trap_ecall_M(rv, tval);
11751178
break;
1179+
#endif /* SYSTEM */
11761180
default:
11771181
__UNREACHABLE;
11781182
break;
@@ -1188,7 +1192,7 @@ void trap_handler(riscv_t *rv)
11881192
void ebreak_handler(riscv_t *rv)
11891193
{
11901194
assert(rv);
1191-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, BREAKPOINT, rv->PC);
1195+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, BREAKPOINT, rv->PC);
11921196
}
11931197

11941198
void ecall_handler(riscv_t *rv)
@@ -1198,7 +1202,7 @@ void ecall_handler(riscv_t *rv)
11981202
syscall_handler(rv);
11991203
rv->PC += 4;
12001204
#else
1201-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, ECALL_M, 0);
1205+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, ECALL_M, 0);
12021206
syscall_handler(rv);
12031207
#endif
12041208
}

‎src/riscv.h

Lines changed: 26 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -84,33 +84,6 @@ enum {
8484
};
8585
/* clang-format on */
8686

87-
enum TRAP_CODE {
88-
INSN_MISALIGNED = 0,
89-
ILLEGAL_INSN = 2,
90-
BREAKPOINT = 3,
91-
LOAD_MISALIGNED = 4,
92-
STORE_MISALIGNED = 6,
93-
PAGEFAULT_INSN = 12,
94-
PAGEFAULT_LOAD = 13,
95-
PAGEFAULT_STORE = 15,
96-
ECALL_M = 11,
97-
};
98-
99-
#define SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval) \
100-
{ \
101-
/* \
102-
* To align rv32emu behavior with Spike \
103-
* \
104-
* If not in system mode, the __trap_handler \
105-
* should be be invoked \
106-
*/ \
107-
IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true, ); \
108-
rv->csr_scause = scause; \
109-
rv->csr_stval = stval; \
110-
rv->io.on_trap(rv); \
111-
}
112-
113-
11487
#define MISA_SUPER (1 << ('S' - 'A'))
11588
#define MISA_USER (1 << ('U' - 'A'))
11689
#define MISA_I (1 << ('I' - 'A'))
@@ -285,6 +258,32 @@ enum TRAP_CODE {
285258
#define RV_PRIV_M_MODE 3
286259
#define RV_PRIV_IS_U_OR_S_MODE() (rv->priv_mode <= RV_PRIV_S_MODE)
287260

261+
enum TRAP_CODE {
262+
INSN_MISALIGNED = 0,
263+
ILLEGAL_INSN = 2,
264+
BREAKPOINT = 3,
265+
LOAD_MISALIGNED = 4,
266+
STORE_MISALIGNED = 6,
267+
PAGEFAULT_INSN = 12,
268+
PAGEFAULT_LOAD = 13,
269+
PAGEFAULT_STORE = 15,
270+
ECALL_M = 11,
271+
};
272+
273+
/* clang-format off */
274+
#define SET_CAUSE_AND_TVAL_THEN_TRAP(rv, cause, tval) \
275+
{ \
276+
/* \
277+
* To align rv32emu behavior with Spike \
278+
* \
279+
* If not in system mode, the __trap_handler \
280+
* should be be invoked \
281+
*/ \
282+
IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true;, ); \
283+
rv->io.on_trap(rv); \
284+
}
285+
/* clang-format on */
286+
288287
/*
289288
* SBI functions must return a pair of values:
290289
*

‎src/system.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -103,11 +103,11 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
103103
break; \
104104
} \
105105
if (pte && (!(*pte & PTE_V))) { \
106-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
106+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
107107
return false; \
108108
} \
109109
if (!(pte && (*pte & access_bits))) { \
110-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
110+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
111111
return false; \
112112
} \
113113
/* \
@@ -122,7 +122,7 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
122122
((SSTATUS_MXR & rv->csr_sstatus) && \
123123
!((*pte & PTE_R) | (*pte & PTE_X)) && \
124124
(access_bits == PTE_R)))) { \
125-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
125+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
126126
return false; \
127127
} \
128128
/* \
@@ -131,12 +131,12 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
131131
*/ \
132132
if (pte && rv->priv_mode == RV_PRIV_S_MODE && \
133133
!(SSTATUS_SUM & rv->csr_sstatus) && (*pte & PTE_U)) { \
134-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
134+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
135135
return false; \
136136
} \
137137
/* PTE not found, map it in handler */ \
138138
if (!pte) { \
139-
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
139+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
140140
return false; \
141141
} \
142142
/* valid PTE */ \

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