3
3
* "LICENSE" for information on usage and redistribution of this file.
4
4
*/
5
5
6
+ #if !RV32_HAS (SYSTEM )
7
+ #error "Do not manage to build this file unless you enable system support."
8
+ #endif
9
+
6
10
#include "riscv_private.h"
7
11
8
12
static bool ppn_is_valid (riscv_t * rv , uint32_t ppn )
@@ -153,8 +157,7 @@ MMU_FAULT_CHECK_IMPL(write, pagefault_store)
153
157
: addr & MASK(RV_PG_SHIFT); \
154
158
} while (0)
155
159
156
- /*
157
- * The IO handler that operates when the Memory Management Unit (MMU)
160
+ /* The IO handler that operates when the Memory Management Unit (MMU)
158
161
* is enabled during system emulation is responsible for managing
159
162
* input/output operations. These callbacks are designed to implement
160
163
* the riscv_io_t interface, ensuring compatibility and consistency to
@@ -178,9 +181,8 @@ static uint32_t mmu_ifetch(riscv_t *rv, const uint32_t addr)
178
181
uint32_t level ;
179
182
uint32_t * pte = mmu_walk (rv , addr , & level );
180
183
bool ok = MMU_FAULT_CHECK (ifetch , rv , pte , addr , PTE_X );
181
- if (unlikely (!ok )) {
184
+ if (unlikely (!ok ))
182
185
pte = mmu_walk (rv , addr , & level );
183
- }
184
186
185
187
get_ppn_and_offset ();
186
188
return memory_ifetch (ppn | offset );
@@ -194,9 +196,8 @@ static uint32_t mmu_read_w(riscv_t *rv, const uint32_t addr)
194
196
uint32_t level ;
195
197
uint32_t * pte = mmu_walk (rv , addr , & level );
196
198
bool ok = MMU_FAULT_CHECK (read , rv , pte , addr , PTE_R );
197
- if (unlikely (!ok )) {
199
+ if (unlikely (!ok ))
198
200
pte = mmu_walk (rv , addr , & level );
199
- }
200
201
201
202
get_ppn_and_offset ();
202
203
return memory_read_w (ppn | offset );
@@ -210,9 +211,8 @@ static uint16_t mmu_read_s(riscv_t *rv, const uint32_t addr)
210
211
uint32_t level ;
211
212
uint32_t * pte = mmu_walk (rv , addr , & level );
212
213
bool ok = MMU_FAULT_CHECK (read , rv , pte , addr , PTE_R );
213
- if (unlikely (!ok )) {
214
+ if (unlikely (!ok ))
214
215
pte = mmu_walk (rv , addr , & level );
215
- }
216
216
217
217
get_ppn_and_offset ();
218
218
return memory_read_s (ppn | offset );
@@ -226,9 +226,8 @@ static uint8_t mmu_read_b(riscv_t *rv, const uint32_t addr)
226
226
uint32_t level ;
227
227
uint32_t * pte = mmu_walk (rv , addr , & level );
228
228
bool ok = MMU_FAULT_CHECK (read , rv , pte , addr , PTE_R );
229
- if (unlikely (!ok )) {
229
+ if (unlikely (!ok ))
230
230
pte = mmu_walk (rv , addr , & level );
231
- }
232
231
233
232
get_ppn_and_offset ();
234
233
return memory_read_b (ppn | offset );
@@ -242,9 +241,8 @@ static void mmu_write_w(riscv_t *rv, const uint32_t addr, const uint32_t val)
242
241
uint32_t level ;
243
242
uint32_t * pte = mmu_walk (rv , addr , & level );
244
243
bool ok = MMU_FAULT_CHECK (write , rv , pte , addr , PTE_W );
245
- if (unlikely (!ok )) {
244
+ if (unlikely (!ok ))
246
245
pte = mmu_walk (rv , addr , & level );
247
- }
248
246
249
247
get_ppn_and_offset ();
250
248
memory_write_w (ppn | offset , (uint8_t * ) & val );
@@ -258,9 +256,8 @@ static void mmu_write_s(riscv_t *rv, const uint32_t addr, const uint16_t val)
258
256
uint32_t level ;
259
257
uint32_t * pte = mmu_walk (rv , addr , & level );
260
258
bool ok = MMU_FAULT_CHECK (write , rv , pte , addr , PTE_W );
261
- if (unlikely (!ok )) {
259
+ if (unlikely (!ok ))
262
260
pte = mmu_walk (rv , addr , & level );
263
- }
264
261
265
262
get_ppn_and_offset ();
266
263
memory_write_s (ppn | offset , (uint8_t * ) & val );
@@ -274,9 +271,8 @@ static void mmu_write_b(riscv_t *rv, const uint32_t addr, const uint8_t val)
274
271
uint32_t level ;
275
272
uint32_t * pte = mmu_walk (rv , addr , & level );
276
273
bool ok = MMU_FAULT_CHECK (write , rv , pte , addr , PTE_W );
277
- if (unlikely (!ok )) {
274
+ if (unlikely (!ok ))
278
275
pte = mmu_walk (rv , addr , & level );
279
- }
280
276
281
277
get_ppn_and_offset ();
282
278
memory_write_b (ppn | offset , (uint8_t * ) & val );
0 commit comments