test

Author: ChinYikMing

src/riscv.h

@@ -96,6 +96,21 @@ enum TRAP_CODE {
     ECALL_M = 11,
 };
 
+#define SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval) \
+    {                                                     \
+        /*                                                \
+         * To align rv32emu behavior with Spike           \
+         *                                                \
+         * If not in system mode, the __trap_handler      \
+         * should be be invoked                           \
+         */                                               \
+        IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true, );   \
+        rv->csr_scause = scause;                          \
+        rv->csr_stval = stval;                            \
+        rv->io.on_trap(rv);                               \
+    }
+
+
 #define MISA_SUPER (1 << ('S' - 'A'))
 #define MISA_USER (1 << ('U' - 'A'))
 #define MISA_I (1 << ('I' - 'A'))

src/system.h

@@ -7,20 +7,6 @@
 
 #include "riscv_private.h"
 
-#define SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval) \
-    {                                                     \
-        /*                                                \
-         * To align rv32emu behavior with Spike           \
-         *                                                \
-         * If not in system mode, the __trap_handler      \
-         * should be be invoked                           \
-         */                                               \
-        IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true, );   \
-        rv->csr_scause = scause;                          \
-        rv->csr_stval = stval;                            \
-        rv->io.on_trap(rv);                               \
-    }
-
 /* PTE XWRV bit in order */
 enum SV32_PTE_PERM {
     NEXT_PG_TBL = 0b0001,