@@ -42,7 +42,9 @@ extern struct target_ops gdbstub_ops;
4242#define IF_imm (i , v ) (i->imm == v)
4343
4444#if RV32_HAS (SYSTEM )
45+ #if !RV32_HAS (JIT )
4546static bool need_clear_block_map = false;
47+ #endif
4648static uint32_t reloc_enable_mmu_jalr_addr ;
4749static bool reloc_enable_mmu = false;
4850bool need_retranslate = false;
@@ -79,14 +81,14 @@ static void __trap_handler(riscv_t *rv);
7981 }
8082
8183/* FIXME: use more precise methods for updating time, e.g., RTC */
84+ #if RV32_HAS (Zicsr )
8285static uint64_t ctr = 0 ;
8386static inline void update_time (riscv_t * rv )
8487{
8588 rv -> csr_time [0 ] = ctr & 0xFFFFFFFF ;
8689 rv -> csr_time [1 ] = ctr >> 32 ;
8790}
8891
89- #if RV32_HAS (Zicsr )
9092/* get a pointer to a CSR */
9193static uint32_t * csr_get_ptr (riscv_t * rv , uint32_t csr )
9294{
@@ -374,42 +376,45 @@ static uint32_t peripheral_update_ctr = 64;
374376#endif
375377
376378/* Interpreter-based execution path */
377- #define RVOP (inst , code , asm ) \
378- static bool do_##inst(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, \
379- uint32_t PC) \
380- { \
381- IIF(RV32_HAS(SYSTEM))(ctr++;, ) cycle++; \
382- code; \
383- IIF(RV32_HAS(SYSTEM)) \
384- ( \
385- if (need_handle_signal) { \
386- need_handle_signal = false; \
387- return true; \
388- }, ) nextop : PC += __rv_insn_##inst##_len; \
389- IIF(RV32_HAS(SYSTEM)) \
390- (IIF(RV32_HAS(JIT))( \
391- , if (unlikely(need_clear_block_map)) { \
392- block_map_clear(rv); \
393- need_clear_block_map = false; \
394- rv->csr_cycle = cycle; \
395- rv->PC = PC; \
396- return false; \
397- }), ); \
398- if (unlikely(RVOP_NO_NEXT(ir))) \
399- goto end_op; \
400- const rv_insn_t *next = ir->next; \
401- MUST_TAIL return next->impl(rv, next, cycle, PC); \
402- end_op: \
403- rv->csr_cycle = cycle; \
404- rv->PC = PC; \
405- return true; \
379+ #define RVOP (inst , code , asm ) \
380+ static bool do_##inst(riscv_t *rv, const rv_insn_t *ir, uint64_t cycle, \
381+ uint32_t PC) \
382+ { \
383+ IIF(RV32_HAS(SYSTEM))(ctr++;, ) cycle++; \
384+ code; \
385+ IIF(RV32_HAS(SYSTEM)) \
386+ ( \
387+ if (need_handle_signal) { \
388+ need_handle_signal = false; \
389+ return true; \
390+ }, ) nextop : PC += __rv_insn_##inst##_len; \
391+ IIF(RV32_HAS(SYSTEM)) \
392+ (IIF(RV32_HAS(JIT))( \
393+ , if (unlikely(need_clear_block_map)) { \
394+ block_map_clear(rv); \
395+ need_clear_block_map = false; \
396+ rv->csr_cycle = cycle; \
397+ rv->PC = PC; \
398+ return false; \
399+ }), ); \
400+ if (unlikely(RVOP_NO_NEXT(ir))) \
401+ goto end_op; \
402+ const rv_insn_t *next = ir->next; \
403+ MUST_TAIL return next->impl(rv, next, cycle, PC); \
404+ end_op: \
405+ rv->csr_cycle = cycle; \
406+ rv->PC = PC; \
407+ return true; \
406408 }
407409
408410#include "rv32_template.c"
409411#undef RVOP
410412
411413/* multiple LUI */
412- static bool do_fuse1 (riscv_t * rv , rv_insn_t * ir , uint64_t cycle , uint32_t PC )
414+ static bool do_fuse1 (riscv_t * rv ,
415+ const rv_insn_t * ir ,
416+ uint64_t cycle ,
417+ uint32_t PC )
413418{
414419 cycle += ir -> imm2 ;
415420 opcode_fuse_t * fuse = ir -> fuse ;
@@ -426,7 +431,10 @@ static bool do_fuse1(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
426431}
427432
428433/* LUI + ADD */
429- static bool do_fuse2 (riscv_t * rv , rv_insn_t * ir , uint64_t cycle , uint32_t PC )
434+ static bool do_fuse2 (riscv_t * rv ,
435+ const rv_insn_t * ir ,
436+ uint64_t cycle ,
437+ uint32_t PC )
430438{
431439 cycle += 2 ;
432440 rv -> X [ir -> rd ] = ir -> imm ;
@@ -442,7 +450,10 @@ static bool do_fuse2(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
442450}
443451
444452/* multiple SW */
445- static bool do_fuse3 (riscv_t * rv , rv_insn_t * ir , uint64_t cycle , uint32_t PC )
453+ static bool do_fuse3 (riscv_t * rv ,
454+ const rv_insn_t * ir ,
455+ uint64_t cycle ,
456+ uint32_t PC )
446457{
447458 cycle += ir -> imm2 ;
448459 opcode_fuse_t * fuse = ir -> fuse ;
@@ -466,7 +477,10 @@ static bool do_fuse3(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
466477}
467478
468479/* multiple LW */
469- static bool do_fuse4 (riscv_t * rv , rv_insn_t * ir , uint64_t cycle , uint32_t PC )
480+ static bool do_fuse4 (riscv_t * rv ,
481+ const rv_insn_t * ir ,
482+ uint64_t cycle ,
483+ uint32_t PC )
470484{
471485 cycle += ir -> imm2 ;
472486 opcode_fuse_t * fuse = ir -> fuse ;
@@ -550,6 +564,7 @@ FORCE_INLINE bool insn_is_translatable(uint8_t opcode)
550564}
551565#endif
552566
567+ #if RV32_HAS (BLOCK_CHAINING )
553568FORCE_INLINE bool insn_is_unconditional_branch (uint8_t opcode )
554569{
555570 switch (opcode ) {
@@ -558,7 +573,9 @@ FORCE_INLINE bool insn_is_unconditional_branch(uint8_t opcode)
558573 case rv_insn_jal :
559574 case rv_insn_jalr :
560575 case rv_insn_mret :
576+ #if RV32_HAS (Zicsr )
561577 case rv_insn_csrrw :
578+ #endif
562579#if RV32_HAS (SYSTEM )
563580 case rv_insn_sret :
564581#endif
@@ -588,6 +605,7 @@ FORCE_INLINE bool insn_is_direct_branch(uint8_t opcode)
588605 return false;
589606 }
590607}
608+ #endif
591609
592610FORCE_INLINE bool insn_is_indirect_branch (uint8_t opcode )
593611{
@@ -664,6 +682,7 @@ static void block_translate(riscv_t *rv, block_t *block)
664682 block -> ir_tail -> next = NULL ;
665683}
666684
685+ #if RV32_HAS (MOP_FUSION )
667686#define COMBINE_MEM_OPS (RW ) \
668687 next_ir = ir->next; \
669688 count = 1; \
@@ -800,6 +819,7 @@ static void match_pattern(riscv_t *rv, block_t *block)
800819 }
801820 }
802821}
822+ #endif
803823
804824typedef struct {
805825 bool is_constant [N_RV_REGS ];
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