Add L1 block cache and direct-mapped BHT

This introduces two lookup optimizations:
1. L1 Direct-Mapped Block Cache (256 entries, interpreter only):
  - Separated tag/pointer arrays: tag array (1KB) checked first, pointer
    loaded only on hit for cache efficiency
  - Invalid tag sentinel (0xFFFFFFFF) for clean miss detection
  - EXT_C-aware index shift (1 vs 2 bits) to reduce conflict misses
  - New block_lookup_or_find() as primary lookup with hash fallback
2. Direct-Mapped Branch History Table (both JIT and non-JIT):
  - O(1) lookup replacing O(n) linear search: index = (PC >> 2) & mask
  - Remove idx field (non-JIT) and bht_find_min_idx() - no longer needed
  - Update bht_find_max_idx() to scan all entries since zeros can appear
    at any index with direct-mapped scheme
  - Add static assert for power-of-2 HISTORY_SIZE

Benchmarks on Intel Xeon E5-2650:
- CoreMark: 804.66 -> ~887 iterations/sec (+10.2%)
- Dhrystone: 1366 -> ~1382 DMIPS (+1.2%)

Author: jserv

src/decode.h

@@ -366,49 +366,38 @@ _Static_assert(offsetof(opcode_fuse_t, opcode) == 7,
                "opcode_fuse_t.opcode must be at offset 7");
 
 #define HISTORY_SIZE 16
+/* Direct-mapped BHT requires power-of-2 size for mask calculation */
+_Static_assert((HISTORY_SIZE & (HISTORY_SIZE - 1)) == 0,
+               "HISTORY_SIZE must be a power of 2");
+
 typedef struct {
-    uint32_t PC[HISTORY_SIZE];
+    uint32_t PC[HISTORY_SIZE]; /**< PC tags for direct-mapped lookup */
 #if !RV32_HAS(JIT)
-    uint8_t idx;
-    struct rv_insn *target[HISTORY_SIZE];
+    struct rv_insn *target[HISTORY_SIZE]; /**< target IR pointers */
 #else
-    uint32_t times[HISTORY_SIZE];
+    uint32_t times[HISTORY_SIZE]; /**< access counts for JIT hotness */
 #if RV32_HAS(SYSTEM)
-    uint32_t satp[HISTORY_SIZE];
+    uint32_t satp[HISTORY_SIZE]; /**< SATP for address space matching */
 #endif
 #endif
 } branch_history_table_t;
 
 #if RV32_HAS(JIT)
 /* Find index with maximum times count in branch history table.
  * Used by JIT to identify the most frequently taken indirect jump target.
+ * Note: With direct-mapped BHT, zeros can appear at any index, so we must
+ * scan all entries (cannot break early on first zero).
  */
 static inline int bht_find_max_idx(const branch_history_table_t *bt)
 {
     int max_idx = 0;
-    for (int i = 0; i < HISTORY_SIZE; i++) {
-        if (!bt->times[i])
-            break;
-        if (bt->times[max_idx] < bt->times[i])
+    for (int i = 1; i < HISTORY_SIZE; i++) {
+        if (bt->times[i] > bt->times[max_idx])
             max_idx = i;
     }
     return max_idx;
 }
 
-/* Find index with minimum times count for LFU replacement.
- * Returns first empty slot if available, otherwise the least frequently used.
- */
-static inline int bht_find_min_idx(const branch_history_table_t *bt)
-{
-    int min_idx = 0;
-    for (int i = 0; i < HISTORY_SIZE; i++) {
-        if (!bt->times[i])
-            return i; /* empty slot found */
-        if (bt->times[min_idx] > bt->times[i])
-            min_idx = i;
-    }
-    return min_idx;
-}
 #endif
 
 typedef struct rv_insn {

src/emulate.c

@@ -530,8 +530,18 @@ static block_t *block_alloc(riscv_t *rv)
 }
 
 #if !RV32_HAS(JIT)
+/* Update L1 direct-mapped block cache.
+ * Called after block insertion to enable fast lookup for hot paths.
+ */
+static inline void block_l1_update(riscv_t *rv, block_t *block)
+{
+    uint32_t idx = (block->pc_start >> BLOCK_L1_INDEX_SHIFT) & BLOCK_L1_MASK;
+    rv->block_l1.tags[idx] = block->pc_start;
+    rv->block_l1.ptrs[idx] = block;
+}
+
 /* insert a block into block map */
-static void block_insert(block_map_t *map, const block_t *block)
+static void block_insert(block_map_t *map, riscv_t *rv, const block_t *block)
 {
     assert(map && block);
     const uint32_t mask = map->block_capacity - 1;
@@ -545,6 +555,9 @@ static void block_insert(block_map_t *map, const block_t *block)
         }
     }
     map->size++;
+
+    /* update L1 cache for fast subsequent lookups */
+    block_l1_update(rv, (block_t *) block);
 }
 
 /* try to locate an already translated block in the block map */
@@ -565,6 +578,32 @@ static block_t *block_find(const block_map_t *map, const uint32_t addr)
     }
     return NULL;
 }
+
+/* Fast block lookup using L1 direct-mapped cache.
+ * Falls back to hash table on L1 miss.
+ * This is the hot path - optimized for tight loops.
+ *
+ * Separated arrays: tag array checked first (1KB), pointer loaded on hit.
+ * Benchmarked faster than interleaved on x86-64.
+ */
+static inline block_t *block_lookup_or_find(riscv_t *rv, uint32_t pc)
+{
+    /* L1 cache lookup - check tag first (avoids loading pointer on miss) */
+    uint32_t idx = (pc >> BLOCK_L1_INDEX_SHIFT) & BLOCK_L1_MASK;
+    if (likely(rv->block_l1.tags[idx] == pc))
+        return rv->block_l1.ptrs[idx];
+
+    /* L1 miss - fall back to hash table lookup */
+    block_t *block = block_find(&rv->block_map, pc);
+
+    /* Populate L1 cache on hash table hit for future lookups */
+    if (block) {
+        rv->block_l1.tags[idx] = pc;
+        rv->block_l1.ptrs[idx] = block;
+    }
+
+    return block;
+}
 #endif
 
 #if !RV32_HAS(EXT_C)
@@ -1808,8 +1847,8 @@ static block_t *block_find_or_translate(riscv_t *rv)
 {
 #if !RV32_HAS(JIT)
     block_map_t *map = &rv->block_map;
-    /* lookup the next block in the block map */
-    block_t *next_blk = block_find(map, rv->PC);
+    /* lookup the next block using L1 cache with hash table fallback */
+    block_t *next_blk = block_lookup_or_find(rv, rv->PC);
 #else
     /* lookup the next block in the block cache */
     block_t *next_blk = (block_t *) cache_get(rv->block_cache, rv->PC, true);
@@ -1861,8 +1900,8 @@ static block_t *block_find_or_translate(riscv_t *rv)
 #endif
 
 #if !RV32_HAS(JIT)
-    /* insert the block into block map */
-    block_insert(&rv->block_map, next_blk);
+    /* insert the block into block map and L1 cache */
+    block_insert(&rv->block_map, rv, next_blk);
 #else
     list_add(&next_blk->list, &rv->block_list);
 
@@ -2096,7 +2135,7 @@ void rv_step(void *arg)
         if (prev && prev->pc_start != last_pc) {
             /* update previous block */
 #if !RV32_HAS(JIT)
-            prev = block_find(&rv->block_map, last_pc);
+            prev = block_lookup_or_find(rv, last_pc);
 #else
             prev = cache_get(rv->block_cache, last_pc, false);
 #endif

src/riscv.c

@@ -80,6 +80,14 @@ void block_map_clear(riscv_t *rv)
         map->map[i] = NULL;
     }
     map->size = 0;
+
+    /* clear L1 direct-mapped block cache - use invalid tags to avoid
+     * false hits on PC=0 edge case. Separated arrays: tags first for
+     * cache-efficient miss detection, ptrs zeroed with memset.
+     */
+    for (int i = 0; i < BLOCK_L1_SIZE; i++)
+        rv->block_l1.tags[i] = BLOCK_L1_INVALID_TAG;
+    memset(rv->block_l1.ptrs, 0, sizeof(rv->block_l1.ptrs));
 }
 
 static void block_map_destroy(riscv_t *rv)
@@ -872,6 +880,11 @@ riscv_t *rv_create(riscv_user_t rv_attr)
 #if !RV32_HAS(JIT)
     /* initialize the block map */
     block_map_init(&rv->block_map, BLOCK_MAP_CAPACITY_BITS);
+
+    /* initialize L1 block cache with invalid tags */
+    for (int i = 0; i < BLOCK_L1_SIZE; i++)
+        rv->block_l1.tags[i] = BLOCK_L1_INVALID_TAG;
+    memset(rv->block_l1.ptrs, 0, sizeof(rv->block_l1.ptrs));
 #else
     INIT_LIST_HEAD(&rv->block_list);
     rv->jit_state = jit_state_init(CODE_CACHE_SIZE);

src/riscv_private.h

@@ -188,29 +188,72 @@ typedef struct {
     block_t **map;           /**< block map */
 } block_map_t;
 
+/* L1 direct-mapped block cache for fast block lookup.
+ * Inspired by rvdbt's tcache.h design.
+ * Expected gain: 5-15% by avoiding hash table lookup for hot loops.
+ *
+ * Design: Separated tag/pointer arrays for cache efficiency.
+ * - Tag array (1KB) checked first - fits in L1, good for miss path
+ * - Pointer array (2KB) loaded only on hit
+ * - Benchmarked faster than interleaved on x86-64 (+11.9% vs +8.8%)
+ */
+#define BLOCK_L1_SIZE 256
+#define BLOCK_L1_MASK (BLOCK_L1_SIZE - 1)
+
+/* Index shift for L1 cache lookup.
+ * With EXT_C: PCs can be half-word aligned, shift by 1 to use bit 1.
+ * Without EXT_C: PCs are word-aligned, shift by 2.
+ * Using correct shift reduces conflict misses in compressed code.
+ */
+#if RV32_HAS(EXT_C)
+#define BLOCK_L1_INDEX_SHIFT 1
+#else
+#define BLOCK_L1_INDEX_SHIFT 2
+#endif
+
+/* Cache line size for alignment (typical x86/Arm64). */
+#define CACHE_LINE_SIZE 64
+
+/* Invalid tag sentinel - guaranteed never to match a valid PC.
+ * Valid RISC-V PCs are word-aligned (or half-word for C extension),
+ * so a value with low bits set is always invalid.
+ */
+#define BLOCK_L1_INVALID_TAG 0xFFFFFFFFu
+
+/* L1 block cache with separated arrays for cache efficiency.
+ * Tag array checked first (1KB), pointer loaded only on hit (2KB).
+ * Separated layout benchmarked faster than interleaved on x86-64.
+ */
+typedef struct {
+    uint32_t tags[BLOCK_L1_SIZE]; /**< PC tags for fast comparison */
+    block_t *ptrs[BLOCK_L1_SIZE]; /**< block pointers, loaded on tag hit */
+} block_l1_cache_t;
+
 /* clear all block in the block map */
 void block_map_clear(riscv_t *rv);
 
 struct riscv_internal {
-    bool halt; /* indicate whether the core is halted */
+    bool halt; /**< indicate whether the core is halted */
 
-    /* integer registers */
-    /*
-     * Aarch64 encoder only accepts 9 bits signed offset. Do not put this
-     * structure below the section.
-     */
+    /* Integer registers - Aarch64 encoder needs 9-bit signed offset access */
     riscv_word_t X[N_RV_REGS];
     riscv_word_t PC;
 
-    uint64_t timer; /* strictly increment timer */
+    uint64_t timer; /**< strictly increment timer */
 
 #if RV32_HAS(SYSTEM)
-    /* is_trapped must be within 256-byte offset for ARM64 JIT access.
-     * Placed early in struct to ensure accessibility from JIT-generated code.
-     */
+    /* is_trapped must be within 256-byte offset for ARM64 JIT access */
     bool is_trapped;
 #endif
 
+#if !RV32_HAS(JIT)
+    /* L1 block cache - tag/pointer separation for cache efficiency.
+     * Tags checked first (1KB), pointers loaded only on hit (2KB).
+     * Placed near hot fields for interpreter fast path.
+     */
+    block_l1_cache_t block_l1 __ALIGNED(CACHE_LINE_SIZE);
+#endif
+
 #if RV32_HAS(JIT) && RV32_HAS(SYSTEM)
     /*
      * Aarch64 encoder only accepts 9 bits signed offset. Do not put this
@@ -270,7 +313,7 @@ struct riscv_internal {
 
     bool compressed; /**< current instruction is compressed or not */
 #if !RV32_HAS(JIT)
-    block_map_t block_map; /**< basic block map */
+    block_map_t block_map; /**< basic block map (fallback on L1 miss) */
 #else
     struct cache *block_cache;
     struct list_head block_list; /**< list of all translated blocks */

src/rv32_template.c

@@ -104,7 +104,7 @@ RVOP(jal, {
 #if !RV32_HAS(JIT)
 #define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE()                                \
     /*                                                                         \
-     * lookup branch history table                                             \
+     * Direct-mapped branch history table lookup.                              \
      *                                                                         \
      * When handling trap, the branch history table should not be lookup since \
      * it causes return from the trap_handler.                                 \
@@ -116,20 +116,18 @@ RVOP(jal, {
     {                                                                          \
         IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), ))     \
         {                                                                      \
-            for (int i = 0; i < HISTORY_SIZE; i++) {                           \
-                if (ir->branch_table->PC[i] == PC) {                           \
-                    MUST_TAIL return ir->branch_table->target[i]->impl(        \
-                        rv, ir->branch_table->target[i], cycle, PC);           \
-                }                                                              \
+            /* Direct-mapped lookup: O(1) instead of O(n) linear search */     \
+            const uint32_t bht_idx = (PC >> 2) & (HISTORY_SIZE - 1);           \
+            if (ir->branch_table->PC[bht_idx] == PC &&                         \
+                ir->branch_table->target[bht_idx]) {                           \
+                MUST_TAIL return ir->branch_table->target[bht_idx]->impl(      \
+                    rv, ir->branch_table->target[bht_idx], cycle, PC);         \
             }                                                                  \
             block_t *block = block_find(&rv->block_map, PC);                   \
             if (block) {                                                       \
-                /* update branch history table */                              \
-                ir->branch_table->PC[ir->branch_table->idx] = PC;              \
-                ir->branch_table->target[ir->branch_table->idx] =              \
-                    block->ir_head;                                            \
-                ir->branch_table->idx =                                        \
-                    (ir->branch_table->idx + 1) % HISTORY_SIZE;                \
+                /* Direct replacement at computed index */                     \
+                ir->branch_table->PC[bht_idx] = PC;                            \
+                ir->branch_table->target[bht_idx] = block->ir_head;            \
                 MUST_TAIL return block->ir_head->impl(rv, block->ir_head,      \
                                                       cycle, PC);              \
             }                                                                  \
@@ -141,23 +139,22 @@ RVOP(jal, {
     {                                                                        \
         block_t *block = cache_get(rv->block_cache, PC, true);               \
         if (block) {                                                         \
-            for (int i = 0; i < HISTORY_SIZE; i++) {                         \
-                if (ir->branch_table->PC[i] == PC) {                         \
-                    IIF(RV32_HAS(SYSTEM))(                                   \
-                        if (ir->branch_table->satp[i] == rv->csr_satp), )    \
-                    {                                                        \
-                        ir->branch_table->times[i]++;                        \
-                        if (cache_hot(rv->block_cache, PC))                  \
-                            goto end_op;                                     \
-                    }                                                        \
+            /* Direct-mapped lookup: O(1) instead of O(n) linear search */   \
+            const uint32_t bht_idx = (PC >> 2) & (HISTORY_SIZE - 1);         \
+            if (ir->branch_table->PC[bht_idx] == PC) {                       \
+                IIF(RV32_HAS(SYSTEM))(                                       \
+                    if (ir->branch_table->satp[bht_idx] == rv->csr_satp), )  \
+                {                                                            \
+                    ir->branch_table->times[bht_idx]++;                      \
+                    if (cache_hot(rv->block_cache, PC))                      \
+                        goto end_op;                                         \
                 }                                                            \
             }                                                                \
-            /* update branch history table using LFU replacement */          \
-            int min_idx = bht_find_min_idx(ir->branch_table);                \
-            ir->branch_table->times[min_idx] = 1;                            \
-            ir->branch_table->PC[min_idx] = PC;                              \
+            /* Direct replacement at computed index */                       \
+            ir->branch_table->times[bht_idx] = 1;                            \
+            ir->branch_table->PC[bht_idx] = PC;                              \
             IIF(RV32_HAS(SYSTEM))(                                           \
-                ir->branch_table->satp[min_idx] = rv->csr_satp, );           \
+                ir->branch_table->satp[bht_idx] = rv->csr_satp, );           \
             if (cache_hot(rv->block_cache, PC))                              \
                 goto end_op;                                                 \
             MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, \