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Add Arm64 TSAN support and fix JIT cache coherency
This commit adds ThreadSanitizer (TSAN) support for ARM64/Apple Silicon and fixes critical JIT instruction cache coherency issues. ARM64 TSAN Support: - Extended TSAN-compatible memory allocation to ARM64 architecture - Main memory allocated at fixed address 0x150000000000 (21TB) - JIT buffer allocated at 0x151000000000 with MAP_JIT for Apple Silicon - Both allocations avoid TSAN shadow memory and enable race detection - Note: Requires ASLR disabled on macOS (SIP restrictions may apply) JIT Cache Coherency Fixes: 1. Fixed pthread_jit_write_protect_np() ordering in update_branch_imm 2. Added sys_icache_invalidate() in update_branch_imm 3. Added cache invalidation in resolve_jumps() for x86_64
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src/io.c

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -27,18 +27,32 @@ memory_t *memory_new(uint32_t size)
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return NULL;
2828
assert(mem);
2929
#if HAVE_MMAP
30-
#if defined(TSAN_ENABLED) && defined(__x86_64__)
30+
#if defined(TSAN_ENABLED)
3131
/* ThreadSanitizer compatibility: Use MAP_FIXED to allocate at a specific
32-
* address within TSAN's app range (0x7cf000000000 - 0x7ffffffff000).
32+
* address to avoid conflicts with TSAN's shadow memory.
33+
*/
34+
#if defined(__x86_64__)
35+
/* x86_64: Allocate within TSAN's range (0x7cf000000000 - 0x7ffffffff000).
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*
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* Fixed address: 0x7d0000000000
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* Size: up to 4GB (0x100000000)
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* End: 0x7d0100000000 (well within app range)
37-
*
38-
* This guarantees the allocation won't land in TSAN's shadow memory,
39-
* preventing "unexpected memory mapping" errors.
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*/
4141
void *fixed_addr = (void *) 0x7d0000000000UL;
42+
#elif defined(__aarch64__)
43+
/* ARM64 (macOS/Apple Silicon): Use higher address range.
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*
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* Fixed address: 0x150000000000 (21TB)
46+
* Size: up to 4GB (0x100000000)
47+
* End: 0x150100000000
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*
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* This avoids TSAN's shadow memory and typical process allocations.
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* Requires ASLR disabled via: setarch $(uname -m) -R
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*/
52+
void *fixed_addr = (void *) 0x150000000000UL;
53+
#else
54+
#error "TSAN is only supported on x86_64 and aarch64"
55+
#endif
4256
data_memory_base = mmap(fixed_addr, size, PROT_READ | PROT_WRITE,
4357
MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED, -1, 0);
4458
if (data_memory_base == MAP_FAILED) {

src/jit.c

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2336,10 +2336,12 @@ struct jit_state *jit_state_init(size_t size)
23362336

23372337
state->offset = 0;
23382338
state->size = size;
2339-
#if defined(TSAN_ENABLED) && defined(__x86_64__)
2339+
#if defined(TSAN_ENABLED)
23402340
/* ThreadSanitizer compatibility: Allocate JIT code buffer at a fixed
23412341
* address above the main memory region to avoid conflicts.
2342-
*
2342+
*/
2343+
#if defined(__x86_64__)
2344+
/* x86_64 memory layout:
23432345
* Main memory: 0x7d0000000000 - 0x7d0100000000 (4GB for FULL4G)
23442346
* JIT buffer: 0x7d1000000000 + size
23452347
*
@@ -2349,6 +2351,26 @@ struct jit_state *jit_state_init(size_t size)
23492351
void *jit_addr = (void *) 0x7d1000000000UL;
23502352
state->buf = mmap(jit_addr, size, PROT_READ | PROT_WRITE | PROT_EXEC,
23512353
MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED, -1, 0);
2354+
#elif defined(__aarch64__)
2355+
/* ARM64 memory layout (macOS/Apple Silicon):
2356+
* Main memory: 0x150000000000 - 0x150100000000 (4GB for FULL4G)
2357+
* JIT buffer: 0x151000000000 + size
2358+
*
2359+
* Apple Silicon requires MAP_JIT for executable memory. The fixed
2360+
* address is chosen to avoid TSAN's shadow memory and typical process
2361+
* allocations. Requires ASLR disabled via: setarch $(uname -m) -R
2362+
*/
2363+
void *jit_addr = (void *) 0x151000000000UL;
2364+
state->buf = mmap(jit_addr, size, PROT_READ | PROT_WRITE | PROT_EXEC,
2365+
MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED
2366+
#if defined(__APPLE__)
2367+
| MAP_JIT
2368+
#endif
2369+
,
2370+
-1, 0);
2371+
#else
2372+
#error "TSAN is only supported on x86_64 and aarch64"
2373+
#endif
23522374
if (state->buf == MAP_FAILED) {
23532375
free(state);
23542376
return NULL;

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