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2 parents 0aceed0 + 6ed2748 commit 78e0011Copy full SHA for 78e0011
scripts/gen-hart-dts.py
@@ -56,7 +56,6 @@ def dtsi_template (cpu_list: str, plic_list, clint_list, clock_freq):
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clint0: clint@4300000 {{
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compatible = "riscv,clint0";
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- interrupt-controller;
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interrupts-extended =
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{clint_list};
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reg = <0x4300000 0x10000>;
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