From 991d86375c691790c249d1f92a0286a9d7da6707 Mon Sep 17 00:00:00 2001 From: Mes Date: Mon, 29 Sep 2025 23:21:09 +0800 Subject: [PATCH] Correct MSWI/MTIMER interrupt IDs in ACLINT The DTS previously set the MSWI and MTIMER interrupt numbers incorrectly, which appears in the 'interrupts-extended' fields of the MSWI and MTIMER nodes in 'riscv-harts.dtsi'. The Linux guests didn't break before because both the timer and IPIs are exercised via SBI calls, and the emulator services them through the SBI handlers rather than by relying on OS-visible IRQ wiring. That masked the DTS error. Nevertheless, fixing the mapping prevents confusion during future bring-up and aligns with the RISC-V interrupt numbering. --- scripts/gen-hart-dts.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/gen-hart-dts.py b/scripts/gen-hart-dts.py index 03cebbc..c7a896f 100644 --- a/scripts/gen-hart-dts.py +++ b/scripts/gen-hart-dts.py @@ -46,7 +46,7 @@ def mtimer_irq_format(nums): s += f"<&cpu{i}_intc 7>, " # 7 is the MTIMER interrupt number (Machine Timer Interrupt) return s[:-2] -def dtsi_template (cpu_list: str, plic_list, sswi_list, mtimer_list, mswi_list, clock_freq): +def dtsi_template (cpu_list: str, plic_list, sswi_list, mswi_list, mtimer_list, clock_freq): return f"""/{{ cpus {{ #address-cells = <1>;