Fix OP_sign_ext source size detection by encoding both sizes

- Encode both source and target sizes in OP_sign_ext src1 parameter:
  * Lower 16 bits: target type size
  * Upper 16 bits: source type size
- Update ARM and RISC-V codegen to decode size information properly
- Calculate precise shift amounts using both source and target sizes
- Fix short integer overflow behavior (32767 + 2 = -32767)
- Update snapshots to reflect new IR encoding format
- Maintain IR semantic compatibility without structural changes

Author: hhhh1300

src/arm-codegen.c

@@ -451,13 +451,16 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
             fatal("Unsupported truncation operation with invalid target size");
         }
         return;
-    case OP_sign_ext:
-        if (rm == 2) {
+    case OP_sign_ext: {
+        /* Decode source size from upper 16 bits */
+        int source_size = (rm >> 16) & 0xFFFF;
+        if (source_size == 2) {
             emit(__sxth(__AL, rd, rn, 0));
         } else {
             /* For other cases, use byte extension (original behavior) */
             emit(__sxtb(__AL, rd, rn, 0));
         }
+    }
         return;
     case OP_cast:
         /* Generic cast operation - for now, just move the value */

src/parser.c

@@ -247,12 +247,18 @@ var_t *promote_unchecked(block_t *block,
 {
     var_t *rd = require_typed_ptr_var(block, target_type, target_ptr);
     gen_name_to(rd->var_name);
-    /* TODO: Use source type size instead of target type size for
-     * sign extension. The OP_sign_ext instruction may need both
-     * source and target sizes for proper code generation.
+    /* Encode both source and target sizes in src1:
+     * Lower 16 bits: target size
+     * Upper 16 bits: source size
+     * This allows codegen to distinguish between different promotion types
+     * without changing IR semantics.
      */
-    add_insn(block, *bb, OP_sign_ext, rd, var, NULL,
-             target_ptr ? PTR_SIZE : var->type->size, NULL);
+    int encoded_size = ((var->type->size) << 16);
+    if (target_ptr)
+        encoded_size |= PTR_SIZE;
+    else
+        encoded_size |= target_type->size;
+    add_insn(block, *bb, OP_sign_ext, rd, var, NULL, encoded_size, NULL);
     return rd;
 }
 

src/riscv-codegen.c

@@ -100,12 +100,15 @@ void update_elf_offset(ph2_ir_t *ph2_ir)
         else
             elf_offset += 4;
         return;
-    case OP_sign_ext:
-        if (ph2_ir->src1 == 2)
-            elf_offset += 8;
+    case OP_sign_ext: {
+        /* Decode source size from upper 16 bits */
+        int source_size = (ph2_ir->src1 >> 16) & 0xFFFF;
+        if (source_size == 2)
+            elf_offset += 8; /* short extension: 2 instructions */
         else
-            elf_offset += 12;
+            elf_offset += 12; /* byte extension: 3 instructions */
         return;
+    }
     case OP_cast:
         elf_offset += 4;
         return;
@@ -443,20 +446,31 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
             fatal("Unsupported truncation operation with invalid target size");
         }
         return;
-    case OP_sign_ext:
-        if (ph2_ir->src1 == 2) {
-            /* Sign extend from short to word
+    case OP_sign_ext: {
+        /* Decode size information:
+         * Lower 16 bits: target size
+         * Upper 16 bits: source size
+         */
+        int target_size = ph2_ir->src1 & 0xFFFF;
+        int source_size = (ph2_ir->src1 >> 16) & 0xFFFF;
+
+        /* Calculate shift amount based on target and source sizes */
+        int shift_amount = (target_size - source_size) * 8;
+
+        if (source_size == 2) {
+            /* Sign extend from short to word (16-bit shift)
              * For 16-bit sign extension, use only shift operations
              * since 0xFFFF is too large for RISC-V immediate field
              */
-            emit(__slli(rd, rs1, 16));
-            emit(__srai(rd, rd, 16));
+            emit(__slli(rd, rs1, shift_amount));
+            emit(__srai(rd, rd, shift_amount));
         } else {
-            /* Sign extend from byte to word (src1 == 1) or fallback */
+            /* Fallback for other sizes */
             emit(__andi(rd, rs1, 0xFF));
-            emit(__slli(rd, rd, 24));
-            emit(__srai(rd, rd, 24));
+            emit(__slli(rd, rd, shift_amount));
+            emit(__srai(rd, rd, shift_amount));
         }
+    }
         return;
     case OP_cast:
         /* Generic cast operation - for now, just move the value */