Implement RISC-V short type code generation

Add RISC-V halfword instruction support for short data type
operations with proper truncation and sign extension.

- Fix OP_trunc for short types using shift operations instead
  of large immediate values that exceed instruction limits
- Implement OP_sign_ext for short-to-int sign extension using
  arithmetic shift operations
- Update halfword operations to handle 2-byte reads correctly

RISC-V short type operations now generate correct instruction
sequences with proper bit manipulation and sign extension.

Author: hhhh1300

src/riscv-codegen.c

@@ -95,7 +95,10 @@ void update_elf_offset(ph2_ir_t *ph2_ir)
         elf_offset += 24;
         return;
     case OP_trunc:
-        elf_offset += 4;
+        if (ph2_ir->src1 == 2)
+            elf_offset += 8;
+        else
+            elf_offset += 4;
         return;
     case OP_sign_ext:
         elf_offset += 12;
@@ -233,6 +236,8 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
     case OP_read:
         if (ph2_ir->src1 == 1)
             emit(__lb(rd, rs1, 0));
+        else if (ph2_ir->src1 == 2)
+            emit(__lh(rd, rs1, 0));
         else if (ph2_ir->src1 == 4)
             emit(__lw(rd, rs1, 0));
         else
@@ -241,6 +246,8 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
     case OP_write:
         if (ph2_ir->dest == 1)
             emit(__sb(rs2, rs1, 0));
+        else if (ph2_ir->dest == 2)
+            emit(__sh(rs2, rs1, 0));
         else if (ph2_ir->dest == 4)
             emit(__sw(rs2, rs1, 0));
         else
@@ -417,24 +424,39 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
         emit(__xori(rd, rd, 1));
         return;
     case OP_trunc:
-        if (ph2_ir->src1 == 1)
+        if (ph2_ir->src1 == 1) {
             rs2 = 0xFF;
-        else if (ph2_ir->src1 == 2)
-            rs2 = 0xFFFF;
-        else if (ph2_ir->src1 == 4)
-            rs2 = 0xFFFFFFFF;
-        else
+            emit(__andi(rd, rs1, rs2));
+        } else if (ph2_ir->src1 == 2) {
+            /* For short truncation,
+             * use shift operations since 0xFFFF is too large
+             */
+            emit(__slli(rd, rs1, 16)); /* Shift left 16 bits */
+            emit(__srli(rd, rd, 16));  /* Shift right 16 bits logical */
+        } else if (ph2_ir->src1 == 4) {
+            /* No truncation needed for 32-bit values */
+            emit(__add(rd, rs1, __zero));
+        } else {
             fatal("Unsupported truncation operation with invalid target size");
-
-        emit(__andi(rd, rs1, rs2));
+        }
         return;
     case OP_sign_ext:
-        /* TODO: Support sign extension to types other than int */
-        emit(__andi(rd, rs1, 0xFF));
-        emit(__slli(rd, rd, 24));
-        emit(__srai(rd, rd, 24));
-        /* TODO: Consider Zbb extension for improved bit manipulation */
-        /* emit(__sext_b(rd, rs1)); */
+        if (ph2_ir->src1 == 1) {
+            /* Sign extend from byte to word */
+            emit(__andi(rd, rs1, 0xFF));
+            emit(__slli(rd, rd, 24));
+            emit(__srai(rd, rd, 24));
+        } else if (ph2_ir->src1 == 2) {
+            /* Sign extend from short to word */
+            emit(__andi(rd, rs1, 0xFFFF));
+            emit(__slli(rd, rd, 16)); /* Shift left 16 bits */
+            emit(__srai(rd, rd, 16)); /* Arithmetic shift right 16 bits */
+        } else {
+            /* Fallback to original behavior for unknown sizes */
+            emit(__andi(rd, rs1, 0xFF));
+            emit(__slli(rd, rd, 24));
+            emit(__srai(rd, rd, 24));
+        }
         return;
     case OP_cast:
         /* Generic cast operation - for now, just move the value */