Fix RISC-V sign extension and parser type size handling

- Fix OP_sign_ext in parser to use source type size instead of target type size
- Improve RISC-V 16-bit sign extension to use shift-only approach, avoiding
  immediate field overflow with 0xFFFF value
- Consolidate RISC-V sign extension fallback cases for better code reusability

Author: hhhh1300

src/parser.c

@@ -247,8 +247,12 @@ var_t *promote_unchecked(block_t *block,
 {
     var_t *rd = require_typed_ptr_var(block, target_type, target_ptr);
     gen_name_to(rd->var_name);
+    /* TODO: Use source type size instead of target type size for
+     * sign extension. The OP_sign_ext instruction may need both
+     * source and target sizes for proper code generation.
+     */
     add_insn(block, *bb, OP_sign_ext, rd, var, NULL,
-             target_ptr ? PTR_SIZE : target_type->size, NULL);
+             target_ptr ? PTR_SIZE : var->type->size, NULL);
     return rd;
 }
 

src/riscv-codegen.c

@@ -101,7 +101,10 @@ void update_elf_offset(ph2_ir_t *ph2_ir)
             elf_offset += 4;
         return;
     case OP_sign_ext:
-        elf_offset += 12;
+        if (ph2_ir->src1 == 2)
+            elf_offset += 8;
+        else
+            elf_offset += 12;
         return;
     case OP_cast:
         elf_offset += 4;
@@ -441,22 +444,19 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
         }
         return;
     case OP_sign_ext:
-        if (ph2_ir->src1 == 1) {
-            /* Sign extend from byte to word */
-            rs2 = 0xFF;
-            ofs = 24;
-        } else if (ph2_ir->src1 == 2) {
-            /* Sign extend from short to word */
-            rs2 = 0xFFFF;
-            ofs = 16;
+        if (ph2_ir->src1 == 2) {
+            /* Sign extend from short to word
+             * For 16-bit sign extension, use only shift operations
+             * since 0xFFFF is too large for RISC-V immediate field
+             */
+            emit(__slli(rd, rs1, 16));
+            emit(__srai(rd, rd, 16));
         } else {
-            /* Fallback to original behavior for unknown sizes */
-            rs2 = 0xFF;
-            ofs = 24;
+            /* Sign extend from byte to word (src1 == 1) or fallback */
+            emit(__andi(rd, rs1, 0xFF));
+            emit(__slli(rd, rd, 24));
+            emit(__srai(rd, rd, 24));
         }
-        emit(__andi(rd, rs1, rs2));
-        emit(__slli(rd, rd, ofs));
-        emit(__srai(rd, rd, ofs));
         return;
     case OP_cast:
         /* Generic cast operation - for now, just move the value */