@@ -937,37 +937,75 @@ bool triple_pattern_optimization(ph2_ir_t *ph2_ir)
937937}
938938
939939/* Main peephole optimization driver.
940- * It iterates through all functions, basic blocks, and IR instructions to apply
941- * local optimizations on adjacent instruction pairs.
940+ *
941+ * SSA Optimizer (insn_t, before register allocation):
942+ * - Constant folding with known values (5+3 → 8, x+0 → x)
943+ * - Common subexpression elimination
944+ * - Self-assignment elimination (x = x)
945+ * - Dead code elimination
946+ * - Constant comparison folding (5 < 3 → 0)
947+ *
948+ * Peephole Optimizer (ph2_ir_t, after register allocation):
949+ * - Register-based self-operations (r1-r1 → 0, r1^r1 → 0)
950+ * - Bitwise operation optimization (SSA doesn't handle these)
951+ * - Strength reduction for power-of-2 (needs actual constants loaded)
952+ * - Load/store pattern elimination
953+ * - Triple instruction sequence optimization
954+ * - Architecture-specific instruction fusion
955+ *
956+ * This refined separation eliminates redundant optimizations while
957+ * maintaining comprehensive coverage of optimization opportunities.
942958 */
943959void peephole (void )
944960{
945961 for (func_t * func = FUNC_LIST .head ; func ; func = func -> next ) {
946- /* Phase 1: Dead code elimination working with SCCP results */
962+ /* Phase 1: Dead code elimination complementing SCCP results */
947963 eliminate_dead_instructions (func );
948964 fold_constant_branches (func );
949965
950- /* Phase 2: Local peephole optimizations */
966+ /* Phase 2: Local peephole optimizations on post-register-allocation IR
967+ */
951968 for (basic_block_t * bb = func -> bbs ; bb ; bb = bb -> rpo_next ) {
952969 for (ph2_ir_t * ir = bb -> ph2_ir_list .head ; ir ; ir = ir -> next ) {
953970 ph2_ir_t * next = ir -> next ;
954971 if (!next )
955972 continue ;
956973
957974 /* Self-assignment elimination
958- * Removes trivial assignments where destination equals source
959- * Pattern: {mov x, x} → eliminated
960- * Common in compiler-generated intermediate code
975+ * Keep this as a safety net: SSA handles most cases, but
976+ * register allocation might create new self-assignments
961977 */
962978 if (next -> op == OP_assign && next -> dest == next -> src0 ) {
963979 ir -> next = next -> next ;
964980 continue ;
965981 }
966982
967- /* Try instruction fusion first */
983+ /* Try triple pattern optimization first (3-instruction
984+ * sequences)
985+ */
986+ if (triple_pattern_optimization (ir ))
987+ continue ;
988+
989+ /* Try instruction fusion (2-instruction sequences) */
968990 if (insn_fusion (ir ))
969991 continue ;
970992
993+ /* Apply comparison optimization */
994+ if (comparison_optimization (ir ))
995+ continue ;
996+
997+ /* Apply strength reduction for power-of-2 operations */
998+ if (strength_reduction (ir ))
999+ continue ;
1000+
1001+ /* Apply algebraic simplification */
1002+ if (algebraic_simplification (ir ))
1003+ continue ;
1004+
1005+ /* Apply bitwise operation optimizations */
1006+ if (bitwise_optimization (ir ))
1007+ continue ;
1008+
9711009 /* Apply redundant move elimination */
9721010 if (redundant_move_elim (ir ))
9731011 continue ;
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