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jackpot51jackpot51
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Add gaze20 (#260)
1 parent 1382fe9 commit 4582580

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11 files changed

+442
-3
lines changed

11 files changed

+442
-3
lines changed

‎src/mainboard/system76/rpl/Kconfig‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,13 @@ config BOARD_SYSTEM76_GAZE18
7878
select EC_SYSTEM76_EC_DGPU
7979
select SOC_INTEL_ALDERLAKE_PCH_P
8080

81+
config BOARD_SYSTEM76_GAZE20
82+
select BOARD_SYSTEM76_RPL_COMMON
83+
select DRIVERS_GFX_NVIDIA
84+
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
85+
select EC_SYSTEM76_EC_DGPU
86+
select SOC_INTEL_ALDERLAKE_PCH_P
87+
8188
config BOARD_SYSTEM76_LEMP12
8289
select BOARD_SYSTEM76_RPL_COMMON
8390
select HAVE_SPD_IN_CBFS
@@ -124,6 +131,7 @@ config VARIANT_DIR
124131
default "darp9" if BOARD_SYSTEM76_DARP9
125132
default "galp7" if BOARD_SYSTEM76_GALP7
126133
default "gaze18" if BOARD_SYSTEM76_GAZE18
134+
default "gaze20" if BOARD_SYSTEM76_GAZE20
127135
default "lemp12" if BOARD_SYSTEM76_LEMP12
128136
default "oryp11" if BOARD_SYSTEM76_ORYP11
129137
default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -140,6 +148,7 @@ config MAINBOARD_PART_NUMBER
140148
default "darp9" if BOARD_SYSTEM76_DARP9
141149
default "galp7" if BOARD_SYSTEM76_GALP7
142150
default "gaze18" if BOARD_SYSTEM76_GAZE18
151+
default "gaze20" if BOARD_SYSTEM76_GAZE20
143152
default "lemp12" if BOARD_SYSTEM76_LEMP12
144153
default "oryp11" if BOARD_SYSTEM76_ORYP11
145154
default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -150,7 +159,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
150159
default "Bonobo WS" if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
151160
default "Darter Pro" if BOARD_SYSTEM76_DARP9
152161
default "Galago Pro" if BOARD_SYSTEM76_GALP7
153-
default "Gazelle" if BOARD_SYSTEM76_GAZE18
162+
default "Gazelle" if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_GAZE20
154163
default "Lemur Pro" if BOARD_SYSTEM76_LEMP12
155164
default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
156165
default "Serval WS" if BOARD_SYSTEM76_SERW13
@@ -163,6 +172,7 @@ config MAINBOARD_VERSION
163172
default "darp9" if BOARD_SYSTEM76_DARP9
164173
default "galp7" if BOARD_SYSTEM76_GALP7
165174
default "gaze18" if BOARD_SYSTEM76_GAZE18
175+
default "gaze20" if BOARD_SYSTEM76_GAZE20
166176
default "lemp12" if BOARD_SYSTEM76_LEMP12
167177
default "oryp11" if BOARD_SYSTEM76_ORYP11
168178
default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -182,12 +192,12 @@ config DRIVERS_GFX_NVIDIA_BRIDGE
182192
default 0x02 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
183193

184194
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
185-
default 45 if BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
195+
default 45 if BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE20 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
186196
default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
187197
default 80 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
188198

189199
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
190-
default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
200+
default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_GAZE20 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
191201

192202
config FMDFILE
193203
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"

‎src/mainboard/system76/rpl/Kconfig.name‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,9 @@ config BOARD_SYSTEM76_GALP7
2121
config BOARD_SYSTEM76_GAZE18
2222
bool "gaze18"
2323

24+
config BOARD_SYSTEM76_GAZE20
25+
bool "gaze20"
26+
2427
config BOARD_SYSTEM76_LEMP12
2528
bool "lemp12"
2629

‎src/mainboard/system76/rpl/variants/gaze20/board.fmd‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
FLASH 32M {
2+
SI_DESC 4K
3+
SI_ME 4824K
4+
SI_BIOS@16M 16M {
5+
RW_MRC_CACHE 64K
6+
SMMSTORE(PRESERVE) 256K
7+
WP_RO {
8+
FMAP 4K
9+
COREBOOT(CBFS)
10+
}
11+
}
12+
}

‎src/mainboard/system76/rpl/variants/gaze20/board_info.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
Board name: gaze20
2+
Release year: 2025

‎src/mainboard/system76/rpl/variants/gaze20/data.vbt‎

9 KB
Binary file not shown.

‎src/mainboard/system76/rpl/variants/gaze20/gpio.c‎

Lines changed: 227 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,227 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#include <mainboard/gpio.h>
4+
#include <soc/gpio.h>
5+
6+
static const struct pad_config gpio_table[] = {
7+
/* ------- GPIO Group GPD ------- */
8+
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
9+
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
10+
PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), // LANRTD3_WAKE#
11+
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
12+
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
13+
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
14+
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
15+
PAD_NC(GPD7, NONE),
16+
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // Not documented
17+
PAD_CFG_GPI(GPD9, NONE, DEEP), // SLP_WLAN#
18+
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
19+
PAD_NC(GPD11, NONE),
20+
21+
/* ------- GPIO Group GPP_A ------- */
22+
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
23+
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
24+
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
25+
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
26+
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
27+
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
28+
PAD_NC(GPP_A6, NONE),
29+
PAD_NC(GPP_A7, NONE),
30+
PAD_NC(GPP_A8, NONE),
31+
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
32+
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
33+
PAD_NC(GPP_A11, NONE),
34+
PAD_NC(GPP_A12, NONE),
35+
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
36+
// GPP_A14 (DGPU_PWR_EN) configured in bootblock
37+
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // DP_HPD
38+
PAD_NC(GPP_A16, NONE),
39+
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
40+
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // MDP_B_HPD
41+
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
42+
_PAD_CFG_STRUCT(GPP_A20, 0x86880100, 0x0000), // HDMI_HPD
43+
_PAD_CFG_STRUCT(GPP_A21, 0x86880100, 0x0000), // NVVDD_TALERT#
44+
PAD_CFG_GPO(GPP_A22, 1, PLTRST), // LAN_PWR_EN
45+
PAD_NC(GPP_A23, NONE),
46+
47+
/* ------- GPIO Group GPP_B ------- */
48+
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
49+
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
50+
// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
51+
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
52+
PAD_NC(GPP_B4, NONE),
53+
PAD_CFG_GPO(GPP_B5, 0, DEEP), // PS8461_SW
54+
PAD_NC(GPP_B6, NONE),
55+
PAD_NC(GPP_B7, NONE),
56+
PAD_NC(GPP_B8, NONE),
57+
// GPP_B9 missing
58+
// GPP_B10 missing
59+
PAD_CFG_GPI(GPP_B11, NONE, PLTRST), // PMCALERT#
60+
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
61+
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
62+
PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap
63+
PAD_CFG_GPO(GPP_B15, 1, PLTRST), // WLAN_RST#_R
64+
_PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000), // INTP_OUT
65+
PAD_NC(GPP_B17, NONE),
66+
PAD_NC(GPP_B18, NONE), // NO REBOOT strap
67+
// GPP_B19 missing
68+
// GPP_B20 missing
69+
// GPP_B21 missing
70+
// GPP_B22 missing
71+
PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
72+
73+
/* ------- GPIO Group GPP_C ------- */
74+
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
75+
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
76+
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_SSD2_PWR_EN
77+
PAD_NC(GPP_C3, NONE),
78+
PAD_NC(GPP_C4, NONE),
79+
PAD_CFG_GPO(GPP_C5, 1, PLTRST), // LAN_RTD3#, TLS CONFIDENTIALITY strap
80+
PAD_NC(GPP_C6, NONE),
81+
PAD_NC(GPP_C7, NONE),
82+
// GPP_C8 missing
83+
// GPP_C9 missing
84+
// GPP_C10 missing
85+
// GPP_C11 missing
86+
// GPP_C12 missing
87+
// GPP_C13 missing
88+
// GPP_C14 missing
89+
// GPP_C15 missing
90+
// GPP_C16 missing
91+
// GPP_C17 missing
92+
// GPP_C18 missing
93+
// GPP_C19 missing
94+
// GPP_C20 missing
95+
// GPP_C21 missing
96+
// GPP_C22 missing
97+
// GPP_C23 missing
98+
99+
/* ------- GPIO Group GPP_D ------- */
100+
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
101+
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
102+
PAD_NC(GPP_D2, NONE),
103+
PAD_NC(GPP_D3, NONE),
104+
PAD_NC(GPP_D4, NONE),
105+
// GPP_D5 (SSD1_CLKREQ#) configured by FSP
106+
PAD_NC(GPP_D6, NONE),
107+
PAD_NC(GPP_D7, NONE),
108+
// GPP_D8 (GPU_PCIE_CLKREQ3#) configured by FSP
109+
PAD_NC(GPP_D9, NONE),
110+
PAD_NC(GPP_D10, NONE), // strap
111+
PAD_NC(GPP_D11, NONE),
112+
PAD_NC(GPP_D12, NONE), // strap
113+
PAD_CFG_GPO(GPP_D13, 0, DEEP), // WLAN_WAKEUP#
114+
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_SSD1_PWR_EN
115+
PAD_NC(GPP_D15, NONE),
116+
PAD_CFG_GPO(GPP_D16, 0, DEEP), // TEST_R
117+
PAD_NC(GPP_D17, NONE),
118+
PAD_NC(GPP_D18, NONE),
119+
PAD_NC(GPP_D19, NONE),
120+
121+
/* ------- GPIO Group GPP_E ------- */
122+
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
123+
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
124+
PAD_NC(GPP_E2, NONE), // BOARD_ID5
125+
PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN
126+
PAD_NC(GPP_E4, NONE),
127+
PAD_NC(GPP_E5, NONE),
128+
PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap
129+
PAD_NC(GPP_E7, NONE),
130+
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
131+
PAD_NC(GPP_E9, NONE), // SWI#
132+
PAD_NC(GPP_E10, NONE), // strap
133+
PAD_NC(GPP_E11, NONE), // strap
134+
PAD_NC(GPP_E12, NONE), // BOARD_ID4
135+
PAD_NC(GPP_E13, NONE),
136+
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
137+
PAD_NC(GPP_E15, NONE),
138+
PAD_NC(GPP_E16, NONE),
139+
PAD_NC(GPP_E17, NONE),
140+
PAD_NC(GPP_E18, NONE),
141+
PAD_NC(GPP_E19, NONE), // strap
142+
PAD_NC(GPP_E20, NONE),
143+
PAD_NC(GPP_E21, NONE), // strap
144+
PAD_NC(GPP_E22, NONE),
145+
PAD_NC(GPP_E23, NONE),
146+
147+
/* ------- GPIO Group GPP_F ------- */
148+
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
149+
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
150+
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
151+
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
152+
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
153+
// GPP_F5 (XTAL_CLKREQ) configured by FSP
154+
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
155+
PAD_CFG_GPO(GPP_F7, 1, DEEP), // GPP_LAN_RST#
156+
// GPP_F8 missing
157+
PAD_NC(GPP_F9, NONE),
158+
PAD_NC(GPP_F10, NONE), // strap
159+
PAD_NC(GPP_F11, NONE), // BOARD_ID3
160+
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
161+
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
162+
PAD_NC(GPP_F14, NONE), // BOARD_ID1
163+
PAD_NC(GPP_F15, NONE), // BOARD_ID2
164+
PAD_NC(GPP_F16, NONE), // BOARD_ID6
165+
PAD_NC(GPP_F17, NONE), // BOARD_ID7
166+
PAD_CFG_GPO(GPP_F18, 1, DEEP), // CCD_FW_WP#
167+
// GPP_F19 (GLAN_CLKREQ#) configured by FSP
168+
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST#
169+
PAD_CFG_GPO(GPP_F21, 1, PLTRST), // M2_SSD2_RST#
170+
PAD_NC(GPP_F22, NONE),
171+
PAD_NC(GPP_F23, NONE),
172+
173+
/* ------- GPIO Group GPP_H ------- */
174+
PAD_NC(GPP_H0, NONE), // strap
175+
PAD_NC(GPP_H1, NONE), // strap
176+
PAD_NC(GPP_H2, NONE), // strap
177+
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
178+
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
179+
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
180+
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // SMD_7411
181+
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // SMC_7411
182+
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
183+
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
184+
// GPP_H10 (UART0_RX) configured in bootblock
185+
// GPP_H11 (UART0_TX) configured in bootblock
186+
PAD_NC(GPP_H12, NONE),
187+
PAD_NC(GPP_H13, NONE),
188+
// GPP_H14 missing
189+
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // I_MDP_CLK
190+
// GPP_H16 missing
191+
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // I_MDP_DATA
192+
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
193+
// GPP_H19 (SSD2_CLKREQ4#) configured by FSP
194+
PAD_NC(GPP_H20, NONE),
195+
PAD_NC(GPP_H21, NONE),
196+
PAD_NC(GPP_H22, NONE),
197+
// GPP_H23 (WLAN_CLKREQ5#) configured by FSP
198+
199+
/* ------- GPIO Group GPP_R ------- */
200+
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
201+
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
202+
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
203+
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
204+
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
205+
PAD_NC(GPP_R5, NONE),
206+
PAD_NC(GPP_R6, NONE),
207+
PAD_NC(GPP_R7, NONE),
208+
209+
/* ------- GPIO Group GPP_S ------- */
210+
PAD_NC(GPP_S0, NONE),
211+
PAD_NC(GPP_S1, NONE),
212+
PAD_NC(GPP_S2, NONE),
213+
PAD_NC(GPP_S3, NONE),
214+
PAD_NC(GPP_S4, NONE),
215+
PAD_NC(GPP_S5, NONE),
216+
PAD_NC(GPP_S6, NONE),
217+
PAD_NC(GPP_S7, NONE),
218+
219+
/* ------- GPIO Group GPP_T ------- */
220+
PAD_NC(GPP_T2, NONE),
221+
PAD_NC(GPP_T3, NONE),
222+
};
223+
224+
void mainboard_configure_gpios(void)
225+
{
226+
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
227+
}

‎src/mainboard/system76/rpl/variants/gaze20/gpio_early.c‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#include <mainboard/gpio.h>
4+
#include <soc/gpio.h>
5+
6+
static const struct pad_config early_gpio_table[] = {
7+
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
8+
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
9+
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
10+
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
11+
};
12+
13+
void mainboard_configure_early_gpios(void)
14+
{
15+
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
16+
}

‎src/mainboard/system76/rpl/variants/gaze20/hda_verb.c‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#include <device/azalia_device.h>
4+
5+
const u32 cim_verb_data[] = {
6+
/* Realtek, ALC255 */
7+
0x10ec0255, /* Vendor ID */
8+
0x15582560, /* Subsystem ID */
9+
12, /* Number of entries */
10+
AZALIA_SUBVENDOR(0, 0x15582560),
11+
AZALIA_RESET(1),
12+
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
13+
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
14+
AZALIA_PIN_CFG(0, 0x17, 0x40000000),
15+
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
16+
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
17+
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
18+
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
19+
AZALIA_PIN_CFG(0, 0x1d, 0x41e79b45),
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AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
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AZALIA_PIN_CFG(0, 0x21, 0x04211020),
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};
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const u32 pc_beep_verbs[] = {};
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AZALIA_ARRAY_SIZES;

‎src/mainboard/system76/rpl/variants/gaze20/include/variant/gpio.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <soc/gpio.h>
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#define DGPU_RST_N GPP_B2
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#define DGPU_PWR_EN GPP_A14
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#define DGPU_GC6 GPP_F13
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#define DGPU_SSID 0x25601558
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#endif

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