From 95903dd0935a1db07ac737cee6532e175f0b27c2 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 20 Mar 2025 22:10:30 +0000 Subject: [PATCH 1/7] Add bonw16 extract --- models/bonw16/IntelGopDriver.efi | 3 + models/bonw16/README.md | 12 + models/bonw16/README.md.in | 1 + models/bonw16/coreboot-collector.txt | 317 +++++++++++++++++++++++++++ models/bonw16/ecspy.txt | 113 ++++++++++ models/bonw16/fd.rom | 3 + models/bonw16/gpio.c | 241 ++++++++++++++++++++ models/bonw16/hda_verb.c | 52 +++++ models/bonw16/me.rom | 3 + models/bonw16/vbt.rom | 3 + tools/coreboot-collector | 2 +- 11 files changed, 749 insertions(+), 1 deletion(-) create mode 100644 models/bonw16/IntelGopDriver.efi create mode 100644 models/bonw16/README.md create mode 100644 models/bonw16/README.md.in create mode 100644 models/bonw16/coreboot-collector.txt create mode 100644 models/bonw16/ecspy.txt create mode 100644 models/bonw16/fd.rom create mode 100644 models/bonw16/gpio.c create mode 100644 models/bonw16/hda_verb.c create mode 100644 models/bonw16/me.rom create mode 100644 models/bonw16/vbt.rom diff --git a/models/bonw16/IntelGopDriver.efi b/models/bonw16/IntelGopDriver.efi new file mode 100644 index 00000000..785ff7ba --- /dev/null +++ b/models/bonw16/IntelGopDriver.efi @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e19dd30591caa694132cfaf9f2326e9f404b18318ffdf8b11c82ceffa9edbfb2 +size 140800 diff --git a/models/bonw16/README.md b/models/bonw16/README.md new file mode 100644 index 00000000..07e766a5 --- /dev/null +++ b/models/bonw16/README.md @@ -0,0 +1,12 @@ +# System76 Bonobo WS (bonw16) + +## Contents + +- [EC](./ec.rom) + - *Read Error: No such file or directory (os error 2)* +- [FD](./fd.rom) + - Size: 16 KB + - HAP: false +- [ME](./me.rom) + - Size: 10472 KB + - Version: 19.0.0.1931 diff --git a/models/bonw16/README.md.in b/models/bonw16/README.md.in new file mode 100644 index 00000000..4684bcbc --- /dev/null +++ b/models/bonw16/README.md.in @@ -0,0 +1 @@ +# System76 Bonobo WS (bonw16) diff --git a/models/bonw16/coreboot-collector.txt b/models/bonw16/coreboot-collector.txt new file mode 100644 index 00000000..9da15778 --- /dev/null +++ b/models/bonw16/coreboot-collector.txt @@ -0,0 +1,317 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x7D1C, Revision 0x01 +PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0x7ECC, Revision 0x10 +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x7D67, Revision 0x06 +PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xAD03, Revision 0x01 +PCI Device: 0000:00:06.0: Class 0x00060400, Vendor 0x8086, Device 0xAE4D, Revision 0x10 +PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xAE4C, Revision 0x10 +PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xAD0D, Revision 0x01 +PCI Device: 0000:00:0b.0: Class 0x00120000, Vendor 0x8086, Device 0xAD1D, Revision 0x01 +PCI Device: 0000:00:14.0: Class 0x00050000, Vendor 0x8086, Device 0xAE7F, Revision 0x10 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0xAE10, Revision 0x10 +PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0xAE23, Revision 0x10 +PCI Device: 0000:01:00.0: Class 0x00010802, Vendor 0x1344, Device 0x5416, Revision 0x01 +PCI Device: 0000:02:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2C58, Revision 0xA1 +PCI Device: 0000:02:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22E9, Revision 0xA1 +PCI Device: 0000:80:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7F6E, Revision 0x10 +PCI Device: 0000:80:14.5: Class 0x00000000, Vendor 0x8086, Device 0x7F2F, Revision 0x10 +PCI Device: 0000:80:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7F4C, Revision 0x10 +PCI Device: 0000:80:15.2: Class 0x000C8000, Vendor 0x8086, Device 0x7F4E, Revision 0x10 +PCI Device: 0000:80:15.3: Class 0x000C8000, Vendor 0x8086, Device 0x7F4F, Revision 0x10 +PCI Device: 0000:80:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7F68, Revision 0x10 +PCI Device: 0000:80:19.0: Class 0x000C8000, Vendor 0x8086, Device 0x7F7A, Revision 0x10 +PCI Device: 0000:80:19.1: Class 0x000C8000, Vendor 0x8086, Device 0x7F7B, Revision 0x10 +PCI Device: 0000:80:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7F3D, Revision 0x10 +PCI Device: 0000:80:1c.6: Class 0x00060400, Vendor 0x8086, Device 0x7F3E, Revision 0x10 +PCI Device: 0000:80:1c.7: Class 0x00060400, Vendor 0x8086, Device 0x7F3F, Revision 0x10 +PCI Device: 0000:80:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x7F30, Revision 0x10 +PCI Device: 0000:80:1d.6: Class 0x00060400, Vendor 0x8086, Device 0x7F36, Revision 0x10 +PCI Device: 0000:80:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7F0C, Revision 0x10 +PCI Device: 0000:80:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x7F50, Revision 0x10 +PCI Device: 0000:80:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7F23, Revision 0x10 +PCI Device: 0000:80:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7F24, Revision 0x10 +PCI Device: 0000:81:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01 +PCI Device: 0000:82:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3102, Revision 0x04 +PCI Device: 0000:83:00.0: Class 0x00028000, Vendor 0x8086, Device 0x272B, Revision 0x1A +PCI Device: 0000:84:00.0: Class 0x00060400, Vendor 0x8086, Device 0x5780, Revision 0x84 +PCI Device: 0000:85:00.0: Class 0x00060400, Vendor 0x8086, Device 0x5780, Revision 0x84 +PCI Device: 0000:85:01.0: Class 0x00060400, Vendor 0x8086, Device 0x5780, Revision 0x84 +PCI Device: 0000:85:02.0: Class 0x00060400, Vendor 0x8086, Device 0x5780, Revision 0x84 +PCI Device: 0000:85:03.0: Class 0x00060400, Vendor 0x8086, Device 0x5780, Revision 0x84 +PCI Device: 0000:86:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x5781, Revision 0x84 +PCI Device: 0000:ad:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x5782, Revision 0x00 +PCI Device: 0000:d5:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3102, Revision 0x04 +## GPIO ## +800 series PCH +GPP_D0 (0x6E,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff +GPP_D1 (0x6E,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D2 (0x6E,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D3 (0x6E,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D4 (0x6E,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D5 (0x6E,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D6 (0x6E,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D7 (0x6E,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D8 (0x6E,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D9 (0x6E,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D10 (0x6E,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D11 (0x6E,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D12 (0x6E,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D13 (0x6E,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D14 (0x6E,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D15 (0x6E,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D16 (0x6E,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D17 (0x6E,0x22) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D18 (0x6E,0x24) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D19 (0x6E,0x26) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D20 (0x6E,0x28) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D21 (0x6E,0x2A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D22 (0x6E,0x2C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_D23 (0x6E,0x2E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R0 (0x6E,0x32) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R1 (0x6E,0x34) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R2 (0x6E,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R3 (0x6E,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R4 (0x6E,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R5 (0x6E,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R6 (0x6E,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R7 (0x6E,0x40) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R8 (0x6E,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R9 (0x6E,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R10 (0x6E,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R11 (0x6E,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_R12 (0x6E,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J0 (0x6E,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J1 (0x6E,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J2 (0x6E,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J3 (0x6E,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J4 (0x6E,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J5 (0x6E,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J6 (0x6E,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J7 (0x6E,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J8 (0x6E,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J9 (0x6E,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J10 (0x6E,0x62) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J11 (0x6E,0x64) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J12 (0x6E,0x66) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J13 (0x6E,0x68) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J14 (0x6E,0x6A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J15 (0x6E,0x6C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_J16 (0x6E,0x6E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A0 (0x6D,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff +GPP_A1 (0x6D,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A2 (0x6D,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A3 (0x6D,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A4 (0x6D,0x08) 0x21000000 0xffffffff 0xffffffff 0xffffffff +GPP_A5 (0x6D,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A6 (0x6D,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A7 (0x6D,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A8 (0x6D,0x10) 0x21001f00 0xffffffff 0xffffffff 0xffffffff +GPP_A9 (0x6D,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A10 (0x6D,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A11 (0x6D,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_A12 (0x6D,0x18) 0x00000000 0xffffffff 0xffffffff 0xffffffff +GPP_A13 (0x6D,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B0 (0x6D,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B1 (0x6D,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B2 (0x6D,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B3 (0x6D,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B4 (0x6D,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B5 (0x6D,0x40) 0x210000ff 0xffffffff 0xffffffff 0xffffffff +GPP_B6 (0x6D,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B7 (0x6D,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B8 (0x6D,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B9 (0x6D,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B10 (0x6D,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B11 (0x6D,0x4C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B12 (0x6D,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B13 (0x6D,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B14 (0x6D,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B15 (0x6D,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B16 (0x6D,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B17 (0x6D,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B18 (0x6D,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B19 (0x6D,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B20 (0x6D,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_B21 (0x6D,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD0 (0x6C,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff +GPD1 (0x6C,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD2 (0x6C,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD3 (0x6C,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD4 (0x6C,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD5 (0x6C,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD6 (0x6C,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD7 (0x6C,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD8 (0x6C,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD9 (0x6C,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD10 (0x6C,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD11 (0x6C,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPD12 (0x6C,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C0 (0x6B,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C1 (0x6B,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C2 (0x6B,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C3 (0x6B,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C4 (0x6B,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C5 (0x6B,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C6 (0x6B,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C7 (0x6B,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C8 (0x6B,0x22) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C9 (0x6B,0x24) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C10 (0x6B,0x26) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C11 (0x6B,0x28) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C12 (0x6B,0x2A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C13 (0x6B,0x2C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C14 (0x6B,0x2E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C15 (0x6B,0x30) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C16 (0x6B,0x32) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C17 (0x6B,0x34) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C18 (0x6B,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C19 (0x6B,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C20 (0x6B,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C21 (0x6B,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C22 (0x6B,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_C23 (0x6B,0x40) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H0 (0x6B,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H1 (0x6B,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H2 (0x6B,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H3 (0x6B,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H4 (0x6B,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H5 (0x6B,0x4C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H6 (0x6B,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H7 (0x6B,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H8 (0x6B,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H9 (0x6B,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H10 (0x6B,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H11 (0x6B,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H12 (0x6B,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H13 (0x6B,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H14 (0x6B,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H15 (0x6B,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H16 (0x6B,0x62) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H17 (0x6B,0x64) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H18 (0x6B,0x66) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_H19 (0x6B,0x68) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_S0 (0x6A,0x00) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S1 (0x6A,0x02) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S2 (0x6A,0x04) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S3 (0x6A,0x06) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S4 (0x6A,0x08) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S5 (0x6A,0x0A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S6 (0x6A,0x0C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_S7 (0x6A,0x0E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E0 (0x6A,0x10) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E1 (0x6A,0x12) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E2 (0x6A,0x14) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E3 (0x6A,0x16) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E4 (0x6A,0x18) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E5 (0x6A,0x1A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E6 (0x6A,0x1C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E7 (0x6A,0x1E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E8 (0x6A,0x20) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E9 (0x6A,0x22) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E10 (0x6A,0x24) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E11 (0x6A,0x26) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E12 (0x6A,0x28) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E13 (0x6A,0x2A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E14 (0x6A,0x2C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E15 (0x6A,0x2E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E16 (0x6A,0x30) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E17 (0x6A,0x32) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E18 (0x6A,0x34) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E19 (0x6A,0x36) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E20 (0x6A,0x38) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_E21 (0x6A,0x3A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K0 (0x6A,0x3E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K1 (0x6A,0x40) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K2 (0x6A,0x42) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K3 (0x6A,0x44) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K4 (0x6A,0x46) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K5 (0x6A,0x48) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K6 (0x6A,0x4A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K7 (0x6A,0x4C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K8 (0x6A,0x4E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K9 (0x6A,0x50) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_K10 (0x6A,0x52) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F0 (0x6A,0x5A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F1 (0x6A,0x5C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F2 (0x6A,0x5E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F3 (0x6A,0x60) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F4 (0x6A,0x62) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F5 (0x6A,0x64) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F6 (0x6A,0x66) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F7 (0x6A,0x68) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F8 (0x6A,0x6A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F9 (0x6A,0x6C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F10 (0x6A,0x6E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F11 (0x6A,0x70) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F12 (0x6A,0x72) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F13 (0x6A,0x74) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F14 (0x6A,0x76) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F15 (0x6A,0x78) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F16 (0x6A,0x7A) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F17 (0x6A,0x7C) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F18 (0x6A,0x7E) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F19 (0x6A,0x80) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F20 (0x6A,0x82) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F21 (0x6A,0x84) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F22 (0x6A,0x86) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_F23 (0x6A,0x88) 0x00000000 0x00000000 0x00000000 0x00000000 +GPP_I0 (0x69,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff +GPP_I1 (0x69,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I2 (0x69,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I3 (0x69,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I4 (0x69,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I5 (0x69,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I6 (0x69,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I7 (0x69,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I8 (0x69,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I9 (0x69,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I10 (0x69,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I11 (0x69,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I12 (0x69,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I13 (0x69,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I14 (0x69,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I15 (0x69,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_I16 (0x69,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Nvidia + chip_name: Generic HDMI + vendor_id: 0x10de00ab + subsystem_id: 0x10de0000 + revision_id: 0x100100 + 0x04: 0x585600f0 + 0x05: 0x185600f0 + 0x06: 0x185600f0 + 0x07: 0x185600f0 +hdaudioC1D0 + vendor_name: Realtek + chip_name: ALC1220 + vendor_id: 0x10ec1220 + subsystem_id: 0x15585802 + revision_id: 0x100101 + 0x12: 0x90a60120 + 0x14: 0x0421101f + 0x15: 0x40000000 + 0x16: 0x411111f0 + 0x17: 0x411111f0 + 0x18: 0x411111f0 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x90170110 + 0x1d: 0x41a7932d + 0x1e: 0x411111f0 +hdaudioC1D2 + vendor_name: Intel + chip_name: Meteor Lake HDMI + vendor_id: 0x8086281d + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x04: 0x18560010 + 0x06: 0x18560010 + 0x08: 0x18560010 + 0x0a: 0x18560010 + 0x0b: 0x18560010 + 0x0c: 0x18560010 + 0x0d: 0x18560010 + 0x0e: 0x18560010 + 0x0f: 0x18560010 diff --git a/models/bonw16/ecspy.txt b/models/bonw16/ecspy.txt new file mode 100644 index 00000000..ac114342 --- /dev/null +++ b/models/bonw16/ecspy.txt @@ -0,0 +1,113 @@ +id 5570 rev 7 +A0: data 1 mirror 1 pot 0 control 80 +A1: data 0 mirror 0 pot 0 control 80 +A2: data 1 mirror 0 pot 0 control 00 +A3: data 1 mirror 1 pot 0 control 00 +A4: data 0 mirror 0 pot 0 control 00 +A5: data 0 mirror 0 pot 0 control 00 +A6: data 0 mirror 0 pot 0 control 00 +A7: data 0 mirror 0 pot 0 control 00 +B0: data 0 mirror 0 pot 0 control 84 +B1: data 1 mirror 1 pot 0 control 84 +B2: data 1 mirror 1 pot 0 control 84 +B3: data 1 mirror 1 pot 0 control 80 +B4: data 1 mirror 1 pot 0 control 40 +B5: data 1 mirror 1 pot 0 control 40 +B6: data 1 mirror 1 pot 0 control 44 +B7: data 1 mirror 1 pot 0 control 80 +C0: data 1 mirror 1 pot 0 control 80 +C1: data 1 mirror 1 pot 0 control 04 +C2: data 1 mirror 1 pot 0 control 04 +C3: data 1 mirror 1 pot 0 control 04 +C4: data 1 mirror 1 pot 0 control 84 +C5: data 1 mirror 1 pot 0 control 04 +C6: data 1 mirror 1 pot 0 control 40 +C7: data 1 mirror 1 pot 0 control 44 +D0: data 1 mirror 1 pot 0 control 40 +D1: data 1 mirror 1 pot 0 control 44 +D2: data 1 mirror 1 pot 0 control 00 +D3: data 0 mirror 0 pot 0 control 40 +D4: data 0 mirror 0 pot 0 control 40 +D5: data 1 mirror 1 pot 0 control 44 +D6: data 1 mirror 1 pot 0 control 02 +D7: data 1 mirror 1 pot 0 control 02 +E0: data 1 mirror 1 pot 0 control 04 +E1: data 1 mirror 1 pot 0 control 44 +E2: data 1 mirror 1 pot 0 control 80 +E3: data 1 mirror 1 pot 0 control 40 +E4: data 1 mirror 1 pot 0 control 42 +E5: data 1 mirror 1 pot 0 control 40 +E6: data 0 mirror 0 pot 0 control 80 +E7: data 1 mirror 1 pot 0 control 04 +F0: data 0 mirror 0 pot 0 control 44 +F1: data 1 mirror 1 pot 0 control 44 +F2: data 1 mirror 1 pot 0 control 44 +F3: data 1 mirror 1 pot 0 control 40 +F4: data 1 mirror 1 pot 0 control 04 +F5: data 1 mirror 1 pot 0 control 04 +F6: data 1 mirror 1 pot 0 control 00 +F7: data 1 mirror 1 pot 0 control 80 +G0: data 1 mirror 1 pot 0 control 40 +G1: data 1 mirror 1 pot 0 control 40 +G2: data 1 mirror 1 pot 0 control 80 +G3: data 0 mirror 0 pot 0 control 00 +G4: data 0 mirror 0 pot 0 control 00 +G5: data 0 mirror 0 pot 0 control 00 +G6: data 0 mirror 0 pot 0 control 44 +G7: data 0 mirror 0 pot 0 control 00 +H0: data 0 mirror 0 pot 0 control 80 +H1: data 0 mirror 0 pot 0 control 40 +H2: data 0 mirror 0 pot 0 control 44 +H3: data 0 mirror 0 pot 0 control 80 +H4: data 1 mirror 1 pot 0 control 80 +H5: data 0 mirror 0 pot 0 control 44 +H6: data 1 mirror 1 pot 0 control 40 +H7: data 1 mirror 1 pot 0 control 80 +I0: data 0 mirror 0 pot 0 control 00 +I1: data 0 mirror 0 pot 0 control 00 +I2: data 0 mirror 0 pot 0 control 82 +I3: data 0 mirror 0 pot 0 control 00 +I4: data 0 mirror 0 pot 0 control 00 +I5: data 0 mirror 0 pot 0 control 00 +I6: data 0 mirror 0 pot 0 control 00 +I7: data 0 mirror 0 pot 0 control 00 +J0: data 1 mirror 1 pot 0 control 44 +J1: data 1 mirror 1 pot 0 control 40 +J2: data 1 mirror 1 pot 0 control 80 +J3: data 0 mirror 0 pot 0 control 80 +J4: data 1 mirror 1 pot 0 control 40 +J5: data 1 mirror 1 pot 0 control 80 +J6: data 0 mirror 0 pot 0 control 44 +J7: data 0 mirror 0 pot 0 control 84 +M0: data 1 mirror 1 control 06 +M1: data 1 mirror 1 control 06 +M2: data 1 mirror 1 control 06 +M3: data 1 mirror 1 control 06 +M4: data 0 mirror 0 control 06 +M5: data 1 mirror 1 control 00 +M6: data 1 mirror 1 control 86 +M7: data 0 mirror 0 control 00 +GCR: 0x04 +GCR1: 0x00 +GCR2: 0x10 +GCR3: 0x40 +GCR4: 0x00 +GCR5: 0x00 +GCR6: 0x00 +GCR7: 0x00 +GCR8: 0x10 +GCR9: 0x20 +GCR10: 0x02 +GCR11: 0x00 +GCR12: 0x00 +GCR13: 0x00 +GCR14: 0x00 +GCR15: 0x10 +GCR16: 0x00 +GCR17: 0x00 +GCR18: 0x00 +GCR19: 0x01 +GCR20: 0x00 +GCR21: 0x00 +GCR22: 0x80 +GCR23: 0x01 diff --git a/models/bonw16/fd.rom b/models/bonw16/fd.rom new file mode 100644 index 00000000..b9044bfb --- /dev/null +++ b/models/bonw16/fd.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d650e9965b77bebceaa0c4c129b99171377e68a66f527277861522bf8c1843cf +size 16384 diff --git a/models/bonw16/gpio.c b/models/bonw16/gpio.c new file mode 100644 index 00000000..c16318e8 --- /dev/null +++ b/models/bonw16/gpio.c @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_GPO(GPD0, 0, PWROK), + _PAD_CFG_STRUCT(GPD1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPD12, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_A0, 0, PWROK), + _PAD_CFG_STRUCT(GPP_A1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A3, 0xfffffffd, 0x3c00), + PAD_CFG_TERM_GPO(GPP_A4, 0, NATIVE, TODO_0x21000000), + _PAD_CFG_STRUCT(GPP_A5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A8, 0x21001f00, 0x3c00), + _PAD_CFG_STRUCT(GPP_A9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_A11, 0xfffffffd, 0x3c00), + PAD_CFG_TERM_GPO(GPP_A12, 0, NATIVE, PWROK), + _PAD_CFG_STRUCT(GPP_A13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B0, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B5, 0x210000fd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B16, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B17, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B18, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B19, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B20, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_B21, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C0, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C16, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C17, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C18, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C19, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C20, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C21, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C22, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_C23, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_D0, 0, PWROK), + _PAD_CFG_STRUCT(GPP_D1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D16, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D17, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D18, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D19, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D20, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D21, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D22, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_D23, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_E0, 0, PWROK), + PAD_CFG_GPO(GPP_E1, 0, PWROK), + PAD_CFG_GPO(GPP_E2, 0, PWROK), + PAD_CFG_GPO(GPP_E3, 0, PWROK), + PAD_CFG_GPO(GPP_E4, 0, PWROK), + PAD_CFG_GPO(GPP_E5, 0, PWROK), + PAD_CFG_GPO(GPP_E6, 0, PWROK), + PAD_CFG_GPO(GPP_E7, 0, PWROK), + PAD_CFG_GPO(GPP_E8, 0, PWROK), + PAD_CFG_GPO(GPP_E9, 0, PWROK), + PAD_CFG_GPO(GPP_E10, 0, PWROK), + PAD_CFG_GPO(GPP_E11, 0, PWROK), + PAD_CFG_GPO(GPP_E12, 0, PWROK), + PAD_CFG_GPO(GPP_E13, 0, PWROK), + PAD_CFG_GPO(GPP_E14, 0, PWROK), + PAD_CFG_GPO(GPP_E15, 0, PWROK), + PAD_CFG_GPO(GPP_E16, 0, PWROK), + PAD_CFG_GPO(GPP_E17, 0, PWROK), + PAD_CFG_GPO(GPP_E18, 0, PWROK), + PAD_CFG_GPO(GPP_E19, 0, PWROK), + PAD_CFG_GPO(GPP_E20, 0, PWROK), + PAD_CFG_GPO(GPP_E21, 0, PWROK), + PAD_CFG_GPO(GPP_F0, 0, PWROK), + PAD_CFG_GPO(GPP_F1, 0, PWROK), + PAD_CFG_GPO(GPP_F2, 0, PWROK), + PAD_CFG_GPO(GPP_F3, 0, PWROK), + PAD_CFG_GPO(GPP_F4, 0, PWROK), + PAD_CFG_GPO(GPP_F5, 0, PWROK), + PAD_CFG_GPO(GPP_F6, 0, PWROK), + PAD_CFG_GPO(GPP_F7, 0, PWROK), + PAD_CFG_GPO(GPP_F8, 0, PWROK), + PAD_CFG_GPO(GPP_F9, 0, PWROK), + PAD_CFG_GPO(GPP_F10, 0, PWROK), + PAD_CFG_GPO(GPP_F11, 0, PWROK), + PAD_CFG_GPO(GPP_F12, 0, PWROK), + PAD_CFG_GPO(GPP_F13, 0, PWROK), + PAD_CFG_GPO(GPP_F14, 0, PWROK), + PAD_CFG_GPO(GPP_F15, 0, PWROK), + PAD_CFG_GPO(GPP_F16, 0, PWROK), + PAD_CFG_GPO(GPP_F17, 0, PWROK), + PAD_CFG_GPO(GPP_F18, 0, PWROK), + PAD_CFG_GPO(GPP_F19, 0, PWROK), + PAD_CFG_GPO(GPP_F20, 0, PWROK), + PAD_CFG_GPO(GPP_F21, 0, PWROK), + PAD_CFG_GPO(GPP_F22, 0, PWROK), + PAD_CFG_GPO(GPP_F23, 0, PWROK), + _PAD_CFG_STRUCT(GPP_H0, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H16, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H17, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H18, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_H19, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_I0, 0, PWROK), + _PAD_CFG_STRUCT(GPP_I1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_I16, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J0, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J12, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J13, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J14, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J15, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_J16, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_K0, 0, PWROK), + PAD_CFG_GPO(GPP_K1, 0, PWROK), + PAD_CFG_GPO(GPP_K2, 0, PWROK), + PAD_CFG_GPO(GPP_K3, 0, PWROK), + PAD_CFG_GPO(GPP_K4, 0, PWROK), + PAD_CFG_GPO(GPP_K5, 0, PWROK), + PAD_CFG_GPO(GPP_K6, 0, PWROK), + PAD_CFG_GPO(GPP_K7, 0, PWROK), + PAD_CFG_GPO(GPP_K8, 0, PWROK), + PAD_CFG_GPO(GPP_K9, 0, PWROK), + PAD_CFG_GPO(GPP_K10, 0, PWROK), + _PAD_CFG_STRUCT(GPP_R0, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R1, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R2, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R3, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R4, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R5, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R6, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R7, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R8, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R9, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R10, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R11, 0xfffffffd, 0x3c00), + _PAD_CFG_STRUCT(GPP_R12, 0xfffffffd, 0x3c00), + PAD_CFG_GPO(GPP_S0, 0, PWROK), + PAD_CFG_GPO(GPP_S1, 0, PWROK), + PAD_CFG_GPO(GPP_S2, 0, PWROK), + PAD_CFG_GPO(GPP_S3, 0, PWROK), + PAD_CFG_GPO(GPP_S4, 0, PWROK), + PAD_CFG_GPO(GPP_S5, 0, PWROK), + PAD_CFG_GPO(GPP_S6, 0, PWROK), + PAD_CFG_GPO(GPP_S7, 0, PWROK), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/models/bonw16/hda_verb.c b/models/bonw16/hda_verb.c new file mode 100644 index 00000000..9b3f8abd --- /dev/null +++ b/models/bonw16/hda_verb.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Nvidia, GenericHDMI */ + 0x10de00ab, /* Vendor ID */ + 0x10de0000, /* Subsystem ID */ + 6, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x10de0000), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x04, 0x585600f0), + AZALIA_PIN_CFG(0, 0x05, 0x185600f0), + AZALIA_PIN_CFG(0, 0x06, 0x185600f0), + AZALIA_PIN_CFG(0, 0x07, 0x185600f0), + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x15585802, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15585802), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60120), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x41a7932d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, MeteorLakeHDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_RESET(1), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/models/bonw16/me.rom b/models/bonw16/me.rom new file mode 100644 index 00000000..1c131001 --- /dev/null +++ b/models/bonw16/me.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8d49c08455a99cc7a688da35f7aef8b2cc2906a6fc4b789e5698beaebfdf1cc8 +size 10723328 diff --git a/models/bonw16/vbt.rom b/models/bonw16/vbt.rom new file mode 100644 index 00000000..b212394f --- /dev/null +++ b/models/bonw16/vbt.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7196a8c933d68ccbd4293c5f8a99bce513dd943f89605fd0c764537d08a6e489 +size 7680 diff --git a/tools/coreboot-collector b/tools/coreboot-collector index b0426101..ff7f10b7 160000 --- a/tools/coreboot-collector +++ b/tools/coreboot-collector @@ -1 +1 @@ -Subproject commit b0426101d6557b9bb0d5b89f773c657520dbdbd0 +Subproject commit ff7f10b7460c1e6063b5fe1b4c7bf0db9a392d03 From 70848a9e893253b6f9f249f9066d29e424b2a47e Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 24 Mar 2025 13:52:29 -0600 Subject: [PATCH 2/7] Add ARL-S FSP and bonw16 configs --- fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.bsf | 6674 +++++++++++++++++ fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.fd | 3 + .../MeteorLakeFspBinPkg/FspPkgPcdShare.dsc | 118 + .../Include/FirmwareVersionInfo.h | 55 + .../Include/FspProducerDataHeader.h | 80 + .../MeteorLakeFspBinPkg/Include/FspUpd.h | 48 + .../MeteorLakeFspBinPkg/Include/FspmUpd.h | 5394 +++++++++++++ .../MeteorLakeFspBinPkg/Include/FspsUpd.h | 4565 +++++++++++ .../MeteorLakeFspBinPkg/Include/FsptUpd.h | 420 ++ .../MeteorLakeFspBinPkg/Include/GpioConfig.h | 349 + .../Include/GpioSampleDef.h | 382 + .../Include/HobUsageDataHob.h | 59 + .../MeteorLakeFspBinPkg/Include/MemInfoHob.h | 347 + .../Include/SmbiosCacheInfoHob.h | 56 + .../Include/SmbiosProcessorInfoHob.h | 67 + .../Library/FspPcdListLib/FspPcdListLibNull.c | 49 + .../FspPcdListLib/FspPcdListLibNull.inf | 86 + .../MeteorLakeFspBinPkg.dec | 43 + models/bonw16/IntelGopDriver.inf | 9 + models/bonw16/MeteorLakeFspBinPkg | 1 + models/bonw16/chip.txt | 1 + models/bonw16/coreboot.config | 27 + models/bonw16/ec.config | 1 + models/bonw16/edk2.config | 9 + 24 files changed, 18843 insertions(+) create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.bsf create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.fd create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FirmwareVersionInfo.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspProducerDataHeader.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspUpd.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspmUpd.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspsUpd.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FsptUpd.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioConfig.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioSampleDef.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/MemInfoHob.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosCacheInfoHob.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf create mode 100644 fsp/arl-s/5083.81/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec create mode 100644 models/bonw16/IntelGopDriver.inf create mode 120000 models/bonw16/MeteorLakeFspBinPkg create mode 100644 models/bonw16/chip.txt create mode 100644 models/bonw16/coreboot.config create mode 100644 models/bonw16/ec.config create mode 100644 models/bonw16/edk2.config diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.bsf b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.bsf new file mode 100644 index 00000000..fd662533 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.bsf @@ -0,0 +1,6674 @@ +/** @file + + Boot Setting File for Platform Configuration. + + Copyright (c) 2025, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + This file is automatically generated. Please do NOT modify !!! + +**/ + + + +GlobalDataDef + SKUID = 0, "DEFAULT" +EndGlobalData + + +StructDef + + Find "MTLUPD_T" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 87 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPowerGating 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xC0000000 + $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength 4 bytes $_DEFAULT_ = 0x10000000 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE036000 + $gSiPkgTokenSpaceGuid_PcdSerialIoUartDebugPciCfgBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x012 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode 1 bytes $_DEFAULT_ = 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartDataBits 1 bytes $_DEFAULT_ = 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMmioBase 4 bytes $_DEFAULT_ = 0xFE034000 + $gSiPkgTokenSpaceGuid_PcdSerialIo2ndUartPciCfgBase 4 bytes $_DEFAULT_ = 0x0 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_FspDebugHandler 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPolarity 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsEnable 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiDefaultCsOutput 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsState 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiNumber 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMmioBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiCsPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiClkPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMisoPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoSpiMosiPinMux 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cMmioBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cSdaPin 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cSclPin 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cPadsTerm 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoI2cNumber 1 bytes $_DEFAULT_ = 0xFF + + Find "MTLUPD_M" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 55 bytes + $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize 8 bytes $_DEFAULT_ = 0x400000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen 2 bytes $_DEFAULT_ = 0x200 + $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_IbeccEcDis 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_RcompResistor 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_RcompTarget 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3 2 bytes $_DEFAULT_ = 0, 1 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3 16 bytes $_DEFAULT_ = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 + $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SmramMask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RmtPerTask 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TrainTrace 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RxVrefTempCoeff 1 bytes $_DEFAULT_ = 0x6 + $gPlatformFspPkgTokenSpaceGuid_CaParityPatternRotation 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WckOffsetWa 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TsegSize 4 bytes $_DEFAULT_ = 0x0400000 + $gPlatformFspPkgTokenSpaceGuid_MmioSize 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DciClkEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DciDbcMode 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_KeepEarlyTrace 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size 2 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_IoeDebugEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmodeClkEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AetTraceHubMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_BiosTraceSinkMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 36 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VtdDisable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VtdIgdEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_VtdIopEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_InternalGfx 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaGvWpMask 1 bytes $_DEFAULT_ = 0x0F + $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_OCSafeMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_tRRSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWRDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWWDD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWSG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDG 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRWDD 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_tREFI32 4 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit3200Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit3600Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit4000Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit4400Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit4800Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit5200Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimit5600Mask 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FreqLimitMaskEn 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_TxVrefOverride 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_IsForceCkdBypass 1 bytes $_DEFAULT_ = 0x00 + Skip 59 bytes + $gPlatformFspPkgTokenSpaceGuid_Vdd2Mv 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SafeLoadingBiosEnableState 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRecoveryStatusEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_MrcPprStatus 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_RetryCount 1 bytes $_DEFAULT_ = 0x0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_VddVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_VddqVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_VppVoltage 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_Ratio 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCL 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCWL 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tFAW 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRAS 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRCDtRP 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_tREFI 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRFC 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_tRRD 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRTP 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFCpb 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC2 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRFC4 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tRRD_S 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCCD_L 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tCCD_L_WR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NModeSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIshEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DFETap1StepSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DFETap2StepSize 1 bytes $_DEFAULT_ = 0x00 + Skip 5 bytes + $gPlatformFspPkgTokenSpaceGuid_SaGvGear 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaGvFreq 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_GearRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DimmOdt 44 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_DFETap1 8 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_DFETap2 8 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_CsVrefLow 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CsVrefHigh 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CaVrefLow 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CaVrefHigh 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_RxVrefOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3 + $gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size 1 bytes $_DEFAULT_ = 0xFF + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xB0000000 + $gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0x9F000000 + $gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SaOcSupport 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_GtAdaptiveVoltage 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset 2 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_RootPortIndex 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn 6 bytes $_DEFAULT_ = 0x1, 0x1, 0x1, 0x1, 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisplayGpioPinMux 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigureDsmMtrr 1 bytes $_DEFAULT_ = 0x1 + Skip 12 bytes + $gPlatformFspPkgTokenSpaceGuid_LMemBar 8 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SaVoltageMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PcieResizableBarSupport 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd 36 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh2Enable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh3Method 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3RootPortPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EndPointPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EndPointHint 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiAspm 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_DmiHweq 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase23Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase3Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen3RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpre 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpo 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3Ltcpre 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3Ltcpo 8 bytes $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen3CoeffListCm 8 bytes $_DEFAULT_ = 0x04, 0x06, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen3CoeffListCp 8 bytes $_DEFAULT_ = 0x05, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortRxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortRxPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortTxPreset 8 bytes $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen4CoeffListCm 8 bytes $_DEFAULT_ = 0x04, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen4CoeffListCp 8 bytes $_DEFAULT_ = 0x05, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase23Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase3Bypass 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPortTxPreset 8 bytes $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07 + $gPlatformFspPkgTokenSpaceGuid_Gen4RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Gen4LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpre 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpo 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPresetEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPortTxPreset 8 bytes $_DEFAULT_ = 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiAspmL1ExitLatency 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4RtcoRtpoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4LtcoEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4Ltcpo 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmL1ExitLatency 1 bytes $_DEFAULT_ = 0x4 + $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4Ltcpre 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DmiL1ssEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 7 bytes + $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioBase 4 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioLimit 4 bytes $_DEFAULT_ = 0xA1000000 + $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioBase 4 bytes $_DEFAULT_ = 0x90000000 + $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioLimit 4 bytes $_DEFAULT_ = 0x91000000 + $gPlatformFspPkgTokenSpaceGuid_EcExtraIoBase 2 bytes $_DEFAULT_ = 0x6A0 + $gPlatformFspPkgTokenSpaceGuid_SioBaseAddress 2 bytes $_DEFAULT_ = 0x0680 + $gPlatformFspPkgTokenSpaceGuid_ApicLocalAddress 4 bytes $_DEFAULT_ = 0xFEE00000 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBar 4 bytes $_DEFAULT_ = 0xA0000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Bar 4 bytes $_DEFAULT_ = 0xA2000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Bar 4 bytes $_DEFAULT_ = 0xA4000000 + $gPlatformFspPkgTokenSpaceGuid_BistOnReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HyperThreading 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CpuRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuRatio 1 bytes $_DEFAULT_ = 0x1C + $gPlatformFspPkgTokenSpaceGuid_BootMaxFrequency 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_FClkFrequency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmxEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingDownBin 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TmeEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DfdEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffset 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOffsetPrefix 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageMode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterVoltageOverride 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterAdaptiveVoltage 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffset 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOffsetPrefix 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageMode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PerCoreVoltageOverride 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreAdaptiveVoltage 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_OcTvb 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcoreTvbTempThreshold0 1 bytes $_DEFAULT_ = 0x46 + $gPlatformFspPkgTokenSpaceGuid_PcoreTvbTempThreshold1 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_EcoreTvbTempThreshold0 1 bytes $_DEFAULT_ = 0x46 + $gPlatformFspPkgTokenSpaceGuid_EcoreTvbTempThreshold1 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_TvbConfigLimitSelect 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerPcoreRatioDownBinAboveT0 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PerPcoreRatioDownBinAboveT1 8 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PerPcoreGrRatioDownBinAboveT0 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PerPcoreGrRatioDownBinAboveT1 8 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PerEcoreCcpRatioDownBinAboveT0 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerEcoreCcpRatioDownBinAboveT1 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck 1 bytes $_DEFAULT_ = 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2 2 bytes $_DEFAULT_ = 100 + $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CoreRatioExtensionMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold 2 bytes $_DEFAULT_ = 0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PvdMode 2 bytes $_DEFAULT_ = 0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ActiveSocNorthAtomCoreCount 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ComputeDieSscEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocDieSscEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GpioOverride 1 bytes $_DEFAULT_ = 0x00 + Skip 10 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SocBclkOcFrequency 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs 1 bytes $_DEFAULT_ = 0x00 + Skip 11 bytes + $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IaIccMax 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_GtIccMax 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaIccUnlimitedMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaIccMax 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccsaBootVoltageSel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuD2dRatio 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CpuBandgapRefMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VcciaBootVoltageSel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GranularRatioOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreGranularityBins 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterGranularityBins 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CoreMinRatio 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPreMem 24 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysSlope 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PsysPmax 2 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_AcLoadline 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_DcLoadline 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold 12 bytes $_DEFAULT_ = 0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold 12 bytes $_DEFAULT_ = 0x14,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x14,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold 12 bytes $_DEFAULT_ = 0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00 + $gPlatformFspPkgTokenSpaceGuid_Psi3Enable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_Psi4Enable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_ImonSlope 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ImonOffset 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_TdcEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_TdcLock 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_DlvrRfiFrequency 2 bytes $_DEFAULT_ = 0x055A + $gPlatformFspPkgTokenSpaceGuid_DlvrSpreadSpectrumPercentage 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_DlvrRfiEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PreWake 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RampUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RampDown 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PS1toPS0DynamicCutoffEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PS1toPS0MCoef 12 bytes $_DEFAULT_ = 0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00 + $gPlatformFspPkgTokenSpaceGuid_PS1toPS0CCoef 12 bytes $_DEFAULT_ = 0xD0,0x07,0xD0,0x07,0xD0,0x07,0xD0,0x07,0xD0,0x07,0xD0,0x07 + $gPlatformFspPkgTokenSpaceGuid_PS2toPS1DynamicCutoffEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PS2toPS1MCoef 12 bytes $_DEFAULT_ = 0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00,0x64,0x00 + $gPlatformFspPkgTokenSpaceGuid_PS2toPS1CCoef 12 bytes $_DEFAULT_ = 0xF4,0x01,0xF4,0x01,0xF4,0x01,0xF4,0x01,0xF4,0x01,0xF4,0x01 + $gPlatformFspPkgTokenSpaceGuid_VccInDemotionEnable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_VccInDemotionQuiescentPowerInMw 6 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_VccInDemotionCapacitanceInUf 24 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysOffset 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate 6 bytes $_DEFAULT_ = 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_IccMax 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_FastVmodeOffset 6 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SvidStabilizationDelay 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_VccDemotionShutdownThreshold 6 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IccLimit 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_CepEnable 6 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SirpEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Irms 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysFullScale 4 bytes $_DEFAULT_ = 0x5DC0 + $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold 4 bytes $_DEFAULT_ = 0x1770 + $gPlatformFspPkgTokenSpaceGuid_PsysFullScale 4 bytes $_DEFAULT_ = 0x30D40 + $gPlatformFspPkgTokenSpaceGuid_PsysCriticalThreshold 4 bytes $_DEFAULT_ = 0x1FBD0 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa 1 bytes $_DEFAULT_ = 0x0D + $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PerCoreMaxRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterMaxRatio 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimit 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CorePllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PerCoreDisableConfiguration 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimitNew 18 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ForcePcoreResidency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VrLimitBypass 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection 1 bytes $_DEFAULT_ = 0x01 + Skip 47 bytes + $gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PrmrrSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + Skip 8 bytes + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ApStartupBase 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TgaSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000 + $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 32 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0 28 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPort80Route 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase 2 bytes $_DEFAULT_ = 0xEFA0 + $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchPcieClkSrcUsage 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchPcieClkSrcClkReq 16 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchAdditionalMmioRsvd 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchPcieRpEnableMask 4 bytes $_DEFAULT_ = 0xFFFFFF + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask 2 bytes $_DEFAULT_ = 0xFFF + $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable 2 bytes $_DEFAULT_ = 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable 2 bytes $_DEFAULT_ = 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_HdaDiscBtOffEnabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchAdditionalIoRsvd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkBPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HdaDiscBtOffSspLink 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocAdditionalMmioRsvd 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable 6 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable 4 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SocAdditionalIoRsvd 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaSubSystemIds 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ExtendedBiosDecodeRange 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase 4 bytes $_DEFAULT_ = 0xF8000000 + $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit 4 bytes $_DEFAULT_ = 0xF9FFFFFF + $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x32 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits 1 bytes $_DEFAULT_ = 0x8 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase 4 bytes $_DEFAULT_ = 0xFE036000 + $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuSaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IaAtomPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie0En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie1En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie2En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie3En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssXdciEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TcssDma0En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssDma1En 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_HobBufferSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ECT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SOT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDMPRT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RCVET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_JWRL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EWRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ERDTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_UNMATCHEDWRTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDTC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVC1D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DDR5ODTTIMING 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VIEWPINCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDDQSODTT 1 bytes $_DEFAULT_ = 0x01 + Skip 6 bytes + $gPlatformFspPkgTokenSpaceGuid_RDDQODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDEQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDCTLET 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PPR 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_WRTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDTC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRVC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVC2D 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXVREFPERBIT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDVC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_LCT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TAT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LVRAUTOTRIM 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ALIASCHK 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RMC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ROWHAMMER 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMRONT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TXTCO 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CLKTCO 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDSR 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDDS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CMDTXEQ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTRETRAIN 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PWRMETER 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DDRPRECOMP 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RDVREFDC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VDDQT 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RMTBIT 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DQDQSSWZ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_REFPI 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXSALCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VCCCLKFF 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCC 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCDOWNSTREAM 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCQCLK 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCRISEFALL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DATAPILIN 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DDR5XTALK 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DCCLP5WCKDCA 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXUNMATCHEDCAL 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TXRK2RK 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RXRK2RK 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_OPTIMIZECOMP 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTDIMMDFE 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTDS 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WRTEQ 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EccSupport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Ibecc 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccParity 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionEnable 8 bytes $_DEFAULT_ = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionBase 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionMask 16 bytes $_DEFAULT_ = 0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F + $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionOverallBase 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_RemapEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RankInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ChHashEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableExtts 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RhSelect 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DccSingleRankTrack 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Write0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdpSharedClock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_ChHashMask 2 bytes $_DEFAULT_ = 0x830 + $gPlatformFspPkgTokenSpaceGuid_BClkFrequency 4 bytes $_DEFAULT_ = 100000000 + $gPlatformFspPkgTokenSpaceGuid_Idd3n 2 bytes $_DEFAULT_ = 0x1A + $gPlatformFspPkgTokenSpaceGuid_Idd3p 2 bytes $_DEFAULT_ = 0x0B + $gPlatformFspPkgTokenSpaceGuid_CMDNORM 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0x06 + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xAC + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xD4 + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm0 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm1 1 bytes $_DEFAULT_ = 0xDD + $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_WriteThreshold 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnCmdRate 1 bytes $_DEFAULT_ = 0x07 + $gPlatformFspPkgTokenSpaceGuid_McRefreshRate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EpgEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OpportunisticSref 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerDownMode 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SafeModeOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcSafeMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RetrainToWorkingChannel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_DdrSafeMode 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_McSafeMode 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BoardStackUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CleanMemory 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEnPreMem 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PwDownMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80 + $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PwDownIdleTimer 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BclkRfiFreq 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieImrRpLocation 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieImrRpSelection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_DdrOneDpc 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_OverrideDriverType 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Lp5BypassVddqLimits 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccIogVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VccClkVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask 1 bytes $_DEFAULT_ = 0xB + $gPlatformFspPkgTokenSpaceGuid_RefreshWm 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CmdMirror 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_OppSrefIdleTmr 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_BoardTopology 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RxDqsDelayTempCoeff 1 bytes $_DEFAULT_ = 0x4 + Skip 15 bytes + $gPlatformFspPkgTokenSpaceGuid_PprTestType 1 bytes $_DEFAULT_ = 0x3 + $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpd 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_LockPTMregs 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_BdatTestType 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize 4 bytes $_DEFAULT_ = 0x0400000 + $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HgSubSystemId 2 bytes $_DEFAULT_ = 0x2112 + $gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VgaInitControl 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VbtPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VgaMessage 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 75 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PprRunOnce 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PprRunAtFastboot 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairType 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprErrorInjection 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprForceRepair 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairController 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairChannel 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairDimm 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairRank 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairRow 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrLow 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrHigh 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairBankGroup 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PprRepairBank 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DIMMODTCASPLIT 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CMDDSSPLIT 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CMDSRSPLIT 1 bytes $_DEFAULT_ = 0x0 + Skip 23 bytes + $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800 + $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 12 bytes $_DEFAULT_ = 0x00 + Skip 16 bytes + $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocBclkPllOn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuBclkPllOn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverEn 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverPostCur 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverPreCur 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiUpPortTranPreset 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiUpPortTranPresetEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiRtlepceb 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00 + Skip 100 bytes + $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x02 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugCtsPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugPciCfgBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_MemSSAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_NguMaxOcRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVoltageMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVoltageOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVoltageOffset 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_NguVfPointCount 1 bytes $_DEFAULT_ = 0x00 + Skip 11 bytes + $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetMode 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffset 30 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_GtVfPointCount 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MrcMustStaticSpdData 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TmeExcludeBase 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TmeExcludeSize 8 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_GenerateNewTmeKey 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CkdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + + Find "MTLUPD_S" + $gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02 + Skip 55 bytes + $gPlatformFspPkgTokenSpaceGuid_LogoPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_BltBufferSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_Device4Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ShowSpiController 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TurboMode 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SataPortDevSlpPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable 16 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_XdciEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PxRcConfig 8 bytes $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B + $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute 1 bytes $_DEFAULT_ = 0x0E + $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect 1 bytes $_DEFAULT_ = 0x09 + $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum 1 bytes $_DEFAULT_ = 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity 14 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable 14 bytes $_DEFAULT_ = 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPinMux 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiClkPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMisoPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMosiPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate 28 bytes $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits 7 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating 7 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable 7 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x01, 0x01, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow 7 bytes $_DEFAULT_ = 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cMode 2 bytes $_DEFAULT_ = 0, 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPadTermination 2 bytes $_DEFAULT_ = 0, 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPadTermination 2 bytes $_DEFAULT_ = 0, 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPinMux 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPadTermination 2 bytes $_DEFAULT_ = 0, 0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing 12 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPinMuxing 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPinMuxing 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination 12 bytes $_DEFAULT_ = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPadTermination 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination 3 bytes $_DEFAULT_ = 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPadTermination 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination 4 bytes $_DEFAULT_ = 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 80 bytes + $gPlatformFspPkgTokenSpaceGuid_PchLanEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed 1 bytes $_DEFAULT_ = 0x02 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PciePtm 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiPowerGatingDis 1 bytes $_DEFAULT_ = 0x01 + Skip 28 bytes + $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + Skip 5 bytes + $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeHostDeviceEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax 1 bytes $_DEFAULT_ = 0x64 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage 2 bytes $_DEFAULT_ = 0x01A4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax 1 bytes $_DEFAULT_ = 0xC8 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x0C + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x036 + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime 1 bytes $_DEFAULT_ = 0x2B + $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime 2 bytes $_DEFAULT_ = 0x0096 + $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_NphyBinPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_NphyBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchXhciHsiiEnable 1 bytes $_DEFAULT_ = 0x1 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PchGpioUnlockDataPtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchGpioUnlockDataSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CnviMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtCore 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload 1 bytes $_DEFAULT_ = 0x01 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AmtEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_FwProgress 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled 1 bytes $_DEFAULT_ = 0x0 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios 2 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs 58 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PavpEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_D3HotEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 48 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x06,0x11,0x00,0x04,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin 8 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SkipFspGop 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_VpuEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit 1 bytes $_DEFAULT_ = 0x0A + $gPlatformFspPkgTokenSpaceGuid_TcNotifyIgd 1 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPort 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortBus 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortDev 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase 4 bytes $_DEFAULT_ = 0x90000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base 4 bytes $_DEFAULT_ = 0x92000000 + $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base 4 bytes $_DEFAULT_ = 0x94000000 + $gPlatformFspPkgTokenSpaceGuid_TcssCpuUsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcPdEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TcssAuxOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_TcssHslOri 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_UsbOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ITbtPcieRootPortEn 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ITbtForcePowerOnTimeoutInMs 2 bytes $_DEFAULT_ = 0x1F4 + $gPlatformFspPkgTokenSpaceGuid_ITbtConnectTopologyTimeoutInMs 2 bytes $_DEFAULT_ = 0x1388 + $gPlatformFspPkgTokenSpaceGuid_VccSt 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_ITbtDmaLtr 4 bytes $_DEFAULT_ = 0xFF,0x97,0xFF,0x97 + $gPlatformFspPkgTokenSpaceGuid_CpuCrashLogEnable 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_PtmEnabled 4 bytes $_DEFAULT_ = 0, 0, 0, 0 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrEnable 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0xC8,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideMultiplier 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpNonSnoopLatencyOverrideValue 8 bytes $_DEFAULT_ = 0xC8,0x00,0xC8,0x00,0xC8,0x00,0xC8,0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpForceLtrOverride 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SaPcieItbtRpLtrConfigLock 4 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_TxtEnable 1 bytes $_DEFAULT_ = 0 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_CpuBistData 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi 4 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_BootFrequency 1 bytes $_DEFAULT_ = 0x02 + Skip 3 bytes + $gPlatformFspPkgTokenSpaceGuid_PpinSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemSize 1 bytes $_DEFAULT_ = 0xff + $gPlatformFspPkgTokenSpaceGuid_SmbiosType4MaxSpeedOverride 2 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AesEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_AvxDisable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_X2ApicEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction 56 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable 5 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase 10 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaPme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchIoApicId 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable 2 bytes $_DEFAULT_ = 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshI3cEnable 1 bytes $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable 12 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchCrid 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThcAssignment 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcInterruptPinMuxing 8 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcMode 2 bytes $_DEFAULT_ = 0x0, 0x0 + $gPlatformFspPkgTokenSpaceGuid_ThcWakeOnTouch 2 bytes $_DEFAULT_ = 0x0, 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr 8 bytes $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + $gPlatformFspPkgTokenSpaceGuid_ThcResetPad 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcResetPadTrigger 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiConnectionSpeed 8 bytes $_DEFAULT_ = 0x40,0x66,0x03,0x01,0x40,0x66,0x03,0x01 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiLimitPacketSize 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportHeaderAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportBodyAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiOutputReportAddress 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiReadOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiWriteOpcode 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiFlags 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_ThcResetSequencingDelay 4 bytes $_DEFAULT_ = 0x2C,0x01,0x2C,0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B + $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates 29 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqLocalTxOverrideEn 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3NoOfPresetOrCoeff 29 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x05, 0x03, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor0List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor0List 29 bytes $_DEFAULT_ = 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor1List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor1List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor2List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor2List 29 bytes $_DEFAULT_ = 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor3List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor3List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor5List 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor6List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor7List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor7List 29 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor8List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor8List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor9List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset0List 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset1List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset2List 29 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x06, 0x07, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset3List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x07, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset4List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x09, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset7List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset8List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset10List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1DpTxPreset 29 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1UpTxPreset 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x07, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh2LocalTxOverridePreset 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqLocalTxOverrideEn 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3NoOfPresetOrCoeff 29 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor0List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor0List 29 bytes $_DEFAULT_ = 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor1List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor1List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor2List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor2List 29 bytes $_DEFAULT_ = 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor3List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor3List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor5List 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor6List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor7List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor7List 29 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor8List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor8List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor9List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset0List 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset1List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset2List 29 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x06, 0x07, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset3List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset4List 29 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x00, 0x09, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset7List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset8List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset10List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1DpTxPreset 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1UpTxPreset 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x07, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh2LocalTxOverridePreset 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqLocalTxOverrideEn 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3NoOfPresetOrCoeff 29 bytes $_DEFAULT_ = 0x03, 0x03, 0x03, 0x04, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor0List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor0List 29 bytes $_DEFAULT_ = 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor1List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor1List 29 bytes $_DEFAULT_ = 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor2List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor2List 29 bytes $_DEFAULT_ = 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor3List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor3List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor5List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor6List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor7List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor7List 29 bytes $_DEFAULT_ = 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor8List 29 bytes $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor8List 29 bytes $_DEFAULT_ = 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset0List 29 bytes $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset1List 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset2List 29 bytes $_DEFAULT_ = 0x07, 0x07, 0x07, 0x06, 0x07, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset3List 29 bytes $_DEFAULT_ = 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset4List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset5List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset6List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset7List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset8List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset9List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset10List 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1DpTxPreset 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1UpTxPreset 29 bytes $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh2LocalTxOverridePreset 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPhBypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPhBypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPhBypass 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3PcetTimer 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4PcetTimer 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5PcetTimer 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieGen3TsLockTimer 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen4TsLockTimer 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieGen5TsLockTimer 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieSetSecuredRegisterLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DGWait 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PcieRpTestAspmOc 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieCfgDump 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieFiaProgramming 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm 1 bytes $_DEFAULT_ = 0x04 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd 8 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort 3 bytes $_DEFAULT_ = 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay 3 bytes $_DEFAULT_ = 100, 100, 100 + $gPlatformFspPkgTokenSpaceGuid_UfsEnable 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_UfsInlineEncryption 2 bytes $_DEFAULT_ = 0, 0 + $gPlatformFspPkgTokenSpaceGuid_IehMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocTTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SocT0Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SocT1Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SocT2Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SocTTEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocTTState13Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SocTTLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchT0Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT1Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchT2Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PchTTEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchTTLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IoeTTSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_IoeT0Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_IoeT1Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_IoeT2Level 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_IoeTTEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_IoeTTLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataP0T1M 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataP0T2M 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SataP0T3M 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1T1M 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataP1T2M 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_SataP1T3M 1 bytes $_DEFAULT_ = 0x03 + $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting 1 bytes $_DEFAULT_ = 0x01 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel 2 bytes $_DEFAULT_ = 0x0073 + $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07 + $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer 1 bytes $_DEFAULT_ = 0x00 + Skip 9 bytes + $gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_SendEcCmd 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_EcCmdLock 1 bytes $_DEFAULT_ = 0xFF + Skip 6 bytes + $gPlatformFspPkgTokenSpaceGuid_EcProvisionEav 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_EcBiosGuardCmdLock 8 bytes $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF + $gPlatformFspPkgTokenSpaceGuid_SiSkipSsidProgramming 1 bytes $_DEFAULT_ = 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSvid 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSsid 2 bytes $_DEFAULT_ = 0x0000 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry 2 bytes $_DEFAULT_ = 0x0000 + $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable 16 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsOnEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl 1 bytes $_DEFAULT_ = 0x04 + $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcOverride 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcSel 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PmcWdtTimerEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieClockGating 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PciePowerGating 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_PcieFomsCp 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_LinkDownGpios 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran 10 bytes $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C + $gPlatformFspPkgTokenSpaceGuid_SkipPamLock 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RenderStandby 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_ConfigureGT 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_GtFreqMax 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RC1pGtFreqEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_RC1pMediaFreqEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PchTsnMultiVcEnable 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PmcLimitC3AndDeeperWA 1 bytes $_DEFAULT_ = 0x01 + Skip 10 bytes + $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_ConfigureMedia 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode 1 bytes $_DEFAULT_ = 0x01 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_VerticalResolution 4 bytes $_DEFAULT_ = 0x00000000 + $gPlatformFspPkgTokenSpaceGuid_MediaStandby 1 bytes $_DEFAULT_ = 0x1 + $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd 32 bytes $_DEFAULT_ = 0x00 + Skip 32 bytes + $gPlatformFspPkgTokenSpaceGuid_EnableRsr 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem1 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Hwp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio 1 bytes $_DEFAULT_ = 0x14 + $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ApIdleManner 1 bytes $_DEFAULT_ = 0x02 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Eist 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TStates 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_BiProcHot 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_Cx 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1e 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CStatePreWake 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_TimedMwait 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ProcHotLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRatio 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_StateRatio 40 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit3 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Boost 2 bytes $_DEFAULT_ = 0x0 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CcfAutoGv 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_RaceToHalt 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounter 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem2 4 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_EnablePerCorePState 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_HwpLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_DualTauBoost 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_StepDownMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorManagement 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorDisplayDisconnect 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnableRp 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PowerFloorPcieGenDowngrade 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest 13 bytes $_DEFAULT_ = 0x00 + Skip 16 bytes + $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage 1 bytes $_DEFAULT_ = 0x2 + $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_CseDataResilience 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_MePostMemRsvd 16 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock 1 bytes $_DEFAULT_ = 0x00 + Skip 2 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency 58 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency 58 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue 58 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier 29 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 + $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue 58 bytes $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + Skip 1 bytes + $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue 58 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0xFF + $gPlatformFspPkgTokenSpaceGuid_PmcPchLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchPmErDebugMode 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_CppmFaEn 1 bytes $_DEFAULT_ = 0x01 + $gPlatformFspPkgTokenSpaceGuid_PchLanWOLFastSupport 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit 1 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrOverrideSpecComplaint 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 + Skip 71 bytes + $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment 1 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio 8 bytes $_DEFAULT_ = 0x00 + $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore 8 bytes $_DEFAULT_ = 0x00 + Skip 4 bytes + $gPlatformFspPkgTokenSpaceGuid_FspEventHandler 4 bytes $_DEFAULT_ = 0x0 + $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00 + +EndStruct + + +List &EN_DIS + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPowerGating + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase + Selection 0 , "0x3F8" + Selection 1 , "0x2F8" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartEnable + Selection 0 , "Disable" + Selection 1 , "Enable and Initialize" + Selection 2 , "Enable without Initializing" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIo2ndUartAutoFlow + Selection 0 , " Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen + Selection 0x100 , "256 Bytes" + Selection 0x200 , "512 Bytes" + Selection 0x400 , "1024 Bytes" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SmramMask + Selection 0 , " Neither" + Selection 1 , "AB-SEG" + Selection 2 , "H-SEG" + Selection 3 , " Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TsegSize + Selection 0x0400000 , "4MB" + Selection 0x01000000 , "16MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption + Selection 0 , "Disabled" + Selection 2 , "Enabled Trace Active" + Selection 4 , "Enabled Trace Ready" + Selection 6 , "Enable Trace Power-Off" + Selection 7 , "Manual" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DciDbcMode + Selection 0 , "Disabled" + Selection 1 , "USB2 DbC" + Selection 2 , "USB3 DbC" + Selection 3 , "Both" + Selection 4 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size + Selection 0x00 , "1MB" + Selection 0x03 , "8MB" + Selection 0x06 , "64MB" + Selection 0x07 , "128MB" + Selection 0x08 , "256MB" + Selection 0x09 , "512MB" + Selection 0x0A , "1GB" + Selection 0x0B , "2GB" + Selection 0x0C , "4GB" + Selection 0x0D , "8GB" + Selection 0x0E , "0MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AetTraceHubMode + Selection 0 , "SOC Trace Hub" + Selection 1 , "PCH Trace Hub" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BiosTraceSinkMode + Selection 0 , "SOC Trace Hub" + Selection 1 , "PCH Trace Hub" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect + Selection 0 , " Both" + Selection 1 , " ClkA" + Selection 2 , " ClkB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc + Selection 0x00 , "0MB" + Selection 0x01 , "32MB" + Selection 0x02 , "64MB" + Selection 0x03 , "96MB" + Selection 0x04 , "128MB" + Selection 0xF0 , "4MB" + Selection 0xF1 , "8MB" + Selection 0xF2 , "12MB" + Selection 0xF3 , "16MB" + Selection 0xF4 , "20MB" + Selection 0xF5 , "24MB" + Selection 0xF6 , "28MB" + Selection 0xF7 , "32MB" + Selection 0xF8 , "36MB" + Selection 0xF9 , "40MB" + Selection 0xFA , "44MB" + Selection 0xFB , "48MB" + Selection 0xFC , "52MB" + Selection 0xFD , "56MB" + Selection 0xFE , "60MB" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_UserBd + Selection 0 , "Mobile/Mobile Halo" + Selection 1 , "Desktop/DT Halo" + Selection 5 , "ULT/ULX/Mobile Halo" + Selection 7 , "UP Server" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss + Selection 0 , "Disabled" + Selection 1 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit + Selection 1067 , "1067" + Selection 1333 , "1333" + Selection 1600 , "1600" + Selection 1867 , "1867" + Selection 2133 , "2133" + Selection 2400 , "2400" + Selection 2667 , "2667" + Selection 2933 , "2933" + Selection 0 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaGv + Selection 0 , "Disabled" + Selection 1 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaGvWpMask + Selection 0x3 , "Points0_1" + Selection 0x7 , "Points0_1_2" + Selection 0xF , "AllPoints0_1_2_3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl + Selection 0 , "Auto" + Selection 1 , "Manual" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected + Selection 0 , "Default SPD Profile" + Selection 1 , "Custom Profile" + Selection 2 , "XMP Profile 1" + Selection 3 , "XMP Profile 2" + Selection 4 , "XMP Profile 3" + Selection 5 , "XMP User Profile 4" + Selection 6 , "XMP User Profile 5" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Vdd2Mv + Selection 0 , "Default" + Selection 1200 , "1.20 Volts" + Selection 1350 , "1.35 Volts ..." +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RefClk + Selection 0 , "133MHz" + Selection 1 , "100MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus + Selection 0 , " PASS" + Selection 1 , " FAIL(Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MrcPprStatus + Selection 0 , " PASS" + Selection 1 , " FAIL(Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RetryCount + Selection 0 , " Default" + Selection 1 , "3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VddVoltage + Selection 0 , "Default" + Selection 1200 , "1.20 Volts" + Selection 1250 , "1.25 Volts" + Selection 1300 , "1.30 Volts" + Selection 1350 , "1.35 Volts" + Selection 1400 , "1.40 Volts" + Selection 1450 , "1.45 Volts" + Selection 1500 , "1.50 Volts" + Selection 1550 , "1.55 Volts" + Selection 1600 , "1.60 Volts" + Selection 1650 , "1.65 Volts" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_Ratio + Selection 0 , "Auto" + Selection 4 , "4" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 9 , "9" + Selection 10 , "10" + Selection 11 , "11" + Selection 12 , "12" + Selection 13 , "13" + Selection 14 , "14" + Selection 15 , "15" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_tWR + Selection 0 , "Auto" + Selection 5 , "5" + Selection 6 , "6" + Selection 7 , "7" + Selection 8 , "8" + Selection 10 , "10" + Selection 12 , "12" + Selection 14 , "14" + Selection 16 , "16" + Selection 18 , "18" + Selection 20 , "20" + Selection 24 , "24" + Selection 30 , "30" + Selection 34 , "34" + Selection 40 , "40" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay + Selection 0 , "iGFX" + Selection 3 , "AUTO" + Selection 4 , "Hybrid Graphics" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size + Selection 0 , "2GB" + Selection 1 , "4GB" + Selection 2 , "6GB" + Selection 3 , "8GB" + Selection 4 , "10GB" + Selection 5 , "12GB" + Selection 6 , "14GB" + Selection 7 , "16GB" + Selection 8 , "18GB" + Selection 9 , "20GB" + Selection 10 , "22GB" + Selection 11 , "24GB" + Selection 12 , "26GB" + Selection 13 , "28GB" + Selection 14 , "30GB" + Selection 15 , "32GB" + Selection 0xFF , "No Allocation" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode + Selection 0 , " Adaptive" + Selection 1 , " Override" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming + Selection 0 , " Disabled" + Selection 1 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig + Selection 0 , "Disabled" + Selection 1 , "eDP" + Selection 2 , "MIPI DSI" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed + Selection 0 , "Auto" + Selection 1 , "Gen1" + Selection 2 , "Gen2" + Selection 3 , "Gen3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh2Enable + Selection 0 , "Disable phase2" + Selection 1 , "Enable phase2" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh3Method + Selection 0 , "Auto" + Selection 1 , "HwEq" + Selection 2 , "SwEq" + Selection 3 , "StaticEq" + Selection 4 , "BypassPhase3" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiL1ssEnable + Selection 0 , " Auto" + Selection 1 , " L1.2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount + Selection 0 , "Disable all big cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all big cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency + Selection 0 , "800 MHz" + Selection 1 , " 1 GHz" + Selection 2 , " 400 MHz" + Selection 3 , " Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "No Change" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveSmallCoreCount + Selection 0 , "Disable all small cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 3 , "3" + Selection 0xFF , "Active all small cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix + Selection 0 , "Positive" + Selection 1 , "Negative" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CoreVfConfigScope + Selection 0 , "All-core" + Selection 1 , "Per-core" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TvbConfigLimitSelect + Selection 0 , "Per CCP Module" + Selection 1 , "Per P-core Group" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck + Selection 0 , "Disable" + Selection 1 , "L1" + Selection 2 , "L2" + Selection 3 , "Both" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ActiveSocNorthAtomCoreCount + Selection 0 , "Disable all Soc-North Atom cores" + Selection 1 , "1" + Selection 2 , "2" + Selection 0xFF , "Active all cores" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Only Smm GPRs Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VccsaBootVoltageSel + Selection 0 , " Nominal" + Selection 1 , " High Voltage(up to 1.2/1.3V)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuBandgapRefMode + Selection 0 , " Normal" + Selection 1 , " Bandgap Bypassed" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VcciaBootVoltageSel + Selection 0 , " Nominal" + Selection 1 , " High Voltage" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride + Selection 0 , " 2400MHz" + Selection 1 , " 1600MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup + Selection 0 , "Enable" + Selection 1 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit + Selection 1 , "Enable" + Selection 0 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle + Selection 1 , "Enable" + Selection 0 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate + Selection 0 , " Fast/2" + Selection 1 , " Fast/4" + Selection 2 , " Fast/8" + Selection 3 , " Fast/16" + Selection 0xFF , " Ignore the configuration" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode + Selection 0 , " Disable" + Selection 1 , " Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection + Selection 1 , "Enable" + Selection 0 , "Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType + Selection 0 , " VC0" + Selection 1 , " VC1" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating + Selection 0 , " POR" + Selection 1 , " Force Enable" + Selection 2 , " Force Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency + Selection 4 , " 96MHz" + Selection 3 , " 48MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode + Selection 0 , " 2T" + Selection 2 , " 4T" + Selection 3 , " 8T" + Selection 4 , " 16T" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber + Selection 0 , "SerialIoUart0" + Selection 1 , "SerialIoUart1" + Selection 2 , "SerialIoUart2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity + Selection 0 , " DefaultParity" + Selection 1 , " NoParity" + Selection 2 , " EvenParity" + Selection 3 , " OddParity" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits + Selection 0 , " DefaultStopBits" + Selection 1 , " OneStopBit" + Selection 2 , " OneFiveStopBits" + Selection 3 , " TwoStopBits" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating + Selection 0 , "Disabled" + Selection 1 , "Enabled" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate + Selection 3 , "9600" + Selection 4 , "19200" + Selection 6 , "56700" + Selection 7 , "115200" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize + Selection 0 , "Default" + Selection 1 , " 1 Byte" + Selection 2 , " 1 KB" + Selection 3 , " Max value" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RXSALCAL + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VCCCLKFF + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode + Selection 0 , "Protect base on address range" + Selection 1 , " Non-protected" + Selection 2 , " All protected" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RhSelect + Selection 0 , "Disable" + Selection 1 , "RFM" + Selection 2 , "pTRR" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported + Selection 0 , "False" + Selection 1 , "True" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit + Selection 0 , "BIT6" + Selection 1 , "BIT7" + Selection 2 , "BIT8" + Selection 3 , "BIT9" + Selection 4 , "BIT10" + Selection 5 , "BIT11" + Selection 6 , "BIT12" + Selection 7 , "BIT13" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency + Selection 100000000 , "100Hz" + Selection 125000000 , "125Hz" + Selection 167000000 , "167Hz" + Selection 250000000 , "250Hz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate + Selection 0 , "Disable" + Selection 5 , "2 CMDS" + Selection 7 , "3 CMDS" + Selection 9 , "4 CMDS" + Selection 11 , "5 CMDS" + Selection 13 , "6 CMDS" + Selection 15 , "7 CMDS" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_McRefreshRate + Selection 0 , "NORMAL Refresh" + Selection 1 , "1x Refresh" + Selection 2 , "2x Refresh" + Selection 3 , "4x Refresh" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_OpportunisticSref + Selection 0 , "Disabled" + Selection 1 , "Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PowerDownMode + Selection 0x0 , "No Power Down" + Selection 0x1 , "APD" + Selection 0x6 , "PPD DLL OFF" + Selection 0xFF , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout + Selection 0 , "Enabled" + Selection 1 , "Disabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PwDownMode + Selection 0x0 , "Enable" + Selection 0x1 , "Disable" + Selection 0x2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel + Selection 0 , "Disable" + Selection 1 , "Error Only" + Selection 2 , "Error and Warnings" + Selection 3 , "Load Error Warnings and Info" + Selection 4 , "Load Error Warnings and Info & Event" + Selection 5 , "Load Error Warnings Info and Verbose" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DdrOneDpc + Selection 0 , " Disabled" + Selection 1 , " Enabled on DIMM0 only" + Selection 2 , " Enabled on DIMM1 only" + Selection 3 , " Enabled" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_RefreshWm + Selection 0 , "Set Refresh Watermarks to Low" + Selection 1 , "Set Refresh Watermarks to High (Default)" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BdatTestType + Selection 0 , "RMT per Rank" + Selection 1 , "RMT per Bit" + Selection 2 , "Margin2D" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay + Selection 0 , " No Delay" + Selection 0xFFFF , " Auto Calulate T12 Delay" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_LidStatus + Selection 0 , " LidClosed" + Selection 1 , " LidOpen" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_VgaInitControl + Selection 0x0 , " NO VGA Init" + Selection 0x1 , " VGA Init" + Selection 0x3 , " VGA Init and VGA Exit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PprRepairType + Selection 0 , "Do not Repair (Default)" + Selection 1 , "Soft Repair" + Selection 2 , "Hard Repair" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode + Selection 0 , "SerialIoUartDisabled" + Selection 1 , "SerialIoUartPci" + Selection 2 , "SerialIoUartHidden" + Selection 3 , "SerialIoUartCom" + Selection 4 , "SerialIoUartSkipInit" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode + Selection 0 , "Regulation Mode" + Selection 1 , "Power Gate Mode" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetMode + Selection 0 , "Legacy" + Selection 1 , "Selection" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SataMode + Selection 0 , "AHCI" + Selection 1 , "RAID" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed + Selection 0 , " 24Mhz 2.5Gbps" + Selection 1 , " 24Mhz 1Gbps" + Selection 2 , " 38.4Mhz 2.5Gbps" + Selection 3 , " 38.4Mhz 1Gbps" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_CnviMode + Selection 0 , "Disable" + Selection 1 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_BootFrequency + Selection 0 , "0" + Selection 1 , "1" + Selection 2 , "2" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PpinSupport + Selection 0 , " Disable" + Selection 1 , " Enable" + Selection 2 , " Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_AvxDisable + Selection 0 , " Enable" + Selection 1 , " Disable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcHotDemotion + Selection 0 , " Disable" + Selection 1 , " Hardware Default" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency + Selection 0 , " 6MHz" + Selection 1 , " 12MHz" + Selection 2 , " 24MHz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod + Selection 0 , " HardwareEq" + Selection 1 , " FixedEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode + Selection 0 , " PresetEq" + Selection 1 , " CoefficientEq" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPhBypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPhBypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPhBypass + Selection 0 , "Disable" + Selection 1 , "Enable" + Selection 2 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieCfgDump + Selection 0 , "Disable" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspm + Selection 0 , "Disabled" + Selection 1 , "L0s" + Selection 2 , "L1" + Selection 3 , "L0sL1" + Selection 4 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_IehMode + Selection 0 , " Bypass" + Selection 1 , "Enable" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW + Selection 0 , "x1" + Selection 1 , "x2" + Selection 2 , "x4" + Selection 3 , "x8" + Selection 4 , "x16" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt + Selection 0 , "Msix" + Selection 1 , "Msi" + Selection 2 , "Legacy" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl + Selection 0 , "Disabled" + Selection 1 , "L0s" + Selection 2 , "L1" + Selection 3 , "L0sL1" + Selection 4 , "Auto" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_PcieFomsCp + Selection 0 , " Auto" + Selection 1 , " Gen3 Foms" + Selection 2 , " Gen4 Foms" + Selection 3 , " Gen3 and Gen4 Foms" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax + Selection 0xFF , " Auto(Default)" + Selection 2 , " 100 Mhz" + Selection 3 , " 150 Mhz" + Selection 4 , " 200 Mhz" + Selection 5 , " 250 Mhz" + Selection 6 , " 300 Mhz" + Selection 7 , " 350 Mhz" + Selection 8 , " 400 Mhz" + Selection 9 , " 450 Mhz" + Selection 0xA , " 500 Mhz" + Selection 0xB , " 550 Mhz" + Selection 0xC , " 600 Mhz" + Selection 0xD , " 650 Mhz" + Selection 0xE , " 700 Mhz" + Selection 0xF , " 750 Mhz" + Selection 0x10 , " 800 Mhz" + Selection 0x11 , " 850 Mhz" + Selection 0x12 , "900 Mhz" + Selection 0x13 , " 950 Mhz" + Selection 0x14 , " 1000 Mhz" + Selection 0x15 , " 1050 Mhz" + Selection 0x16 , " 1100 Mhz" + Selection 0x17 , " 1150 Mhz" + Selection 0x18 , " 1200 Mhz" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner + Selection 1 , " HALT loop" + Selection 2 , " MWAIT loop" + Selection 3 , " RUN loop" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme + Selection 0 , " Single Range Output" + Selection 1 , " ToPA Output" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_StepDownMode + Selection 0 , " Gradual Power Reduction" + Selection 1 , " Aggressive Power Reduction" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage + Selection 0 , "Disable" + Selection 1 , "Send in PEI" + Selection 2 , "Send in DXE" + Selection 3 , "Reserved" +EndList + +List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear + Selection 0 , " Disable ME Unconfig On Rtc Clear" + Selection 1 , " Enable ME Unconfig On Rtc Clear" + Selection 2 , " Cmos is clear" + Selection 3 , " Reserved" +EndList + +BeginInfoBlock + PPVer "0.1" + Description "Alder Lake Platform" +EndInfoBlock + +Page "System Agent(PreMem)" + Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS, + Help "0=Disable/Clear, 1=Enable/Set" + Combo $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee, "State of DMA_CONTROL_GUARANTEE bit in the DMAR table", &EN_DIS, + Help "0=Disable/Clear, 1=Enable/Set" + EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX, + Help "Base addresses for VT-d MMIO access per VT-d engine" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS, + Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdIgdEnable, "Vtd Programming for Igd", &EN_DIS, + Help "1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar programming disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_VtdIopEnable, "Vtd Programming for Iop", &EN_DIS, + Help "1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar programming disabled)" + Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, + Help "Size of memory preallocated for internal graphics." + Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS, + Help "Enable/disable internal graphics." + Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS, + Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuSaPllVoltageOffset, "CPU SA PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IaAtomPllVoltageOffset, "IA Atom PLL voltage offset", HEX, + Help "IA Atom PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX, + Help "Core PLL voltage offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie0En, "TCSS Thunderbolt PCIE Root Port 0 Enable", HEX, + Help "Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie1En, "TCSS Thunderbolt PCIE Root Port 1 Enable", HEX, + Help "Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie2En, "TCSS Thunderbolt PCIE Root Port 2 Enable", HEX, + Help "Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssItbtPcie3En, "TCSS Thunderbolt PCIE Root Port 3 Enable", HEX, + Help "Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssXhciEn, "TCSS USB HOST (xHCI) Enable", HEX, + Help "Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssXdciEn, "TCSS USB DEVICE (xDCI) Enable", HEX, + Help "Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssDma0En, "TCSS DMA0 Enable", HEX, + Help "Set TCSS DMA0. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcssDma1En, "TCSS DMA1 Enable", HEX, + Help "Set TCSS DMA1. 0:Disabled 1:Enabled" + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, + Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, + Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, + Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it" + Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS, + Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0" + Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS, + Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType, + Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table." + EditNum $gPlatformFspPkgTokenSpaceGuid_DmaBufferSize, "PMR Size", HEX, + Help "Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PreBootDmaMask, "The policy for VTd driver behavior", HEX, + Help "BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, + Help "Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate T12 Delay to max 500ms" + EditNum $gPlatformFspPkgTokenSpaceGuid_HgSubSystemId, "HgSubSystemId", HEX, + Help "Hybrid Graphics SubSystemId" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LidStatus, "Platform LID Status for LFP Displays.", &gPlatformFspPkgTokenSpaceGuid_LidStatus, + Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen." + Combo $gPlatformFspPkgTokenSpaceGuid_VgaInitControl, "Control VGA Initialition sequence", &gPlatformFspPkgTokenSpaceGuid_VgaInitControl, + Help "Initialise VGA Init, Set BIT0 - 0 (No VGA Support), BIT0 = 1 (VGA Supported) BIT1 = 1 (VGA Exit)" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtPtr, "Graphics Configuration Ptr", HEX, + Help "Points to VBT" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtSize, "Intel Graphics VBT (Video BIOS Table) Size", HEX, + Help "Size of Graphics VBT Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VgaMessage, "VGA Training Message Pointer", HEX, + Help "Points to VGA Message Array" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Test" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRunOnce, "PPR Run Once", &EN_DIS, + Help "When Eanble, PPR will run only once and then is disabled at next training cycle" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRunAtFastboot, "PPR Run During Fastboot", &EN_DIS, + Help "When Eanble, PPR will run during fastboot" +EndPage + +Page "Memory Reference Code" + EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX, + Help "The minimum platform memory size required to pass control into DXE" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, + Help "Length of SPD Data" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAbove4GBMmio, "Enable above 4GB MMIO resource support", &EN_DIS, + Help "DEPRECATED. Enable/disable above 4GB MMIO resource support" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccEcDis, "Ibecc Ec Dis", &EN_DIS, + Help "This option enables or disables the Ibecc Control register Ec Dis field. Default 0 = Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr000, "Memory SPD Pointer Controller 0 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr001, "Memory SPD Pointer Controller 0 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr010, "Memory SPD Pointer Controller 0 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr011, "Memory SPD Pointer Controller 0 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr020, "Memory SPD Pointer Controller 0 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr021, "Memory SPD Pointer Controller 0 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr030, "Memory SPD Pointer Controller 0 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr031, "Memory SPD Pointer Controller 0 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr100, "Memory SPD Pointer Controller 1 Channel 0 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr101, "Memory SPD Pointer Controller 1 Channel 0 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr110, "Memory SPD Pointer Controller 1 Channel 1 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr111, "Memory SPD Pointer Controller 1 Channel 1 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr120, "Memory SPD Pointer Controller 1 Channel 2 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr121, "Memory SPD Pointer Controller 1 Channel 2 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr130, "Memory SPD Pointer Controller 1 Channel 3 Dimm 0", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr131, "Memory SPD Pointer Controller 1 Channel 3 Dimm 1", HEX, + Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX, + Help "Indicates RcompResistor settings: Board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX, + Help "RcompTarget settings: board-dependent" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch0, "Dqs Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch1, "Dqs Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch2, "Dqs Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc0Ch3, "Dqs Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch0, "Dqs Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch1, "Dqs Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch2, "Dqs Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramMc1Ch3, "Dqs Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch0, "Dq Map CPU to DRAM MC 0 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch1, "Dq Map CPU to DRAM MC 0 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch2, "Dq Map CPU to DRAM MC 0 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc0Ch3, "Dq Map CPU to DRAM MC 0 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch0, "Dq Map CPU to DRAM MC 1 CH 0", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch1, "Dq Map CPU to DRAM MC 1 CH 1", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch2, "Dq Map CPU to DRAM MC 1 CH 2", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DqMapCpu2DramMc1Ch3, "Dq Map CPU to DRAM MC 1 CH 3", HEX, + Help "Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS, + Help "Indicates DqPinsInterleaved setting: board-dependent" + Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask, + Help "The SMM Regions AB-SEG and/or H-SEG reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS, + Help "Enables/Disable the MRC fast path thru the MRC" + Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS, + Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC." + Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS, + Help "This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps." + EditNum $gPlatformFspPkgTokenSpaceGuid_RxVrefTempCoeff, "RxVrefTempCoeff", HEX, + Help "Default = 6. Range from 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CaParityPatternRotation, "CaParityPatternRotation", HEX, + Help "Default = 0 (Auto). 1 for High stress pattern rotation, 2 for no rotation." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_WckOffsetWa, "WCK Offset", &EN_DIS, + Help "This option enables the WCK Offset WA for Hynix32 with freq >= 5600." + Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize, + Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX, + Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB" + "Valid range: 0 ~ 0xC00" + Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS, + Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd, + Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss, "MRC Retraining on RTC Power Loss", &gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss, + Help "Specifies whether MRC memory training will occur when RTC power loss is detected. Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory will not be re-trained when RTC power loss is detected. (Typically used on board designs without a dedicated RTC battery)" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, + Help "Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto." + Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SAGV", &gPlatformFspPkgTokenSpaceGuid_SaGv, + Help "System Agent dynamic frequency support." + Combo $gPlatformFspPkgTokenSpaceGuid_SaGvWpMask, "SAGV WP Mask", &gPlatformFspPkgTokenSpaceGuid_SaGvWpMask, + Help "System Agent dynamic frequency workpoints that memory will be training at the enabled frequencies." + Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, + Help "Run Base Memory Test on Warm Boot" + Combo $gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl, "DDR Speed Control", &gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl, + Help "DDR Frequency and Gear control for all SAGV points." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch0, "Controller 0 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch1, "Controller 0 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch2, "Controller 0 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc0Ch3, "Controller 0 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 0 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch0, "Controller 1 Channel 0 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 0" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch1, "Controller 1 Channel 1 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 1" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch2, "Controller 1 Channel 2 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 2" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMc1Ch3, "Controller 1 Channel 3 DIMM Control", &EN_DIS, + Help "Enable / Disable DIMMs on Controller 1 Channel 3" + Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS, + Help "This option enables data scrambling in memory." + Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, + Help "Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5" + Combo $gPlatformFspPkgTokenSpaceGuid_DynamicMemoryBoost, "Dynamic Memory Boost", &EN_DIS, + Help "0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile, and also the profile selected by SpdProfileSelected, to allow automatic switching during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored." + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryFrequency, "Realtime Memory Frequency", &EN_DIS, + Help "0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is XMP Profile 1. If enabled, MRC will train the Default SPD Profile, and also XMP Profile 1, to allow manually triggered switching between frequencies at runtime." + Combo $gPlatformFspPkgTokenSpaceGuid_OCSafeMode, "OC Safe Mode", &EN_DIS, + Help "Bitmap: Ignored unless SpdProfileSelected is an XMP Profile. Bit 0: Use safe tCL, Bit 1: Limit tWR, tRTP, tCCD_L, tCCD_L_WR, tCL to of freq 6400 when programming Dimm MR if DIMM doesn't support new spec." + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRSG, "tRRSG Delta", HEX, + Help "Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDG, "tRRDG Delta", HEX, + Help "Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDR, "tRRDR Delta", HEX, + Help "Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRDD, "tRRDD Delta", HEX, + Help "Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRSG, "tWRSG Delta", HEX, + Help "Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDG, "tWRDG Delta", HEX, + Help "Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDR, "tWRDR Delta", HEX, + Help "Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWRDD, "tWRDD Delta", HEX, + Help "Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWSG, "tWWSG Delta", HEX, + Help "Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDG, "tWWDG Delta", HEX, + Help "Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDR, "tWWDR Delta", HEX, + Help "Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWWDD, "tWWDD Delta", HEX, + Help "Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWSG, "tRWSG Delta", HEX, + Help "Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDG, "tRWDG Delta", HEX, + Help "Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDR, "tRWDR Delta", HEX, + Help "Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRWDD, "tRWDD Delta", HEX, + Help "Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta range of [-127..127]" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI32, "tREFI32", HEX, + Help "Refresh Interval, 0: AUTO, max: 131071. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit3200Mask, "Config BitMask to limit max freq at 3200", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit3600Mask, "Config BitMask to limit max freq at 3600", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit4000Mask, "Config BitMask to limit max freq at 4000", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit4400Mask, "Config BitMask to limit max freq at 4400", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit4800Mask, "Config BitMask to limit max freq at 4800", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit5200Mask, "Config BitMask to limit max freq at 5200", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimit5600Mask, "Config BitMask to limit max freq at 5600", HEX, + Help "BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, BIT12: 2R2R_32GB_48GB" + "Valid range: 0x0 ~ 0x1FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_FreqLimitMaskEn, "2DPC Enhanced Frequency Limit", &EN_DIS, + Help "Enable/Disable Enhanced FreqLimit for 2DPC" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxVrefOverride, "Initial DDR5 TxVref Override", DEC, + Help "Override for initial DDR5 TxVref value , 0 = Auto (default), valid range from 350 to 975, in increments of 5" + "Valid range: 0 ~ 975" + Combo $gPlatformFspPkgTokenSpaceGuid_IsForceCkdBypass, "Force CKD in Bypass Mode", &EN_DIS, + Help "Enable/Disable Force CKD in Bypass Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_Vdd2Mv, "Vdd2Mv", &gPlatformFspPkgTokenSpaceGuid_Vdd2Mv, + Help "VDD2 in MilliVolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. " + Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk, + Help "100MHz, 133MHz." + Combo $gPlatformFspPkgTokenSpaceGuid_SafeLoadingBiosEnableState, "Safe Loading Bios Enable State", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for TSEG Region." + Combo $gPlatformFspPkgTokenSpaceGuid_PprRecoveryStatusEnable, "Ppr Recovery Status Enable", &EN_DIS, + Help "0: Disabled(Default), 1: Enabled. If enabled, PPR Recovery flow will get Trigger." + Combo $gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus, "Tseg Memory Test Status", &gPlatformFspPkgTokenSpaceGuid_TsegMemoryTestStatus, + Help " If enabled, PPR Recovery flow will get Trigger" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcPprStatus, "Mrc Ppr Status", &gPlatformFspPkgTokenSpaceGuid_MrcPprStatus, + Help " Get Mrc PPR Status after PPR Recovery flow will get Trigger" + Combo $gPlatformFspPkgTokenSpaceGuid_RetryCount, "Tseg Retry Count", &gPlatformFspPkgTokenSpaceGuid_RetryCount, + Help "Tseg Retry count will increase based on TSEG Region Fail count" + Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Vdd Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage, + Help "DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc." + EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltage, "Memory VDDQ Voltage", DEC, + Help "DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts from 0 - default to 1435mv." + "Valid range: 0 ~ 1435" + EditNum $gPlatformFspPkgTokenSpaceGuid_VppVoltage, "Memory VPP Voltage", DEC, + Help "DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from 0 - default to 2135mv." + "Valid range: 0 ~ 2135" + Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio, + Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below." + EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX, + Help "CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX, + Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x22" + EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX, + Help "Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX, + Help "RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX, + Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX, + Help "Obsolete, use tREFI32 instead. Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX, + Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX, + Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX, + Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x0F" + Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR, + Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX, + Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0x1C" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFCpb, "tRFCpb", HEX, + Help "Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC2, "tRFC2", HEX, + Help "Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC4, "tRFC4", HEX, + Help "Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX, + Help "Min Internal row active to row active delay time for same bank groups, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX, + Help "Min Internal row active to row active delay time for different bank groups, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX, + Help "Min Internal write to read command delay time for same bank groups, 0: AUTO, max: 127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCCD_L, "tCCD_L", HEX, + Help "Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tCCD_L_WR, "tCCD_L_WR", HEX, + Help "Min Internal Write-to-Write delay for same bank group, 0: AUTO, max: 150. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX, + Help "Min Internal write to read command delay time for different bank groups, 0: AUTO, max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile)." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX, + Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N" + "Valid range: 0x00 ~ 0x02" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvGear, "SAGV Gear Ratio", HEX, + Help "Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaGvFreq, "SAGV Frequency", HEX, + Help "SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GearRatio, "SAGV Disabled Gear Ratio", HEX, + Help "Gear Selection for SAGV Disabled. 0 - Auto, 2-Gear 2, 2-Gear 4" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttWr, "LPDDR ODT RttWr", HEX, + Help "Initial RttWr for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LpddrRttCa, "LPDDR ODT RttCa", HEX, + Help "Initial RttCa for LP4/5 in Ohms. 0x0 - Auto" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DimmOdt, "Dimm Odt settings", HEX, + Help "Dimm Odt settings of 2 DIMMs of a channel: Memory-dependent, 0: AUTO, max: 0xFFFF meaning disabling" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap1, "Dimm DFE Tap1 settings Deprecated", HEX, + Help "Dimm DFE Tap1 settings: Memory-dependent, positive values will be converted to minus values by *-1 automatically" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap2, "Dimm DFE Tap2 settings Deprecated", HEX, + Help "Dimm DFE Tap2 settings: Memory-dependent, positive values will be converted to minus values by *-1 automatically" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CsVrefLow, "CsVrefLow", HEX, + Help "DDR5 Cs Sweep Low Vref Value, 0: AUTO, max: 125." + "Valid range: 0x00 ~ 0xFD" + EditNum $gPlatformFspPkgTokenSpaceGuid_CsVrefHigh, "CsVrefHigh", HEX, + Help "DDR5 Cs Sweep High Vref Value, 0: AUTO, max: 125." + "Valid range: 0x00 ~ 0xFD" + EditNum $gPlatformFspPkgTokenSpaceGuid_CaVrefLow, "CaVrefLow", HEX, + Help "DDR5 Ca Sweep Low Vref Value, 0: AUTO, max: 125." + "Valid range: 0x00 ~ 0xFD" + EditNum $gPlatformFspPkgTokenSpaceGuid_CaVrefHigh, "CaVrefHigh", HEX, + Help "DDR5 Ca Sweep High Vref Value, 0: AUTO, max: 125." + "Valid range: 0x00 ~ 0xFD" + EditNum $gPlatformFspPkgTokenSpaceGuid_RxVrefOffset, "RxVrefOffset", HEX, + Help "DDR5 RxVref Offset Value, 0: AUTO, max: 1600." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX, + Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size" + "Valid range: 0 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, + Help "0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics" + Combo $gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size, "Internal Graphics Data Stolen Memory GSM2", &gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size, + Help "Size of memory preallocated for internal graphics GSM2." + EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX, + Help "Obsolete field now and it has been extended to 64 bit address, used LMemBar " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS, + Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization" + Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS, + Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport" + Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, + Help "0(Default): Adaptive, 1: Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX, + Help "0(Default)=Minimal/Auto, 60=Maximum" + "Valid range: 0x00 ~ 0x3C" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX, + Help "0(Default)=Minimal, 1000=Maximum" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX, + Help "0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtAdaptiveVoltage, "adaptive voltage applied during turbo frequencies", HEX, + Help "0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX, + Help "0(Default)=Minimal, 1000=Maximum" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Hybrid Graphics dGPU", HEX, + Help "Root port Index number to indicate which PCIe root port has dGPU" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, + Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE." + Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS, + Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU" + Combo $gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn, "IMGU CLKOUT Configuration", &EN_DIS, + Help "The configuration of IMGU CLKOUT, 0: Disable;1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, "Program GPIOs for LFP on DDI port-A device", &gPlatformFspPkgTokenSpaceGuid_DdiPortAConfig, + Help "0=Disabled,1(Default)=eDP, 2=MIPI DSI" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, "Program GPIOs for LFP on DDI port-B device", &gPlatformFspPkgTokenSpaceGuid_DdiPortBConfig, + Help "0(Default)=Disabled,1=eDP, 2=MIPI DSI" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortAHpd, "Enable or disable HPD of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Hpd, "Enable or disable HPD of DDI port 1", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Hpd, "Enable or disable HPD of DDI port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Hpd, "Enable or disable HPD of DDI port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Hpd, "Enable or disable HPD of DDI port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortADdc, "Enable or disable DDC of DDI port A", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort1Ddc, "Enable DDC setting of DDI Port 1", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort2Ddc, "Enable DDC setting of DDI Port 2", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort3Ddc, "Enable DDC setting of DDI Port 3", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DdiPort4Ddc, "Enable DDC setting of DDI Port 4", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisplayGpioPinMux, "GPIO PIN MUX to choose between GPP_SA and GPP_SD Group.", HEX, + Help "Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP, 1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3 - DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigureDsmMtrr, "FrameBuffer via DSM or LMem, when FrameBuffer is pointing to DSM region this option should be enabled", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_LMemBar, "Temporary MMIO address for GMADR", HEX, + Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX, + Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1." + "Valid range: 0x00 ~ 0x7F" + Combo $gPlatformFspPkgTokenSpaceGuid_SaVoltageMode, "SA/Uncore voltage mode", &EN_DIS, + Help "SA/Uncore voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOverride, "SA/Uncore Voltage Override", HEX, + Help "The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_SaAdaptiveVoltage, "SA/Uncore Adaptive voltage", HEX, + Help "Adaptive voltage applicable when SA/Uncore voltage mode is in Adaptive mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &EN_DIS, + Help "0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature" + Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &EN_DIS, + Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieResizableBarSupport, "PCIE Resizable BAR Support", &EN_DIS, + Help "Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default)." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4RootPortPreset, "PCH DMI Gen3 Root port preset values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Production" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, + Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh2Enable, "PCH DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh2Enable, + Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh3Method, "PCH DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EqPh3Method, + Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS, + Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3RootPortPreset, "PCH DMI Gen3 Root port preset values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EndPointPreset, "PCH DMI Gen3 End port preset values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3EndPointHint, "PCH DMI Gen3 End port Hint values per lane", HEX, + Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM Configuration:{Combo", HEX, + Help "Set ASPM Configuration" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm, "PCH DMI ASPM Configuration:{Combo", HEX, + Help "Set ASPM Configuration" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiHweq, "Enable/Disable DMI GEN3 Hardware Eq", &EN_DIS, + Help "Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase23Bypass, "Enable/Disable DMI GEN3 Phase 23 Bypass", &EN_DIS, + Help "DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): Enable Phase 23 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3EqPhase3Bypass, "Enable/Disable DMI GEN3 Phase 3 Bypass", &EN_DIS, + Help "DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): Enable Phase 3 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3LtcoEnable, "Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter Coefficient Override" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen3RtcoRtpoEnable, "Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpre, "DMI Gen3 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3Ltcpo, "DMI Gen3 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3LtcoEnable, "Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter Coefficient Override" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3RtcoRtpoEnable, "Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3Ltcpre, "PCH DMI Gen3 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen3Ltcpo, "PCH DMI Gen3 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen3CoeffListCm, "PCIE Hw Eq Gen3 CoeffList Cm", HEX, + Help "DMI_EQ_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen3CoeffListCp, "PCIE Hw Eq Gen3 CoeffList Cp", HEX, + Help "DMI_EQ_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPresetEnable, "Enable/Disable DMI GEN3 DmiGen3DsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, Manual(0x1): Enable DmiGen3DsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortRxPreset, "DMI Gen3 Root port preset Rx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3DsPortTxPreset, "DMI Gen3 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPresetEnable, "Enable/Disable DMI GEN3 DmiGen3UsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, Manual(0x1): Enable DmiGen3UsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortRxPreset, "DMI Gen3 Root port preset Rx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3UsPortTxPreset, "DMI Gen3 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen4CoeffListCm, "DMI Hw Eq Gen4 CoeffList Cm", HEX, + Help "DMI_EQ_PARAM. Coefficient C-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiHwEqGen4CoeffListCp, "DMI Hw Eq Gen4 CoeffList Cp", HEX, + Help "DMI_EQ_PARAM. Coefficient C+1." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase23Bypass, "Enable/Disable DMI GEN4 Phase 23 Bypass", &EN_DIS, + Help "DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): Enable Phase 23 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4EqPhase3Bypass, "Enable/Disable DMI GEN4 Phase 3 Bypass", &EN_DIS, + Help "DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): Enable Phase 3 Bypass" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPresetEnable, "Enable/Disable DMI GEN4 DmiGen4DsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable, Manual(0x1): Enable DmiGen4DsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4DsPortTxPreset, "DMI Gen4 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4RtcoRtpoEnable, "Enable/Disable DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + Combo $gPlatformFspPkgTokenSpaceGuid_Gen4LtcoEnable, "Enable/Disable DMI Gen4 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter Coefficient Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpre, "DMI Gen4 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, 0 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4Ltcpo, "DMI Gen4 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPresetEnable, "Enable/Disable DMI GEN4 DmiGen4UsPresetEnable", &EN_DIS, + Help "Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable, Manual(0x1): Enable DmiGen4UsPresetEnable" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen4UsPortTxPreset, "DMI Gen4 Root port preset Tx values per lane", HEX, + Help "Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DmiAspmL1ExitLatency, "DMI ASPM L1 exit Latency", HEX, + Help "Range: 0-7, 4 is default L1 exit Latency" + "Valid range: 0x00 ~ 0x07" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4RtcoRtpoEnable, "Enable/Disable PCH DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable", &EN_DIS, + Help "Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote Transmitter Coefficient/Preset Override" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4LtcoEnable, "Enable/Disable PCH DMI Gen4 EQ Local Transmitter Coefficient Override Enable", &EN_DIS, + Help "Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter Coefficient Override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4Ltcpo, "PCH DMI Gen4 Transmitter Post-Cursor Coefficient", HEX, + Help "Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmL1ExitLatency, "PCH DMI ASPM L1 exit Latency", HEX, + Help "Range: 0-7, 4 is default L1 exit Latency" + "Valid range: 0x00 ~ 0x07" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiGen4Ltcpre, "PCH DMI Gen4 Transmitter Pre-Cursor Coefficient ", HEX, + Help "Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, 0 is default for each lane" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiL1ssEnable, "L1SS State Control Policy", &gPlatformFspPkgTokenSpaceGuid_DmiL1ssEnable, + Help "Choose the L1SS State Control Policy, Default = 0 " + EditNum $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioBase, "Temporary address for NvmeHcPeiMmioBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NvmeHcPeiMmioLimit, "Temporary address for NvmeHcPeiMmioLimit", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioBase, "Temporary address for AhciPeiMmioBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AhciPeiMmioLimit, "Temporary address for AhciPeiMmioLimit", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcExtraIoBase, "Temporary address for EcExtraIoBase", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SioBaseAddress, "Temporary address for SioBaseAddress", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ApicLocalAddress, "Temporary address for ApicLocalAddress", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBar, "Temporary CfgBar address for VMD", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Bar, "Temporary MemBar1 address for VMD", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Bar, "Temporary MemBar2 address for VMD", HEX, + Help "The reference code will use this as Temporary address space" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, + Help "Margin Limit Check. Choose level of margin check" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomClusterRatio, "Atom Cluster Max Ratio", HEX, + Help "Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their max core ratio will be aligned." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CoreRatioExtensionMode, "Core Ratio Extension Mode", &EN_DIS, + Help "Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PvdRatioThreshold, "Pvd Ratio Threshold for SOC/CPU die", HEX, + Help "Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. As per the die selected, this threshold is applied to SA and MC/CMI PLL for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default." + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PvdMode, "Pvd Mode SOC/CPU die", HEX, + Help "Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)." + "Valid range: 0x0 ~ 0x3" + EditNum $gPlatformFspPkgTokenSpaceGuid_FllOverclockMode, "FLL Overclock Mode", HEX, + Help "Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63." + "Valid range: 0x0 ~ 0x3" + Combo $gPlatformFspPkgTokenSpaceGuid_ActiveSocNorthAtomCoreCount, "Number of Soc-North Atom cores", &gPlatformFspPkgTokenSpaceGuid_ActiveSocNorthAtomCoreCount, + Help "Number of SOC-North E-cores to enable in SOC North. 0: Disable all Soc-North Atom cores; 1: 1; 2: 2; 0xFF: Active all Soc-North Atom cores" + Combo $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode, "Ring VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetMode, + Help "Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffset, "Ring VF Point Offset", HEX, + Help "Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointOffsetPrefix, "Ring VF Point Offset Prefix", HEX, + Help "Sets the RingVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointRatio, "Ring VF Point Ratio", HEX, + Help "Array for the each selected Ring VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingVfPointCount, "Ring VF Point Count", HEX, + Help "Number of supported Ring Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ComputeDieSscEnable, "Compute Die SSC enable", &EN_DIS, + Help "Enable/Dsiable Compute-Die SSC Configuration. 0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SocDieSscEnable, "Soc Die SSC enable", &EN_DIS, + Help "Enable/Dsiable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioOverride, "GPIO Override", HEX, + Help "Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use" + "Valid range: 0x00 ~ 0x7" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBclkOcFrequency, "CPU BCLK OC Frequency", HEX, + Help "CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SocBclkOcFrequency, "SOC BCLK OC Frequency", HEX, + Help "SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is 40Mhz-1000Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, "Enable CPU CrashLog GPRs dump", &gPlatformFspPkgTokenSpaceGuid_CrashLogGprs, + Help "Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only disable Smm GPRs dump" + EditNum $gPlatformFspPkgTokenSpaceGuid_DisablePerCoreMask, "Bitmask of disable cores", HEX, + Help "Core mask is a bitwise indication of which core should be disabled. 0x00=Default; Bit 0 - core 0, bit 7 - core 7." + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IaIccUnlimitedMode, "Support IA Unlimited ICCMAX", &EN_DIS, + Help "Support IA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_IaIccMax, "IA ICCMAX", HEX, + Help "IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 (HW default). Range is 4-2047." + "Valid range: 0x00 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_GtIccUnlimitedMode, "Support GT Unlimited ICCMAX", &EN_DIS, + Help "Support GT Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_GtIccMax, "GT ICCMAX", HEX, + Help "GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 (HW default). Range is 4-2047." + "Valid range: 0x00 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaIccUnlimitedMode, "Support SA Unlimited ICCMAX", &EN_DIS, + Help "Support SA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_SaIccMax, "SA ICCMAX", HEX, + Help "SA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 (HW default). Range is 4-2047." + "Valid range: 0x00 ~ 0x7FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffset, "Memory Subsystem VF Point Offset", HEX, + Help "Array used to specifies the Memory Subsystem Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetPrefix, "Memory Subsystem VF Point Offset Prefix", HEX, + Help "Sets the MemSSVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointRatio, "Memory Subsystem VF Point Ratio", HEX, + Help "Array for the each selected Memory Subsystem VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointCount, "Memory Subsystem VF Point Count", HEX, + Help "Number of supported Memory Subsystem Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_VccsaBootVoltageSel, "VCCSA Boot Voltage", &gPlatformFspPkgTokenSpaceGuid_VccsaBootVoltageSel, + Help " Default: 0: Nominal 1: High Voltage(up to 1.2/1.3V) to support the voltage needed for VCCSA boot voltage." + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuD2dRatio, "CPU D2D ratio setting", HEX, + Help "0(Default)=No setting, 15=Minimal, 40=Maximum" + "Valid range: 0x0F ~ 0x28" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuBandgapRefMode, "CPU Bandgap Reference Mode", &gPlatformFspPkgTokenSpaceGuid_CpuBandgapRefMode, + Help " Default: 0: Normal 1: Bandgap Bypassed) to support CPU Bandgap Reference Mode." + Combo $gPlatformFspPkgTokenSpaceGuid_VcciaBootVoltageSel, "VCCIA Boot Voltage", &gPlatformFspPkgTokenSpaceGuid_VcciaBootVoltageSel, + Help " Default: 0: Nominal 1: High Voltage to support the voltage higher than 1.65v (max 2.01v))" + Combo $gPlatformFspPkgTokenSpaceGuid_GranularRatioOverride, "Granular Ratio Override", &EN_DIS, + Help "Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreGranularityBins, "Granularity Bins Override for Core", HEX, + Help "Array used to specifies the selected Core Granularity Bins." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterGranularityBins, "Granularity Bins Override for AtomCluster", HEX, + Help "Array used to specifies the selected AtomCluster Granularity Bins." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride, "Sa PLL Frequency", &gPlatformFspPkgTokenSpaceGuid_SaPllFreqOverride, + Help "Configure Sa PLL Frequency. 0: 2400MHz , 1: 1600MHz" + Combo $gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup, "TSC HW Fixup disable", &gPlatformFspPkgTokenSpaceGuid_TscDisableHwFixup, + Help "TSC HW Fixup disable during TSC copy from PMA to APIC. 0: Enable; 1: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit, "Process Vmax Limit", &gPlatformFspPkgTokenSpaceGuid_ProcessVmaxLimit, + Help "Setting this bit will allow user to set any voltage. Note: Disabling the voltage limit checks may cause permanent damage to processor. 1: Enable; 0: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle, "P-Core Power Density Throttle", &gPlatformFspPkgTokenSpaceGuid_PcorePowerDensityThrottle, + Help "This control allow user to disable P-core Power Density Throttling for overclocking. 1: Enable; 0: Disable" + EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMinRatio, "Request Core Min Ratio", HEX, + Help "0(Default)=No Request" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPreMem, "ReservedCpuPreMem", &EN_DIS, + Help "Reserved for Cpu Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS, + Help "Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state. 0: Disabled; 1: Enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX, + Help "PSYS Slope defined in 1/100 increments. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25" + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX, + Help "PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W" + "Valid range: 0x00 ~ 0x400" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcCurrentLimit, "Thermal Design Current current limit", HEX, + Help "TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x7FFF7FFF7FFF7FFF7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX, + Help "AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x7FFF7FFF7FFF7FFF7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX, + Help "DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x18691869186918691869" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX, + Help "PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX, + Help "PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX, + Help "PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x02000200020002000200" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX, + Help "PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX, + Help "PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX, + Help "IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x00C800C800C800C800C8" + EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX, + Help "IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset of 25.348, enter 25348. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX, + Help "VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX, + Help "Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "Thermal Design Current time window", HEX, + Help "TDC Time Window, value in seconds. Range from 1s to 448s, 0 = Auto/HW default. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x0006D6000006D6000006D6000006D6000006D600" + EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX, + Help "Thermal Design Current Lock; 0: Disable; 1: Enable. For all VR Indexes" + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DlvrRfiFrequency, "DLVR RFI Frequency", HEX, + Help "DLVR RFI Frequency in MHz. 0x055A: 1370 MHz." + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DlvrSpreadSpectrumPercentage, "DLVR RFI Spread Spectrum Percentage", HEX, + Help "DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 31 = 7.75%. 0x06: 1.5%; u3.2 value from 0% - 7.75%." + "Valid range: 0x0 ~ 0x1F" + Combo $gPlatformFspPkgTokenSpaceGuid_DlvrRfiEnable, "DLVR RFI Enable", &EN_DIS, + Help "Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX, + Help "Set the maximum Pre Wake randomization time in micro ticks. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX, + Help "Set the maximum Ramp Up randomization time in micro ticks. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX, + Help "Set the maximum Ramp Down randomization time in micro ticks. This is for acoustic noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "Available power delivery segments", HEX, + Help "This field is required to be non-zero on Desktop platforms. Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. 0: Disable.." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX, + Help "Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed at any given time. Range is 0 - 7999mV. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x1F3F1F3F1F3F1F3F1F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS1toPS0DynamicCutoffEnable, "Enable/Disable PS1 to PS0 Dynamic Cutoff", HEX, + Help "PS1 to PS0 Dynamic Cutoff Enable/Disable. 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS1toPS0MCoef, "PS1 to PS0 Dynamic Cutoff M Coef", HEX, + Help "PS1 to PS0 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter 1250. Range: 0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x10001000100010001000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS1toPS0CCoef, "PS1 to PS0 Dynamic Cutoff C Coef", HEX, + Help "PS1 to PS0 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter 1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846, range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x10001000100010001000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS2toPS1DynamicCutoffEnable, "Enable/Disable PS2 to PS1 Dynamic Cutoff", HEX, + Help "PS2 to PS1 Dynamic Cutoff Enable/Disable. 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS2toPS1MCoef, "PS2 to PS1 Dynamic Cutoff M Coef", HEX, + Help "PS2 to PS1 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter 1250, range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x10001000100010001000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PS2toPS1CCoef, "PS2 to PS1 Dynamic Cutoff C Coef", HEX, + Help "PS2 to PS1 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter 1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846, range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x10001000100010001000" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInDemotionEnable, "VCCIN Demotion", HEX, + Help "DEPRECATED. En/Dis VCCIN Demotion. 0: Disable, 1: Enable with default threshold, 2: Enable with user configured threshold. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInDemotionQuiescentPowerInMw, "VCCIN Demotion Quiescent Power in mW", HEX, + Help "DEPRECATED. User configured platform quiescent threshold in milli-watt when VCC Demotion is enabled. Range is 0-255mW. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccInDemotionCapacitanceInUf, "VCCIN Demotion Capacitance in uF", HEX, + Help "DEPRECATED. User configured VR's quiescent power threshold in micro-farad when VCC Demotion is enabled. Range: 0-2000uF. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x000007D0000007D0000007D0000007D0000007D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX, + Help "PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset of 25.348, enter 25348." + "Valid range: 0x0000 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisable, "Disable Fast Slew Rate for Deep Package C States for VR domains", &EN_DIS, + Help "This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. 0: False; 1: True" + Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, "Slew Rate configuration for Deep Package C States for VR domains", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRate, + Help "Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX, + Help "Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x07FF07FF03FFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FastVmodeOffset, "VR Fast Vmode Offset", HEX, + Help "Voltage Regulator Fast Vmode Offset. This value represents the ICC Max Offset(dV/dT) to be configured if Fast Vmode is enabled. The value is represented in 1 mV increments. 0 = Use processor default setting. Highly recommend to keep at the default setting. IA, GT and SA, range 0-255. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SvidStabilizationDelay, "SVID Stabiliation Delay", HEX, + Help "Configure SVID Stabiliation Delay being used for the FVM feature when it is enabled. Note that this delay applies to all SVID domains equally (no unique values possible for IA/GT/SA).The value is represented in 1 us increments. IA, GT and SA, range 0-255." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccDemotionShutdownThreshold, "VCC Demotion Shutdown Threshold in msec", HEX, + Help "User configured time threshold in msec. Range is 0-255 msec. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IccLimit, "VR Fast Vmode ICC Limit support", HEX, + Help "Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds to feature disabled (no reactive protection). This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0x07F807F807F807F807F8" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, "Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.", &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode, + Help "Enable/Disable VR FastVmode; 0: Disable; 1: Enable. For all VR by domain" + Combo $gPlatformFspPkgTokenSpaceGuid_CepEnable, "Enable CEP", &EN_DIS, + Help "Enable/Disable CEP (Current Excursion Protection) Support. 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + Combo $gPlatformFspPkgTokenSpaceGuid_SirpEnable, "Enable SIRP", &EN_DIS, + Help "Enable/Disable SIRP (SoC Iccmax Reactive Protection) Support. 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + EditNum $gPlatformFspPkgTokenSpaceGuid_Irms, "Enable IRMS", HEX, + Help "Enable/Disable IRMS for VR domains - Current root mean square. 0: Disable; 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UnderVoltProtection, "UnderVolt Protection", &EN_DIS, + Help "When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime. 0: Disabled; 1: Enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_EnableVsysCritical, "Vsys Critical", HEX, + Help "PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysFullScale, "Vsys Full Scale", DEC, + Help "Vsys Full Scale, Range is 0-255000mV" + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysCriticalThreshold, "Vsys Critical Threshold", DEC, + Help "Vsys Critical Threshold, Range is 0-255000mV " + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysFullScale, "Psys Full Scale", DEC, + Help "Vsys Full Scale, Range is 0-255000mV" + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysCriticalThreshold, "Psys Critical Threshold", DEC, + Help "Vsys Critical Threshold, Range is 0-255000mV " + "Valid range: 0 ~ 255000" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchMantissa, "Assertion Deglitch Mantissa", HEX, + Help "Assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysAssertionDeglitchExponent, "Assertion Deglitch Exponent", HEX, + Help "Assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchMantissa, "De assertion Deglitch Mantissa", HEX, + Help "De assertion Deglitch Mantissa, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VsysDeassertionDeglitchExponent, "De assertion Deglitch Exponent", HEX, + Help "De assertion Deglitch Exponent, Range is 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreMaxRatio, "Per Core Max OC Ratio", HEX, + Help "Array for the Per Core Max OC Ratio" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerAtomClusterMaxRatio, "Per Atom Cluster Max OC Ratio", HEX, + Help "Array for the Per Atom Cluster Max OC Ratio" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimit, "OC Max Voltage limits", HEX, + Help "OC Max Voltage limits" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllCurrentRefTuningOffset, "Core PLL Current Reference Tuning Offset", HEX, + Help "Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset, "Ring PLL Current Reference Tuning Offset", HEX, + Help "DEPRECATED. Ring PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset, "IaAtom PLL Current Reference Tuning Offset", HEX, + Help "IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreDisableConfiguration, "Per Core Disable Configuration", HEX, + Help "This configuration can be used only when OC is enabled,user can either use legacy num of cores option or the OC specific per core disable configuration. 0: Disable, 1: Enable" + "Valid range: 0x0 ~ 0x1" + EditNum $gPlatformFspPkgTokenSpaceGuid_NpuMaxOcRatio, "Maximum Npu turbo ratio override", HEX, + Help "DEPRECATED. Maximum Npu turbo ratio override allows to increase NPU frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-120" + "Valid range: 0x00 ~ 0x55" + Combo $gPlatformFspPkgTokenSpaceGuid_NpuVoltageMode, "NPU voltage mode", &EN_DIS, + Help "DEPRECATED. NPU voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOverride, "NPU voltage override", HEX, + Help "DEPRECATED. The NPU voltage override which is applied to the entire range of cpu NPU frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_NpuAdaptiveVoltage, "adaptive voltage applied during turbo frequencies", HEX, + Help "DEPRECATED. 0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOffset, "NPU Turbo voltage Offset", HEX, + Help "DEPRECATED. The voltage offset applied to the NPU while operating in turbo mode. Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimitNew, "OC Max Voltage limits", HEX, + Help "DEPRECATED. OC Max Voltage limits" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ForcePcoreResidency, "Force Pcore Residency", &EN_DIS, + Help "Enable/Disable Force Pcore Residency. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_VrLimitBypass, "VR Limit Bypass", &EN_DIS, + Help "Enable/Disable VR Limit Bypass. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection, "Turbo Thermal Protection", &gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection, + Help "This control allow user to disable Turbo Thermal Protection (TTP) for overclocking. 1: Enable; 0: Disable" + Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS, + Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS, + Help "Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX, + Help "Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX, + Help "IsTPMPresence default values" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS, + Help "Reserved for Security Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize, + Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)." + Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS, + Help "Enables/Disable Early Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS, + Help "Enables/Disable SenseAmp Offset Training" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Early ReadMPR Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS, + Help "Enables/Disable Read MPR Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS, + Help "Enables/Disable Receive Enable Training" + Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS, + Help "Enables/Disable Jedec Write Leveling" + Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Write Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS, + Help "Enables/Disable Early Read Time Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_UNMATCHEDWRTC1D, "Unmatched Write Time Centering 1D", &EN_DIS, + Help "Enable/Disable {Unmatched Write Time Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC1D, "Read Voltage Centering 1D", &EN_DIS, + Help "Enable/Disable Read Voltage Centering 1D" + Combo $gPlatformFspPkgTokenSpaceGuid_DDR5ODTTIMING, "DDR5 ODT Timing Config", &EN_DIS, + Help "Enable/Disable DDR5 ODT TIMING CONFIG" + Combo $gPlatformFspPkgTokenSpaceGuid_VIEWPINCAL, "View Pin Calibration", &EN_DIS, + Help "Enables/Disable View Pin Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_RDDQSODTT, "Read DQS ODT Training", &EN_DIS, + Help "Enables/Disable Read DQS ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDDQODTT, "Read DQ ODT Training", &EN_DIS, + Help "Enables/Disable Read DQ ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS, + Help "Enables/Disable Read Equalization Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RDCTLET, "Read CTLE Training", &EN_DIS, + Help "Enables/Disable Read CTLE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_PPR, "Hard Post Package Repair", &EN_DIS, + Help "Enables/Disable Hard Post Package Repair" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Write Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS, + Help "Enables/Disable Read Timing Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Write Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS, + Help "Enables/Disable Read Voltage Centering 2D" + Combo $gPlatformFspPkgTokenSpaceGuid_RXVREFPERBIT, "RxVref Per-Bit Training", &EN_DIS, + Help "Enable/Disable RxVref Per-Bit Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS, + Help "Enables/Disable Command Voltage Centering" + Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS, + Help "Enables/Disable Late Command Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS, + Help "Enables/Disable Turn Around Timing Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS, + Help "Enable/disable Rank Margin Tool" + Combo $gPlatformFspPkgTokenSpaceGuid_LVRAUTOTRIM, "LVR Auto Trim", &EN_DIS, + Help "Enable/disable LVR Auto Trim" + Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS, + Help "Enables/Disable DIMM SPD Alias Test" + Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS, + Help "Enables/Disable Retrain Margin Check" + Combo $gPlatformFspPkgTokenSpaceGuid_ROWHAMMER, "Row Hammering Prevention", &EN_DIS, + Help "Enables/Disable Row Hammering Prevention" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS, + Help "Enables/Disable Dimm ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS, + Help "Enables/Disable DIMM RON Training" + Combo $gPlatformFspPkgTokenSpaceGuid_TXTCO, "TxDqTCO Comp Training", &EN_DIS, + Help "Enable/Disable TxDqTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CLKTCO, "ClkTCO Comp Training", &EN_DIS, + Help "Enable/Disable ClkTCO Comp Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS, + Help "Enable/Disable CMD Slew Rate Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDDS, "CMD Drive Strength", &EN_DIS, + Help "Enable/Disable CMD Drive Strength" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDTXEQ, "CMD Tx Equalization", &EN_DIS, + Help "Enable/Disable CMD Tx Equalization" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTCA, "DIMM CA ODT Training", &EN_DIS, + Help "Enable/Disable DIMM CA ODT Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTRETRAIN, "Write DQ/DQS Retraining", &EN_DIS, + Help "Enable/Disable Write DQ/DQS Retraining" + Combo $gPlatformFspPkgTokenSpaceGuid_PWRMETER, "Power Saving Meter Update", &EN_DIS, + Help "Enable/Disable Power Saving Meter Update" + Combo $gPlatformFspPkgTokenSpaceGuid_DDRPRECOMP, "Pre-Training Comp Calibration", &EN_DIS, + Help "Enable/Disable Pre-Training Comp Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_RDVREFDC, "Read Vref Decap Training", &EN_DIS, + Help "Enable/Disable Read Vref Decap Training" + Combo $gPlatformFspPkgTokenSpaceGuid_VDDQT, "Vddq Training", &EN_DIS, + Help "Enable/Disable Vddq Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RMTBIT, "Rank Margin Tool Per Bit", &EN_DIS, + Help "Enable/Disable Rank Margin Tool Per Bit" + Combo $gPlatformFspPkgTokenSpaceGuid_DQDQSSWZ, "DQ/DQS Swizzle Training", &EN_DIS, + Help "Enable/Disable DQ/DQS Swizzle Training" + Combo $gPlatformFspPkgTokenSpaceGuid_REFPI, "Ref PI Calibration", &EN_DIS, + Help "Enable/Disable Ref PI Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_RXSALCAL, "Rx SAL Calibration", &gPlatformFspPkgTokenSpaceGuid_RXSALCAL, + Help "Enable/Disable Rx SAL Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_VCCCLKFF, "VccClk FF Offset Correction", &gPlatformFspPkgTokenSpaceGuid_VCCCLKFF, + Help "Enable/Disable VccClk FF Offset Correction" + Combo $gPlatformFspPkgTokenSpaceGuid_DCC, "Duty Cycle Correction Training", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction Training" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCDOWNSTREAM, "Duty Cycle Correction Downstream Training", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction Downstream - PI Serializer/LUT" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCQCLK, "Duty Cycle Correction QCLK Calibration", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction QCLK Calbration" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCRISEFALL, "Duty Cycle Correction Rise/Fall Training", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction Rise/Fall Training" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS, "Functional Duty Cycle Correction for DDR5 DQS", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQS, + Help "Enable/Disable Functional Duty Cycle Correction for DDR5 DQS" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK, "Functional Duty Cycle Correction for DDR5 CLK", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCCLK, + Help "Enable/Disable Functional Duty Cycle Correction for DDR5 CLK" + Combo $gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ, "Functional Duty Cycle Correction for Data DQ", &gPlatformFspPkgTokenSpaceGuid_FUNCDCCDQ, + Help "Enable/Disable Functional Duty Cycle Correction for Data DQ" + Combo $gPlatformFspPkgTokenSpaceGuid_DATAPILIN, "Data PI Linearity Calibration", &EN_DIS, + Help "Enable/Disable {ata PI Linearity Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_DDR5XTALK, "Ddr5 Rx Cross-Talk Cancellation", &EN_DIS, + Help "Enable/Disable Ddr5 Rx Cross-Talk Cancellation" + Combo $gPlatformFspPkgTokenSpaceGuid_DCCLP5WCKDCA, "Duty Cycle Correction for LP5 DCA", &EN_DIS, + Help "Enable/Disable Duty Cycle Correction for LP5 DCA" + Combo $gPlatformFspPkgTokenSpaceGuid_RXUNMATCHEDCAL, "Unmatched Rx Calibration", &EN_DIS, + Help "Enable/Disable Rx Unmatched Calibration" + Combo $gPlatformFspPkgTokenSpaceGuid_TXRK2RK, "Write Rank-to-Rank Training", &EN_DIS, + Help "Enable/Disable Write Rank-to-Rank Training" + Combo $gPlatformFspPkgTokenSpaceGuid_RXRK2RK, "Read Rank-to-Rank Training", &EN_DIS, + Help "Enable/Disable Read Rank-to-Rank Training" + Combo $gPlatformFspPkgTokenSpaceGuid_OPTIMIZECOMP, "Compensation Optimization", &EN_DIS, + Help "Enable/Disable Compensation Optimization" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTDIMMDFE, "DIMM DFE Training", &EN_DIS, + Help "Enable/Disable DIMM DFE Training" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTDS, "Write Drive Strength", &EN_DIS, + Help "Enables/Disable Write Drive Strength" + Combo $gPlatformFspPkgTokenSpaceGuid_WRTEQ, "Write Equalization", &EN_DIS, + Help "Enables/Disable Write Equalization" + Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS, + Help "Enables/Disable ECC Support" + Combo $gPlatformFspPkgTokenSpaceGuid_Ibecc, "Ibecc", &EN_DIS, + Help "In-Band ECC Support" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccParity, "IbeccParity", &EN_DIS, + Help "In-Band ECC Parity Control" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, "IbeccOperationMode", &gPlatformFspPkgTokenSpaceGuid_IbeccOperationMode, + Help "In-Band ECC Operation Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionEnable, "IbeccProtectedRegionEnable", &EN_DIS, + Help "In-Band ECC Protected Region Enable " + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionBase, "IbeccProtectedRegionBases", HEX, + Help "IBECC Protected Region Bases per IBECC instance" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionMask, "IbeccProtectedRegionMasks", HEX, + Help "IBECC Protected Region Masks" + "Valid range: 0x00 ~ 0x3FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionOverallBase, "IbeccProtectedRegionOverallBases", HEX, + Help "IBECC Protected Region Bases based on enabled IBECC instance" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS, + Help "Enables/Disable Memory Remap" + Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS, + Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time." + Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS, + Help "Enables/Disable Enhanced Interleave support" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS, + Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS, + Help "Enables/Disable Extern Therm Status" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter", &EN_DIS, + Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS, + Help "Enables/Disable SelfRefresh Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)" + Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS, + Help "Enables/Disable Throttler CKEMin Defeature" + Combo $gPlatformFspPkgTokenSpaceGuid_RhSelect, "Row Hammer Select", &gPlatformFspPkgTokenSpaceGuid_RhSelect, + Help "Row Hammer Select" + Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS, + Help "Enables/Disable Exit On Failure (MRC)" + Combo $gPlatformFspPkgTokenSpaceGuid_DccSingleRankTrack, "DCC Single Rank Tracking", &EN_DIS, + Help "Force DCC to track single rank only" + Combo $gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported, "DDR5 supports MR7 WICA 0.5 tCK offset", &gPlatformFspPkgTokenSpaceGuid_IsDdr5MR7WicaSupported, + Help "DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset, 0:False, 1:True" + Combo $gPlatformFspPkgTokenSpaceGuid_Write0, "Write0 feature", &EN_DIS, + Help "Enables/Disable Write0 feature" + Combo $gPlatformFspPkgTokenSpaceGuid_DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, + Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP" + Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS, + Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP" + Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, + Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX, + Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC" + "Valid range: 0x0000 ~ 0x3FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency, + Help "Base reference clock value, in Hertz(Default is 125Hz)" + EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX, + Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX, + Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11" + "Valid range: 0x00 ~ 0x7D0" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS, + Help "Enable/Disable CMD Normalization" + Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS, + Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm0, "Idle Energy Mc0Ch0Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch0Dimm1, "Idle Energy Mc0Ch0Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm0, "Idle Energy Mc0Ch1Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc0Ch1Dimm1, "Idle Energy Mc0Ch1Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm0, "Idle Energy Mc1Ch0Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch0Dimm1, "Idle Energy Mc1Ch0Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm0, "Idle Energy Mc1Ch1Dimm0", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyMc1Ch1Dimm1, "Idle Energy Mc1Ch1Dimm1", HEX, + Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm0, "PowerDown Energy Mc0Ch0Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch0Dimm1, "PowerDown Energy Mc0Ch0Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm0, "PowerDown Energy Mc0Ch1Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc0Ch1Dimm1, "PowerDown Energy Mc0Ch1Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm0, "PowerDown Energy Mc1Ch0Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch0Dimm1, "PowerDown Energy Mc1Ch0Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm0, "PowerDown Energy Mc1Ch1Dimm0", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyMc1Ch1Dimm1, "PowerDown Energy Mc1Ch1Dimm1", HEX, + Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)" + "Valid range: 0x0 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm0, "Activate Energy Mc0Ch0Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch0Dimm1, "Activate Energy Mc0Ch0Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm0, "Activate Energy Mc0Ch1Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc0Ch1Dimm1, "Activate Energy Mc0Ch1Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm0, "Activate Energy Mc1Ch0Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch0Dimm1, "Activate Energy Mc1Ch0Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm0, "Activate Energy Mc1Ch1Dimm0", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyMc1Ch1Dimm1, "Activate Energy Mc1Ch1Dimm1", HEX, + Help "Activate Energy Contribution, range[255;0],(172= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm0, "Read Energy Mc0Ch0Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch0Dimm1, "Read Energy Mc0Ch0Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm0, "Read Energy Mc0Ch1Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc0Ch1Dimm1, "Read Energy Mc0Ch1Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm0, "Read Energy Mc1Ch0Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch0Dimm1, "Read Energy Mc1Ch0Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm0, "Read Energy Mc1Ch1Dimm0", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyMc1Ch1Dimm1, "Read Energy Mc1Ch1Dimm1", HEX, + Help "Read Energy Contribution, range[255;0],(212= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm0, "Write Energy Mc0Ch0Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch0Dimm1, "Write Energy Mc0Ch0Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm0, "Write Energy Mc0Ch1Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc0Ch1Dimm1, "Write Energy Mc0Ch1Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm0, "Write Energy Mc1Ch0Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch0Dimm1, "Write Energy Mc1Ch0Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm0, "Write Energy Mc1Ch1Dimm0", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyMc1Ch1Dimm1, "Write Energy Mc1Ch1Dimm1", HEX, + Help "Write Energy Contribution, range[255;0],(221= Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX, + Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_AllowOppRefBelowWriteThrehold, "Allow Opp Ref Below Write Threhold", &EN_DIS, + Help "Allow opportunistic refreshes while we don't exit power down." + EditNum $gPlatformFspPkgTokenSpaceGuid_WriteThreshold, "Write Threshold", HEX, + Help "Number of writes that can be accumulated while CKE is low before CKE is asserted." + "Valid range: 0x00 ~ 0x3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX, + Help "Power budget ,range[255;0],(0= 5.3W Def)" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX, + Help "Power budget ,range[255;0],(0= 5.3W Def)" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate, + Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs" + Combo $gPlatformFspPkgTokenSpaceGuid_McRefreshRate, "MC_REFRESH_RATE", &gPlatformFspPkgTokenSpaceGuid_McRefreshRate, + Help "Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS, + Help "Enable/disable Energy Performance Gain. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr0Mask, "RH pTRR LFSR0 Mask", HEX, + Help "Row Hammer pTRR LFSR0 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" + Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS, + Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS, + Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used." + Combo $gPlatformFspPkgTokenSpaceGuid_OpportunisticSref, "Opportunistic Self Refresh", &gPlatformFspPkgTokenSpaceGuid_OpportunisticSref, + Help "Enable\Disable Opportunistic Self Refresh." + Combo $gPlatformFspPkgTokenSpaceGuid_PowerDownMode, "Power Down Mode", &gPlatformFspPkgTokenSpaceGuid_PowerDownMode, + Help "This option controls command bus tristating during idle periods" + EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX, + Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, "Page Close Idle Timeout", &gPlatformFspPkgTokenSpaceGuid_DisPgCloseIdleTimeout, + Help "This option controls Page Close Idle Timeout" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX, + Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, + Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + EditNum $gPlatformFspPkgTokenSpaceGuid_SafeModeOverride, "MRC Safe Mode Override", HEX, + Help "SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] Enable SaGv safe mode override" + "Valid range: 0x00 ~ 0x7" + EditNum $gPlatformFspPkgTokenSpaceGuid_MrcSafeMode, "MRC Safe Mode Support", HEX, + Help "MrcSafeMode[0]: Safe Frequency, MrcSafeMode[1]: Safe Gear, SafeMode[2]: Safe VCC IOG/CLK, SafeMode[3]: Safe VCC DDQ" + "Valid range: 0x00 ~ 0xF" + Combo $gPlatformFspPkgTokenSpaceGuid_RetrainToWorkingChannel, "Retrain On Working Channel", &EN_DIS, + Help "Enables/Disable Retrain On Working Channel feature" + EditNum $gPlatformFspPkgTokenSpaceGuid_DdrSafeMode, "DDR Phy Safe Mode Support", HEX, + Help "DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: PLL Operation, DdrSafeMode[6]: Safe ODT/SenseAmp Timing, DdrSafeMode[7]: Vtt Termination, DdrSafeMode[8]: Periodic Comp" + "Valid range: 0x00 ~ 0x1FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_McSafeMode, "Mc Safe Mode Support", HEX, + Help "McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate, McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]: Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5 Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]: Power Saving" + "Valid range: 0x00 ~ 0x7FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BoardStackUp, "Board Stack Up", HEX, + Help "0: Typical, 1: Frequency Limited" + "Valid range: 0x00 ~ 0x0" + Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS, + Help "Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory." + EditNum $gPlatformFspPkgTokenSpaceGuid_UsbTcPortEnPreMem, "TCSS USB Port Enable", HEX, + Help "Bitmap for per port enabling" + "Valid range: 0x0 ~ 0x000F" + Combo $gPlatformFspPkgTokenSpaceGuid_PwDownMode, "Power Down Mode", &gPlatformFspPkgTokenSpaceGuid_PwDownMode, + Help "This option controls command bus tristating during idle periods" + EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX, + Help "This option configures Post Code Output Port" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX, + Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO" + "Valid range: 0 ~ 0x20" + Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS, + Help "Enable: SA CRID, Disable (Default): SA CRID" + EditNum $gPlatformFspPkgTokenSpaceGuid_PwDownIdleTimer, "Pwr Down Idle Timer", HEX, + Help "Default 0 = AUTO. Range is 30 to 2000(in us)" + "Valid range: 0x0 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_BclkRfiFreq, "BCLK RFI Frequency", HEX, + Help "Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No RFI Tuning. Range is 98Mhz-100Mhz." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX, + Help "Size of PCIe IMR in megabytes" + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS, + Help "0: Disable(AUTO), 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrRpLocation, "Enable PCIe IMR", &EN_DIS, + Help "1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or SA PCIe" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrRpSelection, "Root port number for IMR.", HEX, + Help "Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port from 0 to 23 and if it is SA PCIe then select root port from 0 to 3" + "Valid range: 0x00 ~ 0x17" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, + Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose." + Combo $gPlatformFspPkgTokenSpaceGuid_DdrOneDpc, "DdrOneDpc", &gPlatformFspPkgTokenSpaceGuid_DdrOneDpc, + Help "DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_OverrideDriverType, "Override Driver Type", HEX, + Help "Override Driver Type. 0=Auto, 1=CMOS, 2=NMOS" + "Valid range: 0x0 ~ 0x2" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lp5BypassVddqLimits, "Lp5 Bypass Vddq Limits", HEX, + Help "Bypass Lp5 Vccddq Fuse limits. Advised to keep disabled" + "Valid range: 0x0 ~ 0x1" + Combo $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable, "Enable/Disable I2cPostcode", &EN_DIS, + Help "Enable (Default): Postcode via I2C, Disable: Postcode via Port80" + EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride, "Vddq Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccIogVoltageOverride, "VccIog Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VccClkVoltageOverride, "VccClk Voltage Override", HEX, + Help "# is multiple of 1mV where 0 means Auto." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ExtendedBankHashing, "Extended Bank Hashing", &EN_DIS, + Help "Eanble/Disable ExtendedBankHashing" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lfsr1Mask, "RH pTRR LFSR1 Mask", HEX, + Help "Row Hammer pTRR LFSR1 Mask, 1/2^(value)" + "Valid range: 0x01 ~ 0xF" + Combo $gPlatformFspPkgTokenSpaceGuid_RefreshWm, "Refresh Watermarks", &gPlatformFspPkgTokenSpaceGuid_RefreshWm, + Help "Refresh Watermarks: 0-Low, 1-High (default)" + EditNum $gPlatformFspPkgTokenSpaceGuid_Lp5CccConfig, "Command Pins Mapping", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CmdMirror, "Command Pins Mirrored", HEX, + Help "BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipOverrideBootModeWhenFwUpdate, "Skip override boot mode When Fw Update.", &EN_DIS, + Help "When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init." + EditNum $gPlatformFspPkgTokenSpaceGuid_OppSrefIdleTmr, "Opportunistic Self Refresh IdleTimer", HEX, + Help "Default 0 = AUTO. Range is 500 to 10000(in us)" + "Valid range: 0x0 ~ 0x2710" + Combo $gPlatformFspPkgTokenSpaceGuid_LowerBasicMemTestSize, "LowerBasicMemTestSize", &EN_DIS, + Help "Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_BoardTopology, "Board Topology", HEX, + Help "0: Daisy, 1: Tee" + "Valid range: 0x00 ~ 0x0" + EditNum $gPlatformFspPkgTokenSpaceGuid_RxDqsDelayTempCoeff, "RxDqsDelayTempCoeff", HEX, + Help "Default = 4. Range from 0-255" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprTestType, "PPR Test Type", HEX, + Help "Select memory tests used in Post Package Repair flow. This option is only valid if PPR=1, otherwise ignored. Bit 0: WCMATS8 test, Bit 1: Data Retention test, Bit 2: X March test, Bit 3: X March G test, Bit 4: Y March Short test, Bit 5: Y March Long test. Default=0x3, WCMATS8 and data retention" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpd, "PreMemRsvd", &EN_DIS, + Help "Reserved for Pre-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_PprRepairType, "PPR Repair Type", &gPlatformFspPkgTokenSpaceGuid_PprRepairType, + Help "PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair" + Combo $gPlatformFspPkgTokenSpaceGuid_PprErrorInjection, "PPR Error Injection", &EN_DIS, + Help "When Eanble, PPR will inject bad rows during testing" + Combo $gPlatformFspPkgTokenSpaceGuid_PprForceRepair, "PPR ForceRepair", &EN_DIS, + Help "When Eanble, PPR will force repair some rows many times (90)" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairController, "PPR Repair Controller", HEX, + Help "PPR repair controller: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairChannel, "PPR Repair Channel", HEX, + Help "PPR repair Channel: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairDimm, "PPR Repair Dimm", HEX, + Help "PPR repair Dimm: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairRank, "PPR Repair Rank", HEX, + Help "PPR repair Rank: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0x01" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairRow, "PPR Repair Row", HEX, + Help "PPR repair Row: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrLow, "PPR Repair Physical Address Low", HEX, + Help "PPR repair Physical Address Low: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairPhysicalAddrHigh, "PPR Repair Physical Address High", HEX, + Help "PPR repair Physical Address High: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairBankGroup, "PPR Repair BankGroup", HEX, + Help "PPR repair BankGroup: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PprRepairBank, "PPR Repair Bank", HEX, + Help "PPR repair Bank: User chooses to force repair specifc address " + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTCASPLIT, "DIMM CA ODT Split Training", &EN_DIS, + Help "Enable/Disable DIMM CA ODT Split Training" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSSPLIT, "CMD Drive Strength Split", &EN_DIS, + Help "Enable/Disable CMD Drive Strength Split" + Combo $gPlatformFspPkgTokenSpaceGuid_CMDSRSPLIT, "CMD Slew Rate Split Training", &EN_DIS, + Help "Enable/Disable CMD Slew Rate Split Training" + EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX, + Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX, + Help "The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS, + Help "Reserved for SA Pre-Mem Test" +EndPage + +Page "PCH(PreMem)" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS, + Help "Enable/disable SMBus controller." + EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX, + Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugOption, + Help "Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n\nEnabled Trace ready: TraceHub is enabled and allowed S0ix.\n\nEnabled Trace power off: TraceHub is powergated, provide setting close to functional low power state\n\nManual: user needs to configure Advanced Debug Settings manually, aimed at advanced users" + Combo $gPlatformFspPkgTokenSpaceGuid_DciEn, "DCI Enable", &EN_DIS, + Help "Determine if to enable DCI debug from host" + Combo $gPlatformFspPkgTokenSpaceGuid_DciClkEnable, "DCI Clock Enable", &EN_DIS, + Help "Enable/Disable DCI clock in lowest power state" + Combo $gPlatformFspPkgTokenSpaceGuid_DciDbcMode, "DCI DbC Mode", &gPlatformFspPkgTokenSpaceGuid_DciDbcMode, + Help "Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value" + Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, + Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting." + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMode, "SOC Trace Hub Mode", &EN_DIS, + Help "Enable/Disable SOC TraceHub" + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size, "SOC Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg0Size, + Help "Select size of memory region 0 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size, "SOC Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_SocTraceHubMemReg1Size, + Help "Select size of memory region 1 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_KeepEarlyTrace, "Keep Early Trace", &EN_DIS, + Help "Trace is activated by default. When enable, keep early trace data and keep tracing, may block s0ix.\nWhen disabled will abandon trace data and stop tracing which allows enter s0ix\n\nnoted:enable this option will not enable TraceHub; When probe is connected, keep early trace will then be configured by tool, this option will not take effect." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &EN_DIS, + Help "Enable/Disable PCH TraceHub" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, + Help "Select size of memory region 0 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, + Help "Select size of memory region 1 buffer. Memory allocated by BIOS only applies to ITH tool running on the host. For ITH tool running on the target, choose None/OS, memory shall be allocated by tool. User should be cautious to choose the amount of memory. If chosen size is larger than half of system memory, setup will automatically rollback to default value." + Combo $gPlatformFspPkgTokenSpaceGuid_IoeDebugEn, "IOE Debug Enable", &EN_DIS, + Help "Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock is enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PmodeClkEn, "Pmode Clock Enable", &EN_DIS, + Help "Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use" + Combo $gPlatformFspPkgTokenSpaceGuid_AetTraceHubMode, "AET Trace Hub Mode Select", &gPlatformFspPkgTokenSpaceGuid_AetTraceHubMode, + Help "Select AET to Trace Hub destination." + Combo $gPlatformFspPkgTokenSpaceGuid_BiosTraceSinkMode, "BIOS trace destination", &gPlatformFspPkgTokenSpaceGuid_BiosTraceSinkMode, + Help "Select BIOS trace destination." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, "HD Audio DMIC Link Clock Select", &gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClockSelect, + Help "Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS, + Help "0: Disable, 1: Enable (Default) Azalia controller" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS, + Help "0: Disable, 1: Enable (Default) ISH Controller" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap1StepSize, "Dimm DFE Tap1 Step Size Setting", HEX, + Help "Dimm DFE Tap1 setting: Memory-dependent, positive value will be converted to minus values by *-1 automatically" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_DFETap2StepSize, "Dimm DFE Tap2 Step Size Setting", HEX, + Help "Dimm DFE Tap2 setting: Memory-dependent, positive value will be converted to minus values by *-1 automatically" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX, + Help "Enable PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX, + Help "PCH PCIe Gen 3 Set CTLE Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX, + Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX, + Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX, + Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX, + Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS, + Help "Original LPC only decodes one byte of port 80h." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS, + Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS, + Help "Enable SMBus ARP support." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX, + Help "The number of elements in the RsvdSmbusAddressTable." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX, + Help "SMBUS Base Address (IO space)." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS, + Help "Enable SMBus Alert Pin." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for SOC/IOE ClkSrc", HEX, + Help "0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieClkSrcUsage, "Usage type for PCH ClkSrc", HEX, + Help "0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "SOC/IOE ClkReq-to-ClkSrc mapping", HEX, + Help "Number of ClkReq signal assigned to ClkSrc" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieClkSrcClkReq, "PCH ClkReq-to-ClkSrc mapping", HEX, + Help "Number of ClkReq signal assigned to ClkSrc" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkReqGpioMux, "Clk Req GPIO Pin", HEX, + Help "Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX, + Help "Array of addresses reserved for non-ARP-capable SMBus devices." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieRpEnableMask, "Enable PCH PCIE RP Mask", HEX, + Help "Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable SOC/IOE PCIE RP Mask", HEX, + Help "Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on." + "Valid range: 0x00 ~ 0xFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, + Help "Virtual Channel Type Select: 0: VC0, 1: VC1." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS, + Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHdaEnable, "Enable HD Audio Link", &EN_DIS, + Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSdiEnable, "Enable HDA SDI lanes", HEX, + Help "Enable/disable HDA SDI lanes." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, "HDA Power/Clock Gating (PGD/CGD)", &gPlatformFspPkgTokenSpaceGuid_PchHdaTestPowerClockGating, + Help "Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicEnable, "Enable HD Audio DMIC_N Link", HEX, + Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_HdaDiscBtOffEnabled, "Discrete BT Offload Enabled", HEX, + Help "Enable/disable Discrete BT Offload." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchAdditionalIoRsvd, "PCH additional IO reserved", HEX, + Help "Additional IO reserved for PCH usage in KB" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkAPinMux, "DMIC ClkA Pin Muxing (N - DMIC number)", HEX, + Help "Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicClkBPinMux, "DMIC ClkB Pin Muxing", HEX, + Help "Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS, + Help "Enable/disable HD Audio DSP feature." + EditNum $gPlatformFspPkgTokenSpaceGuid_HdaDiscBtOffSspLink, "Discrete BT Offload Ssp Link", HEX, + Help "Select SSP link instance for Discrete BT Offload. Note that this SSP instance must also be enabled." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SocAdditionalMmioRsvd, "SoC additional MMIO reserved", HEX, + Help "Additional MMIO reserved for SoC usage (i.e TBT) in MB" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmicDataPinMux, "DMIC Data Pin Muxing", HEX, + Help "Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSspEnable, "Enable HD Audio SSP0 Link", HEX, + Help "Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndwEnable, "Enable HD Audio SoundWire#N Link", HEX, + Help "Enable/disable HD Audio SNDW#N link. Muxed with HDA." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, + Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdAudioSndwMultilaneEnable, "Sndw0 Multiline enablement", &EN_DIS, + Help "SoundWire Link 0 Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled, 2: Three lines enabled, 3: Four Lines enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, + Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS, + Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSubSystemIds, "Audio Sub System IDs", HEX, + Help "Set default Audio Sub System IDs. If its set to 0 then value from Strap is used." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim, "CNVi DDR RFI Mitigation", &EN_DIS, + Help "Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_ExtendedBiosDecodeRange, "Extended BIOS Support", &EN_DIS, + Help "Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeEnable, "Extented BIOS Direct Read Decode enable", &EN_DIS, + Help "Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. 0: disabled (default), 1: enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeBase, "Extended BIOS Direct Read Decode Range base", HEX, + Help "Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSpiExtendedBiosDecodeRangeLimit, "Extended BIOS Direct Read Decode Range limit", HEX, + Help "Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX, + Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used." + "Valid range: 0x00 ~ 0x3F" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, + Help "Select SerialIo Uart Controller for debug." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS, + Help "Enables UART hardware flow control, CTS and RTS lines." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC, + Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000" + "Valid range: 0 ~ 6000000" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, + Help "Set default Parity." + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, + Help "Set default stop bits." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0x08" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "SerialIo Uart PowerGating", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, + Help "Select SerialIo Uart Powergating mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMmioBase, "Serial Io Uart Debug Mmio Base", HEX, + Help "Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode = SerialIoUartPci." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, + Help "Select ISA Serial Base address. Default is 0x3F8." + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS, + Help "Disable or Enable Smbus dynamic power gating." + Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS, + Help "Set 1 to clear WDT status, then disable and lock WDT registers." + Combo $gPlatformFspPkgTokenSpaceGuid_SocBclkPllOn, "SoC BCLK PLL configuration", &EN_DIS, + Help "Configure SoC BCLK PLL state" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuBclkPllOn, "CPU BCLK PLL configuration", &EN_DIS, + Help "Configure CPU BCLK PLL state" + Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS, + Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverEn, "Dmi Tran Co Over En", HEX, + Help "Enable/Disable Lane Transmitter Coefficient." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverPostCur, "Dmi Tran Co Over Post Cur", HEX, + Help "Lane Transmitter Post-Cursor Coefficient Override." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiTranCoOverPreCur, "Dmi Tran Co Over Pre Cur", HEX, + Help "Lane Transmitter Pre-Cursor Coefficient Override." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiUpPortTranPreset, "Dmi Up Port Tran Preset", HEX, + Help "Upstream Port Lane Transmitter Preset." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiUpPortTranPresetEn, "Dmi UpPort Tran Preset En", HEX, + Help "0: POR setting, 1: force enable, 2: force disable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchDmiRtlepceb, "Dmi Rtlepceb", HEX, + Help "DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB)." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS, + Help "0: Disable, 1: Enable (Default) timeout check for HECI" + Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS, + Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable message check." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS, + Help "Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob." + Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS, + Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space." + Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS, + Help "Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor, "Avx2 Voltage Guardband Scaling Factor", HEX, + Help "AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor." + "Valid range: 0x00 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor, "Avx512 Voltage Guardband Scaling Factor", HEX, + Help "DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor." + "Valid range: 0x00 ~ 0xC8" + Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode, "Serial Io Uart Debug Mode", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode, + Help "Select SerialIo Uart Controller mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux, "SerialIoUartDebugRxPinMux - FSPM", HEX, + Help "Select RX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux, "SerialIoUartDebugTxPinMux - FSPM", HEX, + Help "Select TX pin muxing for SerialIo UART used for debug" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRtsPinMux, "SerialIoUartDebugRtsPinMux - FSPM", HEX, + Help "Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugCtsPinMux, "SerialIoUartDebugCtsPinMux - FSPM", HEX, + Help "Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugPciCfgBase, "Serial Io Uart Debug Pci Base", HEX, + Help "Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageMode, "Memory Subsystem voltage mode", &EN_DIS, + Help "Memory Subsystem voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSAdaptiveVoltage, "Memory Subsystem Adaptive Voltage", HEX, + Help "Adaptive voltage applied to the memory when the cpu is operating in adaptive mode. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageOverride, "Memory Subsystem voltage override", HEX, + Help "The Memory Subsystem voltage override which is applied to the entire range of memory frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + Combo $gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetMode, "Memory Subsystem VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_MemSSVfPointOffsetMode, + Help "Selects Memory Subsystem Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSMaxOcRatio, "Maximum Memory Subsystem turbo ratio override", HEX, + Help "Maximum Memory Subsystem turbo ratio override allows to increase memory frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85" + "Valid range: 0x00 ~ 0x55" + EditNum $gPlatformFspPkgTokenSpaceGuid_MemSSVoltageOffset, "Memory Subsystem Turbo voltage Offset", HEX, + Help "The voltage offset applied to the memory while operating in turbo mode. Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + Combo $gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode, "Select Core(s) and RING DLVR Mode", &gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode, + Help "DEPRECATED. Select Core(s) and RING DLVR Mode). 0: Regulation Mode; 1: Power Gate Mode" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguMaxOcRatio, "Maximum clr turbo ratio override", HEX, + Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85" + "Valid range: 0x00 ~ 0x55" + Combo $gPlatformFspPkgTokenSpaceGuid_NguVoltageMode, "NGU voltage mode", &EN_DIS, + Help "NGU voltage mode; 0: Adaptive; 1: Override." + EditNum $gPlatformFspPkgTokenSpaceGuid_NguRatio, "NGU Ratio", HEX, + Help "Sets the Ratio for NGU when SAGV is enabled, using SAVG B2P Mailbox cmd 0x22 and subcommand 0x1. When this value is zero, dynamic mode is selected and NGU ratio can be modified using OCMB cmd 0x11. When valid ratio value is set, static mode is selected with the fixed ratio specified by this value.. 0: Hardware defaults. Range: 0-85" + "Valid range: 0x00 ~ 0x55" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVoltageOverride, "NGU voltage override", HEX, + Help "The NGU voltage override which is applied to the entire range of cpu NGU frequencies. Valid Range 0 to 2000" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguAdaptiveVoltage, "adaptive voltage applied during turbo frequencies", HEX, + Help "0(Default)=Minimal, 2000=Maximum" + "Valid range: 0x00 ~ 0x7D0" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVoltageOffset, "NGU Turbo voltage Offset", HEX, + Help "The voltage offset applied to the NGU while operating in turbo mode. Valid Range 0 to 1000" + "Valid range: 0x00 ~ 0x3E8" + Combo $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetMode, "NGU VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetMode, + Help "Selects NGU Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffset, "NGU VF Point Offset", HEX, + Help "Array used to specifies the NGU Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVfPointOffsetPrefix, "NGU VF Point Offset Prefix", HEX, + Help "Sets the NguVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVfPointRatio, "NGU VF Point Ratio", HEX, + Help "Array for the each selected NGU VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NguVfPointCount, "NGU VF Point Count", HEX, + Help "Number of supported NGU Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetMode, "GT VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetMode, + Help "Selects GT Voltage & Frequency Offset mode between Legacy and Selection modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, setting a selected VF point; 0: Legacy; 1: Selection." + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffset, "GT VF Point Offset", HEX, + Help "Array used to specifies the GT Voltage Offset applied to the each selected VF Point. This voltage is specified in millivolts." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVfPointOffsetPrefix, "GT VF Point Offset Prefix", HEX, + Help "Sets the GtVfPointOffset value as positive or negative for corresponding core VF Point; 0: Positive ; 1: Negative." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVfPointRatio, "GT VF Point Ratio", HEX, + Help "Array for the each selected GT VF Point to display the ration." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GtVfPointCount, "GT VF Point Count", HEX, + Help "Number of supported GT Voltage & Frequency Point Offset" + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS, + Help "Time Measure: 0(Default)=Disable, 1=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_MrcMustStaticSpdData, "Must use static SPD data from VPD", HEX, + Help "Must use static SPD data from VPD and Spd Address is correct: Each bit maps to one dimm" + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TmeExcludeBase, "TME Exclude Base Address", HEX, + Help "TME Exclude Base Address." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TmeExcludeSize, "TME Exclude Size Value", HEX, + Help "TME Exclude Size Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_GenerateNewTmeKey, "Generate New TME Key", &EN_DIS, + Help "Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset" + EditNum $gPlatformFspPkgTokenSpaceGuid_CkdAddressTable, "CkdAddress Tabl", HEX, + Help "Specify CKD Address table for CH0D0/CH0D1/CH1D0&CH1D1" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping, "Channel to CKD QCK Mapping", HEX, + Help "Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm, "DDRIO Clock to CKD DIMM", HEX, + Help "Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1" + "Valid range: 0x00 ~ 0xFF" +EndPage + +Page "System Agent(PostMem)" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX, + Help "Points to PEI Display Logo Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX, + Help "Size of PEI Display Logo Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX, + Help "Address of Blt buffer" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX, + Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX, + Help "Points to VBT" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS, + Help "Enable/disable Device 4" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX, + Help "Memory Base of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX, + Help "Size of Microcode Updates" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS, + Help "Enable/Disable processor Turbo Mode. 0:disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS, + Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable" + Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS, + Help "Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer." + Combo $gPlatformFspPkgTokenSpaceGuid_D3HotEnable, "Enable D3 Hot in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 hot support in IOM" + Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS, + Help "0=Disable, 1(Default)=Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg, "TypeC port GPIO setting", HEX, + Help "GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl = MeteorLake)" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin, "CPU USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USBC Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_D3ColdEnable, "Enable D3 Cold in TCSS ", &EN_DIS, + Help "This policy will enable/disable D3 cold support in IOM" + Combo $gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4, "Enable/Disable PCIe tunneling for USB4", &EN_DIS, + Help "Enable/Disable PCIe tunneling for USB4, default is enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SkipFspGop, "Enable/Disable SkipFspGop", &EN_DIS, + Help "Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver" + Combo $gPlatformFspPkgTokenSpaceGuid_VpuEnable, "Enable/Disable VPU Device", &EN_DIS, + Help "Enable(Default): Enable VPU Device, Disable: Disable VPU Device" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcCstateLimit, "TC State in TCSS ", HEX, + Help "This TC C-State Limit in IOM" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TcNotifyIgd, "Display port support policy in TCSS ", &EN_DIS, + Help "This policy will enable/disable Display port support in IOM" + EditNum $gPlatformFspPkgTokenSpaceGuid_VbtSize, "Intel Graphics VBT (Video BIOS Table) Size", HEX, + Help "Size of Internal Graphics VBT Image" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_LidStatus, "Platform LID Status for LFP Displays.", &gPlatformFspPkgTokenSpaceGuid_LidStatus, + Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen." + Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd, "PchPostMemRsvd", &EN_DIS, + Help "Reserved for PCH Post-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdEnable, "Enable VMD controller", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable; 1: Enable(Default)" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping, "Enable VMD Global Mapping", &EN_DIS, + Help "Enable/disable to VMD controller.0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_VmdPort, "Map port under VMD", &EN_DIS, + Help "Map/UnMap port under VMD" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortBus, "VMD Port Bus", DEC, + Help "VMD Root port bus number." + "Valid range: 0 ~ 255" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortDev, "VMD Port Device", DEC, + Help "VMD Root port device number." + "Valid range: 0 ~ 31" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc, "VMD Port Func", DEC, + Help "VMD Root port function number." + "Valid range: 0 ~ 7" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr, "VMD Variable", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase, "Temporary CfgBar address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base, "Temporary MemBar1 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base, "Temporary MemBar2 address for VMD", HEX, + Help "VMD Variable Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX, + Help "BgpdtHash values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX, + Help "BiosGuardAttr default values" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX, + Help "BiosGuardModulePtr default values" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX, + Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX, + Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX, + Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcProvisionEav, "EcProvisionEav", HEX, + Help "EcProvisionEav function pointer. \n @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8 *ReturnValue); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_EcBiosGuardCmdLock, "EcBiosGuardCmdLock", HEX, + Help "EcBiosGuardCmdLock function pointer. \n @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SiSkipSsidProgramming, "Skip Ssid Programming.", &EN_DIS, + Help "When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly." + EditNum $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSvid, "Change Default SVID", HEX, + Help "Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiCustomizedSsid, "Change Default SSID", HEX, + Help "Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX, + Help "The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX, + Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortResetMessageEnable, "USB2 Port Reset Message Enable", HEX, + Help "0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, + Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS, + Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS, + Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin." + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, + Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS, + Help "Central Write Buffer feature configurable and enabled by default" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcOsIdleEnable, "OS IDLE Mode Enable", &EN_DIS, + Help "Enable/Disable OS Idle Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PchS0ixAutoDemotion, "S0ix Auto-Demotion", &EN_DIS, + Help "Enable/Disable the Low Power Mode Auto-Demotion Host Control feature." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLatchEventsC10Exit, "Latch Events C10 Exit", &EN_DIS, + Help "When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default)" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrEn, "PMC ADR enable", &EN_DIS, + Help "Enable/disable asynchronous DRAM refresh" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimerEn, "PMC ADR timer configuration enable", &EN_DIS, + Help "Enable/disable ADR timer configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrTimer1Val, "PMC ADR phase 1 timer value", HEX, + Help "Enable/disable ADR timer configuration" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrMultiplier1Val, "PMC ADR phase 1 timer multiplier value", HEX, + Help "Specify the multiplier value for phase 1 ADR timer" + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrHostPartitionReset, "PMC ADR host reset partition enable", &EN_DIS, + Help "Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcOverride, "PMC ADR source select override enable", &EN_DIS, + Help "Tells the FSP to update the source select with platform value" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcAdrSrcSel, "PMC ADR source selection", HEX, + Help "Specify which sources should cause ADR flow" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcWdtTimerEn, "PMC WDT enable", &EN_DIS, + Help "Enable/disable PMC WDT configuration" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieClockGating, "PCIe RootPort Clock Gating", &EN_DIS, + Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PciePowerGating, "PCIe RootPort Power Gating", &EN_DIS, + Help "Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieFomsCp, "FOMS Control Policy", &gPlatformFspPkgTokenSpaceGuid_PcieFomsCp, + Help "Choose the Foms Control Policy, Default = 0 " + Combo $gPlatformFspPkgTokenSpaceGuid_LinkDownGpios, "PCIe GPIO Assertion in Link Down", &EN_DIS, + Help "Describes whether the PCIe GPIO Assertion in Link Down programming is enabled for each root portby platform modules. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM regsiter lock", &EN_DIS, + Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC" + Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS, + Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigureGT, "Enable/Disable GT Configuration", &EN_DIS, + Help "Enable(Default): Configure GT for use, Disable: Skip GT Configuration" + Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax, + Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS, + Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency" + Combo $gPlatformFspPkgTokenSpaceGuid_RC1pGtFreqEnable, "Enable RC1p GT frequency request to PMA (provided all other conditions are met)", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_RC1pMediaFreqEnable, "Enable RC1p Media frequency request to PMA (provided all other conditions are met)", &EN_DIS, + Help "0(Default)=Disable, 1=Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnMultiVcEnable, "Enable TSN Multi-VC", &EN_DIS, + Help "Enable/disable Multi Virtual Channels(VC) in TSN." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcLimitC3AndDeeperWA, "PMC Limit Powergating", &EN_DIS, + Help "Enable/disable Limit PSF powergating to C3 and deeper states" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX, + Help "Address of LogoPixelHeight" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX, + Help "Address of LogoPixelWidth" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigureMedia, "Enable/Disable Media Configuration", &EN_DIS, + Help "Enable(Default): Configure Media for use, Disable: Skip Media Configuration" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb4CmMode, "ITbt Usb4CmMode value", HEX, + Help "ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_HorizontalResolution, "HorizontalResolution for PEI Logo", HEX, + Help "HorizontalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_VerticalResolution, "VerticalResolution for PEI Logo", HEX, + Help "VerticalResolution from PEIm Gfx for PEI Logo" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_MediaStandby, "Enable/Disable IGFX Media Standby", &EN_DIS, + Help "Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby" + Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS, + Help "Reserved for SA Post-Mem Test" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableRsr, "RSR feature", &EN_DIS, + Help "Enable or Disable RSR feature; 0: Disable; 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem1, "ReservedCpuPostMem1", &EN_DIS, + Help "Reserved for CPU Post-Mem 1" + Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS, + Help "Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: Enable;" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX, + Help "Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS, + Help "Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS, + Help "Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register. 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX, + Help "Power Limit 3 Time Window value in Milli seconds. Indicates the time window over which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX, + Help "Specify the duty cycle in percentage that the CPU is required to maintain over the configured time window. Range is 0-100." + "Valid range: 0x00 ~ 0x64" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS, + Help "Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled PL3 configuration can be changed during OS. 0: Disable ; 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS, + Help "Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled PL4 configuration can be changed during OS. 0: Disable ; 1:Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX, + Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts. Default = 0h." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS, + Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1. 0: Disabled; 1: Enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS, + Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX, + Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table. Sets the number of custom P-states. At least 2 states must be present" + "Valid range: 0x00 ~ 0x28" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained." + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained." + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX, + Help "Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained." + "Valid range: 0x00 ~ 0x80" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX, + Help "Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX, + Help "Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2" + "Valid range: 0x00 ~ 0x2" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS, + Help "cTDP(Assured Power) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP(Assured Power) Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS, + Help "Enables cTDP(Assured Power) control via runtime ACPI BIOS methods. This 'BIOS only' feature does not require EC or driver support. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS, + Help "Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX, + Help "Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform Processor Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128" + "Valid range: 0x00 ~ 0x80" + Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS, + Help "Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS, + Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS, + Help "Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner should not set in MWAIT Loop. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS, + Help "Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner, + Help "AP threads Idle Manner for waiting signal to run. 1: HALT loop; 2: MWAIT loop; 3: RUN loop." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, + Help "Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS, + Help "Enable or Disable Processor Trace feature; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS, + Help "Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS, + Help "Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is supported. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &EN_DIS, + Help "Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS, + Help "Enable or Disable T states; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS, + Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS, + Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS, + Help "Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS, + Help "Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableAllThermalFunctions, "Enable or Disable Thermal Reporting", &EN_DIS, + Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS, + Help "Enable or Disable Thermal Monitor; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS, + Help "Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS, + Help "Configure MSR to CFG Lock bit. 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS, + Help "Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS, + Help "Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS, + Help "Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS, + Help "Enable or Disable TimedMwait Support. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS, + Help "When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset). 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX, + Help "Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit. Valid values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - CPU Default, 255 - Auto" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX, + Help "Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: Round robin; 2: Hash vector; 7: No change." + "Valid range: 0x00 ~ 0x7" + Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS, + Help "Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX, + Help "cTDP(Assured Power) Mode as Nominal/Level1/Level2/Deactivate TDP(Base Power) selection. Deactivate option will set MSR to Nominal and MMIO to Zero. 0: TDP(Base Power) Nominal; 1: TDP(Base Power) Down; 2: TDP(Base Power) Up;0xFF : Deactivate" + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX, + Help "Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F" + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX, + Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F" + EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX, + Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F" + "Valid range: 0x00 ~ 0x7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX, + Help "Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor Base Power (TDP). Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX, + Help "Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX, + Help "Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Boost, "Package PL4 boost configuration", HEX, + Help "Configure Power Limit 4 Boost in Watts. Valid Range 0 to 1023 in step size of 1 Watt. The value 0 means disable." + "Valid range: 0x00 ~ 0x3FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX, + Help "" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX, + Help "Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX, + Help "Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX, + Help "Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX, + Help "Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX, + Help "Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new PL1 value for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX, + Help "Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767." + "Valid range: 0x00 ~ 0x7FFF" + Combo $gPlatformFspPkgTokenSpaceGuid_CcfAutoGv, "CCF AutoGV", &EN_DIS, + Help "Enable/Disable CCF AutoGV; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS, + Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounter, "Enable or Disable Three Strike Counter", &EN_DIS, + Help "Enable (default): Three Strike counter will be incremented. Disable: Prevents Three Strike counter from incrementing; 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS, + Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMem2, "ReservedCpuPostMem2", &EN_DIS, + Help "Reserved for CPU Post-Mem 2" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS, + Help "Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS, + Help "Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX, + Help "Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Maximum Ring ratio limit override", HEX, + Help "Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit" + "Valid range: 0x00 ~ 0x53" + Combo $gPlatformFspPkgTokenSpaceGuid_EnablePerCorePState, "Enable or Disable Per Core P State OS control", &EN_DIS, + Help "Enable/Disable Per Core P state OS control mode. When set, the highest core request is used for all other core requests. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoPerCorePstate, "Enable or Disable HwP Autonomous Per Core P State OS control", &EN_DIS, + Help "Disable Autonomous PCPS Autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableHwpAutoEppGrouping, "Enable or Disable HwP Autonomous EPP Grouping", &EN_DIS, + Help "Enable EPP grouping Autonomous will request the same values for all cores with same EPP. Disable EPP grouping autonomous will not necessarily request same values for all cores with same EPP. 0: Disable ; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_ApplyConfigTdp, "Enable Configurable TDP", &EN_DIS, + Help "Applies cTDP(Assured Power) initialization settings based on non-cTDP(Assured Power) or cTDP(Assured Power). Default is 1: Applies to cTDP(Assured Power); if 0 then applies non-cTDP(Assured Power) and BIOS will bypass cTDP(Assured Power) initialzation flow" + Combo $gPlatformFspPkgTokenSpaceGuid_HwpLock, "Misc Power Management MSR Lock", &EN_DIS, + Help "Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS, + Help "Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_StepDownMode, "Response Mode", &gPlatformFspPkgTokenSpaceGuid_StepDownMode, + Help "Use Response Mode to adjust Psys_PL3 power reduction behavior. Battery-enabled systems use Gradual Power Reduction. 0: Gradual Power Reduction ; 1: Aggressive Power Reduction" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorManagement, "Power Floor Managment for SOC", &EN_DIS, + Help "Option to disable Power Floor Managment for SOC. Disabling this might effectively raise power floor of the SoC and may lead to stability issues. 0: Disable, 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorDisplayDisconnect, "Power Floor Disaplay Disconnect", &EN_DIS, + Help "SoC can disconnect secondary/external display to lower SoC floor power (Default enabled). 0: Disable: Display disconnect will not be used by SoC., 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_EnableRp, "Resource Priority Feature", &EN_DIS, + Help "Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable ; 1:Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PowerFloorPcieGenDowngrade, "Power Floor PCIe Gen Downgrade", &EN_DIS, + Help "SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0: Disable: Reduction in PCIe gen speed will not be used by SoC., 1: Enable " + Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS, + Help "Reserved for CPU Post-Mem Test" +EndPage + +Page "PCH(PostMem)" + Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS, + Help "Enable/disable to show SPI controller." + Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS, + Help "Enable/disable SATA Aggressive Link Power Management." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX, + Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX, + Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortDevSlpPinMux, "SATA DEVSLP GPIO Pin", HEX, + Help "Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX, + Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX, + Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS, + Help "Enable/disable to xDCI controller." + EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX, + Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX, + Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL." + "Valid range: 0x00 ~ 0x40" + EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX, + Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX, + Help "GPIO IRQ Select. The valid value is 14 or 15." + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX, + Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only." + "Valid range: 0x00 ~ 0x17" + EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX, + Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23." + "Valid range: 0x00 ~ 0x17" + Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS, + Help "Enable/disable TCO IRQ" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX, + Help "Number of Entries in Verb Table." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX, + Help "Pointer to Array of pointers to Verb Table." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS, + Help "Enable/disable SATA controller." + Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode, + Help "Select SATA controller working mode." + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX, + Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPolarity, "SPI Chip Select Polarity", HEX, + Help "Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsEnable, "SPI Chip Select Enable", HEX, + Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX, + Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsMode, "SPIn Default Chip Select Mode HW/SW", HEX, + Help "Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState, "SPIn Default Chip Select State Low/High", HEX, + Help "Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPinMux, "Serial IO SPI CS Pin Muxing", HEX, + Help "Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiClkPinMux, "Serial IO SPI CLK Pin Muxing", HEX, + Help "Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMisoPinMux, "Serial IO SPI MISO Pin Muxing", HEX, + Help "Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMosiPinMux, "Serial IO SPI MOSI Pin Muxing", HEX, + Help "Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX, + Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX, + Help "Set default BaudRate Supported from 0 - default to 6000000" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX, + Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX, + Help "Set default word length. 0: Default, 5,6,7,8" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX, + Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX, + Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX, + Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled" + "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX, + Help "Enables UART hardware flow control, CTS and RTS lines." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRtsPinMuxPolicy, "SerialIoUartRtsPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy, "SerialIoUartCtsPinMuxPolicy", HEX, + Help "Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy, "SerialIoUartRxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy, "SerialIoUartTxPinMuxPolicy", HEX, + Help "Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX, + Help "Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX, + Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux, "Serial IO I2C SDA Pin Muxing", HEX, + Help "Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSclPinMux, "Serial IO I2C SCL Pin Muxing", HEX, + Help "Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cMode, "I3C Device Mode", HEX, + Help "Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)" + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPinMux, "Serial IO I3C SDA Pin Muxing", HEX, + Help "Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSdaPadTermination, "Serial IO I3C SDA Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPinMux, "Serial IO I3C SCL Pin Muxing", HEX, + Help "Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclPadTermination, "Serial IO I3C SCL Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPinMux, "Serial IO I3C SCL FB Pin Muxing", HEX, + Help "Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI3cSclFbPadTermination, "Serial IO I3C SCL FB Pad Termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on." + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPinMuxing, "ISH GP GPIO Pin Muxing", HEX, + Help "Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPinMuxing, "ISH UART Rx Pin Muxing", HEX, + Help "Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPinMuxing, "ISH UART Tx Pin Muxing", HEX, + Help "Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPinMuxing, "ISH UART Rts Pin Muxing", HEX, + Help "Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPinMuxing, "ISH I2C SDA Pin Muxing", HEX, + Help "Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPinMuxing, "ISH I2C SCL Pin Muxing", HEX, + Help "Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPinMuxing, "ISH I3C SDA Pin Muxing", HEX, + Help "Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPinMuxing, "ISH I3C SCL Pin Muxing", HEX, + Help "Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPinMuxing, "ISH SPI MOSI Pin Muxing", HEX, + Help "Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPinMuxing, "ISH SPI MISO Pin Muxing", HEX, + Help "Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPinMuxing, "ISH SPI CLK Pin Muxing", HEX, + Help "Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPinMuxing, "ISH SPI CS#N Pin Muxing", HEX, + Help "Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible values. N-SPI number, 0-1." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshGpGpioPadTermination, "ISH GP GPIO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRxPadTermination, "ISH UART Rx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 Rx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartTxPadTermination, "ISH UART Tx Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 Tx, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartRtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 Rts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshUartCtsPadTermination, "ISH UART Rts Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 Cts, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSdaPadTermination, "ISH I2C SDA Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSdaPadTermination, "ISH I3C SDA Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, and so on." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI2cSclPadTermination, "ISH I2C SCL Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshI3cSclPadTermination, "ISH I3C SCL Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, and so on." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMosiPadTermination, "ISH SPI MOSI Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 Mosi, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiMisoPadTermination, "ISH SPI MISO Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 Miso, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiClkPadTermination, "ISH SPI CLK Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, and so on." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IshSpiCsPadTermination, "ISH SPI CS#N Pad termination", HEX, + Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCsEnable, "Enable PCH ISH SPI Cs#N pins assigned", HEX, + Help "Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs number: 0-1" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPetxiset, "USB Per Port HS Preemphasis Bias", HEX, + Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyTxiset, "USB Per Port HS Transmitter Bias", HEX, + Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPredeemp, "USB Per Port HS Transmitter Emphasis", HEX, + Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2PhyPehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX, + Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX, + Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX, + Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS, + Help "Enable/disable LAN controller." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnEnable, "Enable PCH TSN", &EN_DIS, + Help "Enable/disable TSN on the PCH." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed, "TSN Link Speed", &gPlatformFspPkgTokenSpaceGuid_PchTsnLinkSpeed, + Help "Set TSN Link Speed." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressHigh, "PCH TSN MAC Address High Bits", HEX, + Help "Set TSN MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsnMacAddressLow, "PCH TSN MAC Address Low Bits", HEX, + Help "Set TSN MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressHigh, "PCH TSN MAC Address High Bits", HEX, + Help "Set TSN MAC Address High." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressLow, "PCH TSN MAC Address Low Bits", HEX, + Help "Set TSN MAC Address Low." + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PciePtm, "PCIe PTM enable/disable", HEX, + Help "Enable/disable Precision Time Measurement for PCIE Root Ports." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_DmiPowerGatingDis, "Disable DMI Power Gating", &EN_DIS, + Help "Enable/disable DMI Power Gating Disable." + Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS, + Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX, + Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range" + "Valid range: 0x00 ~ 0x009C4000" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeHostDeviceEnabled, "PCH eSPI Host and Device BME enabled", &EN_DIS, + Help "PCH eSPI Host and Device BME enabled" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS, + Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target addresseses from range 0x0 - 0x7FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailEnabledStates, "Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states", HEX, + Help "Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailSupportedVoltageStates, "Mask to enable the platform configuration of external V1p05 VR rail", HEX, + Help "External V1P05 Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailVoltage, "External V1P05 Voltage Value that will be used in S0i2/S0i3 states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMax, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailEnabledStates, "Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states", HEX, + Help "Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSupportedVoltageStates, "Mask to enable the platform configuration of external Vnn VR rail", HEX, + Help "External Vnn Rail Supported Configuration" + "Valid range: 0x00 ~ 0x0F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailVoltage, "External Vnn Voltage Value that will be used in S0ix/Sx states", HEX, + Help "Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMax, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxEnabledStates, "Mask to enable the usage of external Vnn VR rail in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5" + "Valid range: 0x00 ~ 0x1F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxVoltage, "External Vnn Voltage Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)" + "Valid range: 0x0 ~ 0x07FF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMax, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA" + "Valid range: 0x0 ~ 0xC8" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxLowToHighCurModeVolTranTime, "Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToHighCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxRetToLowCurModeVolTranTime, "Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrVccinAuxOffToHighCurModeVolTranTime, "Transition time in microseconds from Off (0V) to High Current Mode Voltage", HEX, + Help "This field has 1us resolution. When value is 0 Transition to 0V is disabled." + "Valid range: 0x0 ~ 0x7FF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS, + Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer to ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX, + Help "ChipsetInit Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NphyBinPtr, "Pointer to NPHY Binary", HEX, + Help "Nphy Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_NphyBinLen, "Length of NPHY Binary", HEX, + Help "Nphy Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinPtr, "Pointer to SYNPS PHY Binary", HEX, + Help "Synps Binary Pointer." + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SynpsPhyBinLen, "Length of SYNPS PHY Binary", HEX, + Help "Synps Binary Length." + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchFivrDynPm, "FIVR Dynamic Power Management", &EN_DIS, + Help "Enable/Disable FIVR Dynamic Power Management." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailIccMaximum, "External V1P05 Icc Max Value", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailIccMaximum, "External Vnn Icc Max Value that will be used in S0ix/Sx states", HEX, + Help "Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailSxIccMaximum, "External Vnn Icc Max Value that will be used in Sx states", HEX, + Help "Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA" + "Valid range: 0x0 ~ 0x1F4" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciUaolEnable, "USB Audio Offload enable", &EN_DIS, + Help "Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)" + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciHsiiEnable, "PCH xHCI enable HS Interrupt IN Alarm", &EN_DIS, + Help "PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchGpioUnlockDataPtr, "PCH GPIOV2 Unlock Data Buffer Address", HEX, + Help "Address of GPIO Unlock Data buffer" + "Valid range: 0x0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchGpioUnlockDataSize, "PCH GPIOV2 Unlock Data Buffer Size", HEX, + Help "Size of PCH GPIO Unlock Data Buffer" + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPostMemRsvd, "PchPostMemRsvd", &EN_DIS, + Help "Reserved for PCH Post-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode, + Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi." + Combo $gPlatformFspPkgTokenSpaceGuid_CnviWifiCore, "CNVi Wi-Fi Core", &EN_DIS, + Help "Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS, + Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE" + Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS, + Help "Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviRfResetPinMux, "CNVi RF_RESET pin muxing", HEX, + Help "Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_CnviClkreqPinMux, "CNVi CLKREQ pin muxing", HEX, + Help "Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h." + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiHostC10ReportEnable, "Enable Host C10 reporting through eSPI", &EN_DIS, + Help "Enable/disable Host C10 reporting to Device via eSPI Virtual Wire." + Combo $gPlatformFspPkgTokenSpaceGuid_PmcUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS, + Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS, + Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode ", &EN_DIS, + Help "This option enables or disables espi lgmr " + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtV1p05RailCtrlRampTmr, "External V1P05 Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the v1p05_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchFivrExtVnnRailCtrlRampTmr, "External VNN Control Ramp Timer value", HEX, + Help "Hold off time to be used when changing the vnn_ctrl for external bypass value in us" + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX, + Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, + Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, + Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS, + Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality." + Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0." + Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0." + Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS, + Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0." + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX, + Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX, + Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX, + Help "0: built-in device, 1:slot" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX, + Help "Enable/Disable PCIE RP Access Control Services Extended Capability" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX, + Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX, + Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS, + Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05PhyExtFetControlEn, "V1p05-PHY supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcV1p05IsExtFetControlEn, "V1p05-IS supply external FET control", &EN_DIS, + Help "Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS, + Help "Enable DMI Power Optimizer on PCH side." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX, + Help "Write or erase is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX, + Help "Read is blocked by hardware." + "Valid range: 0x00 ~ 0xFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX, + Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS, + Help "Enable Azalia wake-on-ring." + Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, + Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiCs0Enable, "Enable PCH ISH SPI Cs0 pins assigned", HEX, + Help "Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS, + Help "0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX, + Help "This member determines IOAPIC ID. Default is 0x02." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshSpiEnable, "Enable PCH ISH SPI pins assigned", HEX, + Help "Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshUartEnable, "Enable PCH ISH UART pins assigned", HEX, + Help "Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshI2cEnable, "Enable PCH ISH I2C pins assigned", HEX, + Help "Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshI3cEnable, "Enable PCH ISH I3C pins assigned", HEX, + Help "Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchIshGpEnable, "Enable PCH ISH GP pins assigned", HEX, + Help "Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS, + Help "0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt, "PCH ISH Disable MSI Interrupts", &EN_DIS, + Help "0: False; 1: True." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS, + Help "0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS, + Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection." + Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS, + Help "This member describes whether or not the CRID feature of PCH should be enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_RtcBiosInterfaceLock, "RTC BIOS Interface Lock", &EN_DIS, + Help "Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed." + Combo $gPlatformFspPkgTokenSpaceGuid_RtcMemoryLock, "RTC Cmos Memory Lock", &EN_DIS, + Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX, + Help "Indicate whether the root port is hot plug available." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", &EN_DIS, + Help "Indicate whether the root port power manager SCI is enabled." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX, + Help "Indicate whether the Transmitter Half Swing is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX, + Help "Probe CLKREQ# signal before enabling CLKREQ# based power management." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX, + Help "Indicate whether the Advanced Error Reporting is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX, + Help "Indicate whether the Unsupported Request Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX, + Help "Indicate whether the Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX, + Help "Indicate whether the No Fatal Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX, + Help "Indicate whether the Correctable Error Report is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX, + Help "Indicate whether the System Error on Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX, + Help "Indicate whether the System Error on Non Fatal Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX, + Help "Indicate whether the System Error on Correctable Error is enabled." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX, + Help "Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcAssignment, "Touch Host Controller Assignment", HEX, + Help "Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcInterruptPinMuxing, "Touch Host Controller Interrupt Pin Mux", HEX, + Help "Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values." + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcMode, "Touch Host Controller Mode", HEX, + Help "Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcWakeOnTouch, "Touch Host Controller Wake On Touch", HEX, + Help "Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI" + "Valid range: 0 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcActiveLtr, "Touch Host Controller Active Ltr", HEX, + Help "Expose Active Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcIdleLtr, "Touch Host Controller Idle Ltr", HEX, + Help "Expose Idle Ltr for OS driver to set" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetPad, "Touch Host Controller Hid Over Spi ResetPad", HEX, + Help "Hid Over Spi ResetPad" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetPadTrigger, "Touch Host Controller Hid Over Spi ResetPad Trigger", HEX, + Help "Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiConnectionSpeed, "Touch Host Controller Hid Over Spi Connection Speed", HEX, + Help "Hid Over Spi Connection Speed - SPI Frequency" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiLimitPacketSize, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcPerformanceLimitation, "Touch Host Controller Hid Over Spi Limit PacketSize", HEX, + Help "Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, 1-65535 (0xFFFF) - up to 655350 us" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportHeaderAddress, "Touch Host Controller Hid Over Spi Input Report Header Address", HEX, + Help "Hid Over Spi Input Report Header Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiInputReportBodyAddress, "Touch Host Controller Hid Over Spi Input Report Body Address", HEX, + Help "Hid Over Spi Input Report Body Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiOutputReportAddress, "Touch Host Controller Hid Over Spi Output Report Address", HEX, + Help "Hid Over Spi Output Report Address" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiReadOpcode, "Touch Host Controller Hid Over Spi Read Opcode", HEX, + Help "Hid Over Spi Read Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiWriteOpcode, "Touch Host Controller Hid Over Spi Write Opcode", HEX, + Help "Hid Over Spi Write Opcode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcHidSpiFlags, "Touch Host Controller Hid Over Spi Flags", HEX, + Help "Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode" + "Valid range: 0 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_ThcResetSequencingDelay, "Touch Host Controller Hid Over Spi Reset Sequencing Delay [ms]", HEX, + Help "Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX, + Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX, + Help "Indicates the slot number for the root port. Default is the value as root port index." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX, + Help "The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX, + Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX, + Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX, + Help "Latency Tolerance Reporting Mechanism." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX, + Help "0: Disable; 1: Enable." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEqOverrideDefault, "PCIE RP override default settings for EQ", &EN_DIS, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen3EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen4EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod, "PCIE RP choose EQ method", &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMethod, + Help "Choose PCIe EQ method" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode, "PCIE RP choose EQ mode", &gPlatformFspPkgTokenSpaceGuid_PcieGen5EqMode, + Help "Choose PCIe EQ mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqLocalTxOverrideEn, "PCIE RP EQ local transmitter override", &EN_DIS, + Help "Enable/Disable local transmitter override" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3NoOfPresetOrCoeff, "PCI RP number of valid list entries", HEX, + Help "Select number of presets or coefficients depending on the mode" + "Valid range: 0 ~ 11" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor0List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor0List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor1List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor1List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor2List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor2List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor3List, "PCIR RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor3List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor4List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor4List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor5List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor5List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor6List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor6List, "PCIe post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor7List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor7List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor8List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor8List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PreCursor9List, "PCIE RP pre-cursor coefficient list", HEX, + Help "Provide a list of pre-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0x0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3PostCursor9List, "PCIE RP post-cursor coefficient list", HEX, + Help "Provide a list of post-cursor coefficients to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset0List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset1List, "PCIe preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset2List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset3List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset4List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset5List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset6List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset7List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset8List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset9List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh3Preset10List, "PCIE RP preset list", HEX, + Help "Provide a list of presets to be used during phase 3 EQ" + "Valid range: 0 ~ 0x3F3F3F3F3F3F3F3F3F3F3F" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1DpTxPreset, "PCIe EQ phase 1 downstream transmitter port preset", HEX, + Help "Allows to select the downstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh1UpTxPreset, "PCIE RP EQ phase 1 upstream tranmitter port preset", HEX, + Help "Allows to select the upstream port preset value that will be used during phase 1 of equalization" + "Valid range: 0 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5EqPh2LocalTxOverridePreset, "PCIE RP EQ phase 2 local transmitter override preset", HEX, + Help "Allows to select the value of the preset used during phase 2 local transmitter override" + "Valid range: 0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass, "Phase3 RP Gen3 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Bypass, + Help "Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass, "Phase3 RP Gen3 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh3Bypass, + Help "Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass, "Phase3 RP Gen5 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh3Bypass, + Help "Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass, "Phase2-3 RP Gen3 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh23Bypass, + Help "Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass, "Phase2-3 RP Gen4 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPh23Bypass, + Help "Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass, "Phase2-3 RP Gen5 EQ enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPh23Bypass, + Help "Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): Enable Phase2-3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPhBypass, "RP Gen3 EQ Phase enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPhBypass, + Help "Gen3 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPhBypass, "RP Gen4 EQ Phase enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen4EqPhBypass, + Help "Gen4 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPhBypass, "RP Gen5 EQ Phase enable", &gPlatformFspPkgTokenSpaceGuid_PcieRpGen5EqPhBypass, + Help "Gen5 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3PcetTimer, "PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4PcetTimer, "Gen4 PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5PcetTimer, "Gen5 PCET Timer", HEX, + Help "Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default is 0x0(2ms)" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen3TsLockTimer, "TS Lock Timer for Gen3", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen4TsLockTimer, "PTS Lock Timer for Gen4", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieGen5TsLockTimer, "PTS Lock Timer for Gen5", HEX, + Help "Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0" + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieSetSecuredRegisterLock, "PCIE Secure Register Lock", &EN_DIS, + Help "Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_DGWait, "DG Wait", &EN_DIS, + Help "0(Default) = Disable, 1 = Enable" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTestAspmOc, "Enable/Disable ASPM Optionality Compliance", HEX, + Help "Enable/Disable ASPM Optionality Compliance." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieCfgDump, "PCIe Configuration Dump", &gPlatformFspPkgTokenSpaceGuid_PcieCfgDump, + Help "Enable/Disable ASPM Optionality Compliance." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE RP Enable Peer Memory Write", &EN_DIS, + Help "This member describes whether Peer Memory Writes are enabled on the platform." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS, + Help "Compliance Test Mode shall be enabled when using Compliance Load Board." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS, + Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieFiaProgramming, "PCIe Fia Programming", &EN_DIS, + Help "Load Fia configuration if enable. 0: Disable; 1: Enable(Default)." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS, + Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1." + Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS, + Help "Enables Isolated Memory Region for PCIe." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX, + Help "Selects PCIE root port number for IMR feature." + "Valid range: 0x0 ~ 23" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS, + Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS, + Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS, + Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS, + Help "Determine if enable LAN to wake from deep Sx." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS, + Help "Deep Sx Policy." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS, + Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX, + Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX, + Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX, + Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX, + Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for VISA", &EN_DIS, + Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when VISA pin is muxed with USB OC" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS, + Help "Enable SLP_X Stretching After SUS Well Power Up." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS, + Help "Enable/Disable SLP_LAN# Low on DC Power." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX, + Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS, + Help "Power button native mode disable." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS, + Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS, + Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX, + Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX, + Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS, + Help "Set to enable low latency of legacy IO. 0: Disable, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS, + Help "SATA Power Optimizer on PCH side." + Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS, + Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX, + Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault." + "Valid range: 0x0 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX, + Help "Enable SATA Port HotPlug." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX, + Help "Enable SATA Port Interlock Sw." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX, + Help "Enable SATA Port External." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX, + Help "Enable the COMRESET initialization Sequence to the device." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX, + Help "0: HDD; 1: SSD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX, + Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX, + Help "DITO multiplier. Default is 15." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspm, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspm, + Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX, + Help "DEVSLP Idle Timeout (DITO), Default is 625." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX, + Help "Support zero power ODD." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Alternate Id", &EN_DIS, + Help "Enable RAID Alternate ID." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX, + Help "Enable Intel RST for PCIe Storage remapping." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX, + Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)." + "Valid range: 0x00 ~ 0xFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX, + Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms" + "Valid range: 0x00 ~ 0xFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsEnable, "UFS enable/disable", &EN_DIS, + Help "Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller 0 and (0,1) to enable controller 1" + Combo $gPlatformFspPkgTokenSpaceGuid_UfsInlineEncryption, "UFS Inline Encryption enable/disable", &EN_DIS, + Help "Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0) to enable Inline Encryption for controller 0 and (0,1) to enable Inline Encryption for controller 1 " + Combo $gPlatformFspPkgTokenSpaceGuid_IehMode, "IEH Mode", &gPlatformFspPkgTokenSpaceGuid_IehMode, + Help "Integrated Error Handler Mode, 0: Bypass, 1: Enable" + Combo $gPlatformFspPkgTokenSpaceGuid_SocTTSuggestedSetting, "SOC Thermal Throttling Suggested Setting", &EN_DIS, + Help "Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels are ignored but with native settings." + EditNum $gPlatformFspPkgTokenSpaceGuid_SocT0Level, "SOC Thermal Throttling Custimized T0Level Value", HEX, + Help "Custimized T0Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SocT1Level, "SOC Thermal Throttling Custimized T1Level Value", HEX, + Help "Custimized T1Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SocT2Level, "SOC Thermal Throttling Custimized T2Level Value", HEX, + Help "Custimized T2Level value." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SocTTEnable, "Enable SOC Thermal Throttle", &EN_DIS, + Help "Enable thermal throttle function." + Combo $gPlatformFspPkgTokenSpaceGuid_SocTTState13Enable, "SOC PMSync State 13", &EN_DIS, + Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." + Combo $gPlatformFspPkgTokenSpaceGuid_SocTTLock, "SOC Thermal Throttle Lock", &EN_DIS, + Help "Thermal Throttle Lock." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTSuggestedSetting, "PCH Thermal Throttling Suggested Setting", &EN_DIS, + Help "Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels are ignored but with native settings." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "PCH Thermal Throttling Custimized T0Level Value", HEX, + Help "Custimized T0Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "PCH Thermal Throttling Custimized T1Level Value", HEX, + Help "Custimized T1Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "PCH Thermal Throttling Custimized T2Level Value", HEX, + Help "Custimized T2Level value." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable PCH Thermal Throttle", &EN_DIS, + Help "Enable thermal throttle function." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PCH PMSync State 13", &EN_DIS, + Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state." + Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "PCH Thermal Throttle Lock", &EN_DIS, + Help "Thermal Throttle Lock." + Combo $gPlatformFspPkgTokenSpaceGuid_IoeTTSuggestedSetting, "IOE Thermal Throttling Suggested Setting", &EN_DIS, + Help "IOE Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels are ignored but with native settings." + EditNum $gPlatformFspPkgTokenSpaceGuid_IoeT0Level, "IOE Thermal Throttling Custimized T0Level Value", HEX, + Help "Custimized IOE T0Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IoeT1Level, "IOE Thermal Throttling Custimized T1Level Value", HEX, + Help "Custimized IOE T1Level value." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_IoeT2Level, "IOE Thermal Throttling Custimized T2Level Value", HEX, + Help "Custimized IOE T2Level value." + "Valid range: 0x00 ~ 0xFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_IoeTTEnable, "Enable IOE Thermal Throttle", &EN_DIS, + Help "Enable thermal throttle function." + Combo $gPlatformFspPkgTokenSpaceGuid_IoeTTLock, "IOE Thermal Throttle Lock", &EN_DIS, + Help "Thermal Throttle Lock." + Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS, + Help "DMI Thermal Sensor Autonomous Width Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS, + Help "DMT thermal sensor suggested representative values." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, + Help "Thermal Sensor 0 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, + Help "Thermal Sensor 1 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, + Help "Thermal Sensor 2 Target Width." + Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, + Help "Thermal Sensor 3 Target Width." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX, + Help "Port 0 T1 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX, + Help "Port 0 T2 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX, + Help "Port 0 T3 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX, + Help "Port 0 Tdispatch." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX, + Help "Port 1 T1 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX, + Help "Port 1 T2 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX, + Help "Port 1 T3 Multipler." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX, + Help "Port 1 Tdispatch." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX, + Help "Port 0 Tinactive." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS, + Help "Port 0 Alternate Fast Init Tdispatch." + EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX, + Help "Port 1 Tinactive." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS, + Help "Port 1 Alternate Fast Init Tdispatch." + Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS, + Help "Sata Thermal Throttling Suggested Setting." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX, + Help "Decides the temperature." + "Valid range: 0x00 ~ 0xFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 2.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX, + Help "Describe the specific over current pin number of USB 3.0 Port N." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS, + Help "Enables override of recommended LTR values for xHCI" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX, + Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting" + "Valid range: 0x00 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS, + Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled." + Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS, + Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming." + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS, + Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS." + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX, + Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port." + "Valid range: 0x00 ~ 0x01010101010101010101" + EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX, + Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, + Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE" + Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS, + Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices" + Combo $gPlatformFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS, + Help "Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable." + Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, + Help "0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved" + Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS, + Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable" + Combo $gPlatformFspPkgTokenSpaceGuid_CseDataResilience, "CSE Data Resilience Support", &EN_DIS, + Help "0: Disable CSE Data Resilience Support. 1: Enable CSE Data Resilience Support." + Combo $gPlatformFspPkgTokenSpaceGuid_MePostMemRsvd, "MePostMemRsvd", &EN_DIS, + Help "Reserved for ME Post-Mem" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS, + Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit." + Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS, + Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register." + Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS, + Help "Force all GPIO pads to be unlocked for debug purpose." + Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS, + Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access." + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX, + Help "Latency Tolerance Reporting, Max Non-Snoop Latency." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX, + Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX, + Help "Specifies scale used for slot power limit value. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX, + Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS, + Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable." + EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX, + Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)." + "Valid range: 0x0 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS, + Help "Disable/Enable PCH to CPU energy report feature." + Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS, + Help "Allow entrance to the PCH SATA test modes." + Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS, + Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked." + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask, "Low Power Mode Enable/Disable config mask", HEX, + Help "Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4." + "Valid range: 0x00 ~ 0xFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPchLpmS0ixSubStateEnableMask, "Low Power Mode Enable/Disable config mask", HEX, + Help "Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4." + "Valid range: 0x00 ~ 0xFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PchPmErDebugMode, "PCH PMC ER Debug mode", &EN_DIS, + Help "Disable/Enable Energy Reporting Debug Mode." + Combo $gPlatformFspPkgTokenSpaceGuid_CppmFaEn, "CPPM Forced Alignment Enable", &EN_DIS, + Help "Enable/Disable CPPM Force Alignment. When enabled, PMC allows stalling of the backbone or blocking the DMI transmit arbiter" + Combo $gPlatformFspPkgTokenSpaceGuid_PchLanWOLFastSupport, "PCH Lan WOL Fast Support", &EN_DIS, + Help "Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm." + Combo $gPlatformFspPkgTokenSpaceGuid_PlatformAtxTelemetryUnit, "Platform ATX Telemetry Unit", &EN_DIS, + Help "Set ATX Telemetry Unit in Watts or Percentage; 0: Watts; 1: Percent" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrOverrideSpecComplaint, "PCIE RP LTR Override Spec Complaint", HEX, + Help "Override LTR based on Ep capability." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_PmcC10DynamicThresholdAdjustment, "PMC C10 dynamic threshold dajustment enable", &EN_DIS, + Help "Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs" + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitRatio, "Turbo Ratio Limit Ratio array", HEX, + Help "Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio Limit Ratio0 must be greater than or equal all other ratio values. If this value is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit Ratio1 must be <= to Turbo Ratio Limit Ratio0~6." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_TurboRatioLimitNumCore, "Turbo Ratio Limit Num Core array", HEX, + Help "Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitRatio, "ATOM Turbo Ratio Limit Ratio array", HEX, + Help "Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective of the core extension mode), the core range is defined in E-core Turbo Ratio Limit CoreCount0-7." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_AtomTurboRatioLimitNumCore, "ATOM Turbo Ratio Limit Num Core array", HEX, + Help "Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry is ignored." + "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF" + EditNum $gPlatformFspPkgTokenSpaceGuid_FspEventHandler, "FspEventHandler", HEX, + Help "Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER." + "Valid range: 0x0 ~ 0xFFFFFFFF" + Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcssCovTypeA, "Type C Port x Convert to TypeA", &EN_DIS, + Help "Enable / Disable(default) Type C Port x Convert to TypeA" +EndPage + diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.fd b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.fd new file mode 100644 index 00000000..eceb7c9d --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Fsp.fd @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3a5ce17d450e2f7177e54cd5e7bfc14990f6ea3a14cfa6ccb0ac1fe73a745632 +size 1310720 diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc new file mode 100644 index 00000000..0c4e550a --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc @@ -0,0 +1,118 @@ +## @file +# Platform description for DynamicEx PCDs, defined in FSP Package +# and shared with Board Package. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright 2018 - 2021 Intel Corporation. +# +# The source code contained or described herein and all documents related to the +# source code ("Material") are owned by Intel Corporation or its suppliers or +# licensors. Title to the Material remains with Intel Corporation or its suppliers +# and licensors. The Material may contain trade secrets and proprietary and +# confidential information of Intel Corporation and its suppliers and licensors, +# and is protected by worldwide copyright and trade secret laws and treaty +# provisions. No part of the Material may be used, copied, reproduced, modified, +# published, uploaded, posted, transmitted, distributed, or disclosed in any way +# without Intel's prior express written permission. +# +# No license under any patent, copyright, trade secret or other intellectual +# property right is granted to or conferred upon you by disclosure or delivery +# of the Materials, either expressly, by implication, inducement, estoppel or +# otherwise. Any license under such intellectual property rights must be +# express and approved by Intel in writing. +# +# Unless otherwise agreed by Intel in writing, you may not remove or alter +# this notice or any other notice embedded in Materials by Intel or +# Intel's suppliers or licensors in any way. +# +# This file contains an 'Intel Peripheral Driver' and is uniquely identified as +# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under +# the terms of your license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the license agreement. +# +# @par Specification +## + +[PcdsDynamicExDefault] + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 + + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000 + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + + !if gSiPkgTokenSpaceGuid.PcdEmbeddedEnable == 0x1 + gSiPkgTokenSpaceGuid.PcdI2cPostCode|0x0 + !endif + + ## Specifies the base address of the first microcode Patch in the microcode Region. + # @Prompt Microcode Region base address. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + + ## Specifies the AP target C-state for Mwait during POST phase. + # The default value 0 means C1 state. + # The value is defined as below.

+ # @Prompt The specified AP target C-state for Mwait. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + + # + # Enable ACPI S3 support in FSP by default + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1 + + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. + # @Prompt The pointer to a CPU S3 data buffer. + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00 + + ## As input, specifies user's desired settings for enabling/disabling processor features. + ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature. + # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + ## Contains the size of memory required when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The memory size used for processor trace if processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0 + + ## Contains the processor trace output scheme when CPU processor trace is enabled.

+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.

+ # @Prompt The processor trace output scheme used when processor trace is enabled. + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0 + + ## Indicates processor feature capabilities, each bit corresponding to a specific feature. + # @Prompt Processor feature capabilities. + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + + # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + + ## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Data pointer. + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0 + + ## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Smm Data pointer. + # @ValidList 0x80000001 | 0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0 \ No newline at end of file diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FirmwareVersionInfo.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FirmwareVersionInfo.h new file mode 100644 index 00000000..466cb8e7 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FirmwareVersionInfo.h @@ -0,0 +1,55 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspProducerDataHeader.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspProducerDataHeader.h new file mode 100644 index 00000000..90292964 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspProducerDataHeader.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspUpd.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspUpd.h new file mode 100644 index 00000000..0028bdef --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2025, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */ + +#pragma pack() + +#endif diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspmUpd.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspmUpd.h new file mode 100644 index 00000000..8e7068a7 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspmUpd.h @@ -0,0 +1,5394 @@ +/** @file + +Copyright (c) 2025, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Enable above 4GB MMIO resource support + DEPRECATED. Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x004B - Ibecc Ec Dis + This option enables or disables the Ibecc Control register Ec Dis field. Default + 0 = Enabled. + $EN_DIS +**/ + UINT8 IbeccEcDis; + +/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr000; + +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr001; + +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr010; + +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr011; + +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr020; + +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr021; + +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr030; + +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr031; + +/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr100; + +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr101; + +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr110; + +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr111; + +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr120; + +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr121; + +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr130; + +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr131; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x012A - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x012B - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x012C - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x012D - RxVrefTempCoeff + Default = 6. Range from 0-255 +**/ + UINT8 RxVrefTempCoeff; + +/** Offset 0x012E - CaParityPatternRotation + Default = 0 (Auto). 1 for High stress pattern rotation, 2 for no rotation. +**/ + UINT8 CaParityPatternRotation; + +/** Offset 0x012F - WCK Offset + This option enables the WCK Offset WA for Hynix32 with freq >= 5600. + $EN_DIS +**/ + UINT8 WckOffsetWa; + +/** Offset 0x0130 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0134 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x0136 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x0137 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0138 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0148 - Platform Debug Consent + Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n + \n + Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n + \n + Enabled Trace power off: TraceHub is powergated, provide setting close to functional + low power state\n + \n + Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual +**/ + UINT8 PlatformDebugOption; + +/** Offset 0x0149 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x014A - DCI Clock Enable + Enable/Disable DCI clock in lowest power state + $EN_DIS +**/ + UINT8 DciClkEnable; + +/** Offset 0x014B - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x014C - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x014D - SOC Trace Hub Mode + Enable/Disable SOC TraceHub + $EN_DIS +**/ + UINT8 SocTraceHubMode; + +/** Offset 0x014E - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg0Size; + +/** Offset 0x0150 - SOC Trace Hub Memory Region 1 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg1Size; + +/** Offset 0x0152 - Keep Early Trace + Trace is activated by default. When enable, keep early trace data and keep tracing, + may block s0ix.\n + When disabled will abandon trace data and stop tracing which allows enter s0ix\n + \n + noted:enable this option will not enable TraceHub; When probe is connected, keep + early trace will then be configured by tool, this option will not take effect. + $EN_DIS +**/ + UINT8 KeepEarlyTrace; + +/** Offset 0x0153 - PCH Trace Hub Mode + Enable/Disable PCH TraceHub + $EN_DIS +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0154 - PCH Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg0Size; + +/** Offset 0x0156 - PCH Trace Hub Memory Region 1 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg1Size; + +/** Offset 0x0158 - IOE Debug Enable + Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock + is enabled + $EN_DIS +**/ + UINT8 IoeDebugEn; + +/** Offset 0x0159 - Pmode Clock Enable + Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use + $EN_DIS +**/ + UINT8 PmodeClkEn; + +/** Offset 0x015A - AET Trace Hub Mode Select + Select AET to Trace Hub destination. + 0:SOC Trace Hub, 1:PCH Trace Hub +**/ + UINT8 AetTraceHubMode; + +/** Offset 0x015B - BIOS trace destination + Select BIOS trace destination. + 0:SOC Trace Hub, 1:PCH Trace Hub +**/ + UINT8 BiosTraceSinkMode; + +/** Offset 0x015C - HD Audio DMIC Link Clock Select + Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB +**/ + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x015F - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x0160 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x0184 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0185 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x0186 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x0187 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, + 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, + 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x0188 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x0189 - Oem T12 Dealy Override + Oem T12 Dealy Override. 0(Default)=Disable 1=Enable + $EN_DIS +**/ + UINT8 OemT12DelayOverride; + +/** Offset 0x018A - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x018B - MRC Retraining on RTC Power Loss + Specifies whether MRC memory training will occur when RTC power loss is detected. + Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory + will not be re-trained when RTC power loss is detected. (Typically used on board + designs without a dedicated RTC battery) + 0:Disabled, 1:Enabled +**/ + UINT8 DisableMrcRetrainingOnRtcPowerLoss; + +/** Offset 0x018C - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x018E - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x018F - SAGV WP Mask + System Agent dynamic frequency workpoints that memory will be training at the enabled + frequencies. + 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 +**/ + UINT8 SaGvWpMask; + +/** Offset 0x0190 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x0191 - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x0192 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x0193 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x0194 - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x0195 - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x0196 - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x0197 - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x0198 - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x0199 - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x019A - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x019B - SPD Profile Selected + Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, + 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP + User Profile 5 + 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP + Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x019C - Dynamic Memory Boost + 0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile, + and also the profile selected by SpdProfileSelected, to allow automatic switching + during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored. + $EN_DIS +**/ + UINT8 DynamicMemoryBoost; + +/** Offset 0x019D - Realtime Memory Frequency + 0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is XMP Profile + 1. If enabled, MRC will train the Default SPD Profile, and also XMP Profile 1, + to allow manually triggered switching between frequencies at runtime. + $EN_DIS +**/ + UINT8 RealtimeMemoryFrequency; + +/** Offset 0x019E - OC Safe Mode + Bitmap: Ignored unless SpdProfileSelected is an XMP Profile. Bit 0: Use safe tCL, + Bit 1: Limit tWR, tRTP, tCCD_L, tCCD_L_WR, tCL to of freq 6400 when programming + Dimm MR if DIMM doesn't support new spec. + $EN_DIS +**/ + UINT8 OCSafeMode; + +/** Offset 0x019F - tRRSG Delta + Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRSG; + +/** Offset 0x01A0 - tRRDG Delta + Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRRDG; + +/** Offset 0x01A1 - tRRDR Delta + Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDR; + +/** Offset 0x01A2 - tRRDD Delta + Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRRDD; + +/** Offset 0x01A3 - tWRSG Delta + Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRSG; + +/** Offset 0x01A4 - tWRDG Delta + Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWRDG; + +/** Offset 0x01A5 - tWRDR Delta + Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDR; + +/** Offset 0x01A6 - tWRDD Delta + Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWRDD; + +/** Offset 0x01A7 - tWWSG Delta + Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tWWSG; + +/** Offset 0x01A8 - tWWDG Delta + Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed + TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta + range of [-127..127] +**/ + UINT8 tWWDG; + +/** Offset 0x01A9 - tWWDR Delta + Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDR; + +/** Offset 0x01AA - tWWDD Delta + Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tWWDD; + +/** Offset 0x01AB - tRWSG Delta + Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWSG; + +/** Offset 0x01AC - tRWDG Delta + Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT + delta is (Value - 128). Input value range of [0..255] will give a TAT delta range + of [-127..127] +**/ + UINT8 tRWDG; + +/** Offset 0x01AD - tRWDR Delta + Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDR; + +/** Offset 0x01AE - tRWDD Delta + Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta + is (Value - 128). Input value range of [0..255] will give a TAT delta range of + [-127..127] +**/ + UINT8 tRWDD; + +/** Offset 0x01AF +**/ + UINT8 Rsvd031[1]; + +/** Offset 0x01B0 - tREFI32 + Refresh Interval, 0: AUTO, max: 131071. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT32 tREFI32; + +/** Offset 0x01B4 - Config BitMask to limit max freq at 3200 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit3200Mask; + +/** Offset 0x01B6 - Config BitMask to limit max freq at 3600 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit3600Mask; + +/** Offset 0x01B8 - Config BitMask to limit max freq at 4000 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit4000Mask; + +/** Offset 0x01BA - Config BitMask to limit max freq at 4400 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit4400Mask; + +/** Offset 0x01BC - Config BitMask to limit max freq at 4800 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit4800Mask; + +/** Offset 0x01BE - Config BitMask to limit max freq at 5200 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit5200Mask; + +/** Offset 0x01C0 - Config BitMask to limit max freq at 5600 + BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB, + BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB, + BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB, + BIT12: 2R2R_32GB_48GB +**/ + UINT16 FreqLimit5600Mask; + +/** Offset 0x01C2 - 2DPC Enhanced Frequency Limit + Enable/Disable Enhanced FreqLimit for 2DPC + $EN_DIS +**/ + UINT8 FreqLimitMaskEn; + +/** Offset 0x01C3 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x01C4 - Initial DDR5 TxVref Override + Override for initial DDR5 TxVref value , 0 = Auto (default), valid range from 350 + to 975, in increments of 5 +**/ + UINT16 TxVrefOverride; + +/** Offset 0x01C6 - Force CKD in Bypass Mode + Enable/Disable Force CKD in Bypass Mode + $EN_DIS +**/ + UINT8 IsForceCkdBypass; + +/** Offset 0x01C7 +**/ + UINT8 Rsvd036[58]; + +/** Offset 0x0201 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0202 - Vdd2Mv + VDD2 in MilliVolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1350:1.35 Volts ... +**/ + UINT16 Vdd2Mv; + +/** Offset 0x0204 - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x0205 +**/ + UINT8 Rsvd032[1]; + +/** Offset 0x0206 - Safe Loading Bios Enable State + 0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for + TSEG Region. + $EN_DIS +**/ + UINT8 SafeLoadingBiosEnableState; + +/** Offset 0x0207 - Ppr Recovery Status Enable + 0: Disabled(Default), 1: Enabled. If enabled, PPR Recovery flow will get Trigger. + $EN_DIS +**/ + UINT8 PprRecoveryStatusEnable; + +/** Offset 0x0208 - Tseg Memory Test Status + If enabled, PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 TsegMemoryTestStatus; + +/** Offset 0x0209 - Mrc Ppr Status + Get Mrc PPR Status after PPR Recovery flow will get Trigger + 0: PASS, 1: FAIL(Default) +**/ + UINT8 MrcPprStatus; + +/** Offset 0x020A - Tseg Retry Count + Tseg Retry count will increase based on TSEG Region Fail count + 0: Default, 1:3 +**/ + UINT8 RetryCount; + +/** Offset 0x020B +**/ + UINT8 Rsvd035[3]; + +/** Offset 0x020E - Memory Vdd Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x0210 - Memory VDDQ Voltage + DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts + from 0 - default to 1435mv. +**/ + UINT16 VddqVoltage; + +/** Offset 0x0212 - Memory VPP Voltage + DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from + 0 - default to 2135mv. +**/ + UINT16 VppVoltage; + +/** Offset 0x0214 - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT16 Ratio; + +/** Offset 0x0216 - tCL + CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCL; + +/** Offset 0x0217 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCWL; + +/** Offset 0x0218 - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tFAW; + +/** Offset 0x021A - tRAS + RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRAS; + +/** Offset 0x021C - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRCDtRP; + +/** Offset 0x021D +**/ + UINT8 Rsvd040[1]; + +/** Offset 0x021E - tREFI + Obsolete, use tREFI32 instead. Refresh Interval, 0: AUTO, max: 65535. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tREFI; + +/** Offset 0x0220 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC; + +/** Offset 0x0222 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRRD; + +/** Offset 0x0223 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRTP; + +/** Offset 0x0224 - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x0225 - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tWTR; + +/** Offset 0x0226 - tRFCpb + Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tRFCpb; + +/** Offset 0x0228 - tRFC2 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC2; + +/** Offset 0x022A - tRFC4 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC4; + +/** Offset 0x022C - tRRD_L + Min Internal row active to row active delay time for same bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_L; + +/** Offset 0x022D - tRRD_S + Min Internal row active to row active delay time for different bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_S; + +/** Offset 0x022E - tWTR_L + Min Internal write to read command delay time for same bank groups, 0: AUTO, max: + 127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_L; + +/** Offset 0x022F - tCCD_L + Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if + FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tCCD_L; + +/** Offset 0x0230 - tCCD_L_WR + Min Internal Write-to-Write delay for same bank group, 0: AUTO, max: 150. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tCCD_L_WR; + +/** Offset 0x0231 - tWTR_S + Min Internal write to read command delay time for different bank groups, 0: AUTO, + max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_S; + +/** Offset 0x0232 - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x0233 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x0234 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x0235 - Dimm DFE Tap1 Step Size Setting + Dimm DFE Tap1 setting: Memory-dependent, positive value will be converted to minus + values by *-1 automatically +**/ + UINT8 DFETap1StepSize; + +/** Offset 0x0236 - Dimm DFE Tap2 Step Size Setting + Dimm DFE Tap2 setting: Memory-dependent, positive value will be converted to minus + values by *-1 automatically +**/ + UINT8 DFETap2StepSize; + +/** Offset 0x0237 +**/ + UINT8 Rsvd041[5]; + +/** Offset 0x023C - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x0240 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x0248 - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 2-Gear 2, 2-Gear 4 +**/ + UINT8 GearRatio; + +/** Offset 0x0249 - LPDDR ODT RttWr + Initial RttWr for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttWr; + +/** Offset 0x024A - LPDDR ODT RttCa + Initial RttCa for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttCa; + +/** Offset 0x024B - Dimm Odt settings + Dimm Odt settings of 2 DIMMs of a channel: Memory-dependent, 0: AUTO, max: 0xFFFF + meaning disabling +**/ + UINT8 DimmOdt[44]; + +/** Offset 0x0277 - Dimm DFE Tap1 settings Deprecated + Dimm DFE Tap1 settings: Memory-dependent, positive values will be converted to minus + values by *-1 automatically +**/ + UINT8 DFETap1[8]; + +/** Offset 0x027F - Dimm DFE Tap2 settings Deprecated + Dimm DFE Tap2 settings: Memory-dependent, positive values will be converted to minus + values by *-1 automatically +**/ + UINT8 DFETap2[8]; + +/** Offset 0x0287 - CsVrefLow + DDR5 Cs Sweep Low Vref Value, 0: AUTO, max: 125. +**/ + UINT8 CsVrefLow; + +/** Offset 0x0288 - CsVrefHigh + DDR5 Cs Sweep High Vref Value, 0: AUTO, max: 125. +**/ + UINT8 CsVrefHigh; + +/** Offset 0x0289 - CaVrefLow + DDR5 Ca Sweep Low Vref Value, 0: AUTO, max: 125. +**/ + UINT8 CaVrefLow; + +/** Offset 0x028A - CaVrefHigh + DDR5 Ca Sweep High Vref Value, 0: AUTO, max: 125. +**/ + UINT8 CaVrefHigh; + +/** Offset 0x028B +**/ + UINT8 Rsvd050[1]; + +/** Offset 0x028C - RxVrefOffset + DDR5 RxVref Offset Value, 0: AUTO, max: 1600. +**/ + UINT16 RxVrefOffset; + +/** Offset 0x028E - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x0290 - Selection of the primary display device + 0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0291 - Internal Graphics Data Stolen Memory GSM2 + Size of memory preallocated for internal graphics GSM2. + 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, + 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation +**/ + UINT8 IgdGsm2Size; + +/** Offset 0x0292 +**/ + UINT8 UnusedUpdSpace2[2]; + +/** Offset 0x0294 - Temporary MMIO address for GMADR + Obsolete field now and it has been extended to 64 bit address, used LMemBar +**/ + UINT32 GmAdr; + +/** Offset 0x0298 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x029C - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x029D - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x029E - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x029F - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x02A0 - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x02A2 - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x02A4 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtAdaptiveVoltage; + +/** Offset 0x02A6 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x02A8 - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x02A9 - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x02AA +**/ + UINT8 Rsvd065; + +/** Offset 0x02AB - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x02AC - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x02B2 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x02B3 - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x02B4 - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x02B5 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x02B6 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x02B7 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x02B8 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x02B9 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x02BA - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x02BB - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x02BC - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x02BD - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x02BE - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x02BF - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x02C0 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x02C1 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x02C2 - GPIO PIN MUX to choose between GPP_SA and GPP_SD Group. + Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP, + 1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3 + - DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4 +**/ + UINT8 DisplayGpioPinMux; + +/** Offset 0x02C3 - FrameBuffer via DSM or LMem, when FrameBuffer is pointing to DSM region this option should be enabled + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 ConfigureDsmMtrr; + +/** Offset 0x02C4 +**/ + UINT8 Rsvd070[8]; + +/** Offset 0x02CC +**/ + UINT8 UnusedUpdSpace3[4]; + +/** Offset 0x02D0 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1) +**/ + UINT64 LMemBar; + +/** Offset 0x02D8 - Per-core HT Disable + Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, + 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value + of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have + HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. +**/ + UINT16 PerCoreHtDisable; + +/** Offset 0x02DA - SA/Uncore voltage mode + SA/Uncore voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 SaVoltageMode; + +/** Offset 0x02DB +**/ + UINT8 Rsvd080[1]; + +/** Offset 0x02DC - SA/Uncore Voltage Override + The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override + mode. Valid Range 0 to 2000 +**/ + UINT16 SaVoltageOverride; + +/** Offset 0x02DE - SA/Uncore Adaptive voltage + Adaptive voltage applicable when SA/Uncore voltage mode is in Adaptive mode. Valid + Range 0 to 2000 +**/ + UINT16 SaAdaptiveVoltage; + +/** Offset 0x02E0 - Thermal Velocity Boost Ratio clipping + 0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction + caused by high package temperatures for processors that implement the Intel Thermal + Velocity Boost (TVB) feature + $EN_DIS +**/ + UINT8 TvbRatioClipping; + +/** Offset 0x02E1 - Thermal Velocity Boost voltage optimization + 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations + for processors that implement the Intel Thermal Velocity Boost (TVB) feature. + $EN_DIS +**/ + UINT8 TvbVoltageOptimization; + +/** Offset 0x02E2 - PCIE Resizable BAR Support + Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default). + $EN_DIS +**/ + UINT8 PcieResizableBarSupport; + +/** Offset 0x02E3 - PCH DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane +**/ + UINT8 PchDmiGen4RootPortPreset[8]; + +/** Offset 0x02EB - SaPreMemProductionRsvd + Reserved for SA Pre-Mem Production + $EN_DIS +**/ + UINT8 SaPreMemProductionRsvd[36]; + +/** Offset 0x030F - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0310 - PCH DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 PchDmiGen3EqPh2Enable; + +/** Offset 0x0311 - PCH DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 PchDmiGen3EqPh3Method; + +/** Offset 0x0312 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x0313 - PCH DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane +**/ + UINT8 PchDmiGen3RootPortPreset[8]; + +/** Offset 0x031B - PCH DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 PchDmiGen3EndPointPreset[8]; + +/** Offset 0x0323 - PCH DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 PchDmiGen3EndPointHint[8]; + +/** Offset 0x032B - DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x032C - PCH DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 PchDmiAspm; + +/** Offset 0x032D - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): + Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x032E - Enable/Disable DMI GEN3 Phase 23 Bypass + DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase23Bypass; + +/** Offset 0x032F - Enable/Disable DMI GEN3 Phase 3 Bypass + DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase3Bypass; + +/** Offset 0x0330 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local + Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen3LtcoEnable; + +/** Offset 0x0331 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x0332 - DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 DmiGen3Ltcpre[8]; + +/** Offset 0x033A - DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 DmiGen3Ltcpo[8]; + +/** Offset 0x0342 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local + Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 PchDmiGen3LtcoEnable; + +/** Offset 0x0343 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 PchDmiGen3RtcoRtpoEnable; + +/** Offset 0x0344 - PCH DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 PchDmiGen3Ltcpre[8]; + +/** Offset 0x034C - PCH DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 PchDmiGen3Ltcpo[8]; + +/** Offset 0x0354 - PCIE Hw Eq Gen3 CoeffList Cm + DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 DmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x035C - PCIE Hw Eq Gen3 CoeffList Cp + DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 DmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0364 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable + Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, + Manual(0x1): Enable DmiGen3DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3DsPresetEnable; + +/** Offset 0x0365 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3DsPortRxPreset[8]; + +/** Offset 0x036D - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3DsPortTxPreset[8]; + +/** Offset 0x0375 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable + Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, + Manual(0x1): Enable DmiGen3UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3UsPresetEnable; + +/** Offset 0x0376 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortRxPreset[8]; + +/** Offset 0x037E - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3UsPortTxPreset[8]; + +/** Offset 0x0386 - DMI Hw Eq Gen4 CoeffList Cm + DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 DmiHwEqGen4CoeffListCm[8]; + +/** Offset 0x038E - DMI Hw Eq Gen4 CoeffList Cp + DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 DmiHwEqGen4CoeffListCp[8]; + +/** Offset 0x0396 - Enable/Disable DMI GEN4 Phase 23 Bypass + DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase23Bypass; + +/** Offset 0x0397 - Enable/Disable DMI GEN4 Phase 3 Bypass + DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase3Bypass; + +/** Offset 0x0398 - Enable/Disable DMI GEN4 DmiGen4DsPresetEnable + Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable, + Manual(0x1): Enable DmiGen4DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4DsPresetEnable; + +/** Offset 0x0399 - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen4DsPortTxPreset[8]; + +/** Offset 0x03A1 - Enable/Disable DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen4RtcoRtpoEnable; + +/** Offset 0x03A2 - Enable/Disable DMI Gen4 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen4LtcoEnable; + +/** Offset 0x03A3 - DMI Gen4 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 0 is default for each lane +**/ + UINT8 DmiGen4Ltcpre[8]; + +/** Offset 0x03AB - DMI Gen4 Transmitter Post-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8 + is default for each lane +**/ + UINT8 DmiGen4Ltcpo[8]; + +/** Offset 0x03B3 - Enable/Disable DMI GEN4 DmiGen4UsPresetEnable + Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable, + Manual(0x1): Enable DmiGen4UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4UsPresetEnable; + +/** Offset 0x03B4 - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen4UsPortTxPreset[8]; + +/** Offset 0x03BC - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x03BD - Enable/Disable PCH DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 PchDmiGen4RtcoRtpoEnable; + +/** Offset 0x03BE - Enable/Disable PCH DMI Gen4 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 PchDmiGen4LtcoEnable; + +/** Offset 0x03BF - PCH DMI Gen4 Transmitter Post-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8 + is default for each lane +**/ + UINT8 PchDmiGen4Ltcpo[8]; + +/** Offset 0x03C7 - PCH DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 PchDmiAspmL1ExitLatency; + +/** Offset 0x03C8 - PCH DMI Gen4 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 0 is default for each lane +**/ + UINT8 PchDmiGen4Ltcpre[8]; + +/** Offset 0x03D0 - L1SS State Control Policy + Choose the L1SS State Control Policy, Default = 0 + 0: Auto, 1: L1.2 +**/ + UINT8 DmiL1ssEnable; + +/** Offset 0x03D1 +**/ + UINT8 Rsvd085[7]; + +/** Offset 0x03D8 - Temporary address for NvmeHcPeiMmioBase + The reference code will use this as Temporary address space +**/ + UINT32 NvmeHcPeiMmioBase; + +/** Offset 0x03DC - Temporary address for NvmeHcPeiMmioLimit + The reference code will use this as Temporary address space +**/ + UINT32 NvmeHcPeiMmioLimit; + +/** Offset 0x03E0 - Temporary address for AhciPeiMmioBase + The reference code will use this as Temporary address space +**/ + UINT32 AhciPeiMmioBase; + +/** Offset 0x03E4 - Temporary address for AhciPeiMmioLimit + The reference code will use this as Temporary address space +**/ + UINT32 AhciPeiMmioLimit; + +/** Offset 0x03E8 - Temporary address for EcExtraIoBase + The reference code will use this as Temporary address space +**/ + UINT16 EcExtraIoBase; + +/** Offset 0x03EA - Temporary address for SioBaseAddress + The reference code will use this as Temporary address space +**/ + UINT16 SioBaseAddress; + +/** Offset 0x03EC - Temporary address for ApicLocalAddress + The reference code will use this as Temporary address space +**/ + UINT32 ApicLocalAddress; + +/** Offset 0x03F0 - Temporary CfgBar address for VMD + The reference code will use this as Temporary address space +**/ + UINT32 VmdCfgBarBar; + +/** Offset 0x03F4 - Temporary MemBar1 address for VMD + The reference code will use this as Temporary address space +**/ + UINT32 VmdMemBar1Bar; + +/** Offset 0x03F8 - Temporary MemBar2 address for VMD + The reference code will use this as Temporary address space +**/ + UINT32 VmdMemBar2Bar; + +/** Offset 0x03FC - BIST on Reset + Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x03FD - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x03FE - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x03FF - Over clocking Lock + Lock Overclocking. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x0400 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 if CoreRatioExtensionMode + is disabled. 0-120 if CoreRatioExtensionMode is enabled. +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x0401 - Core voltage mode + Core voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x0402 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x0403 - Hyper Threading Enable/Disable + Enable or Disable Hyper-Threading Technology. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0404 - Enable or Disable CPU Ratio Override + Enable/Disable CPU Flex Ratio Programming; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuRatioOverride; + +/** Offset 0x0405 - CPU ratio value + This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio + set by Hardware (HFM). Valid Range 0 to 63. +**/ + UINT8 CpuRatio; + +/** Offset 0x0406 - Boot max frequency + Enable Boot Maximum Frequency in CPU strap. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BootMaxFrequency; + +/** Offset 0x0407 - Number of active big cores + Number of P-cores to enable in each processor package. Note: Number of P-Cores and + E-Cores are looked at together. When both are {0,0 + 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x0408 - Processor Early Power On Configuration FCLK setting + FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). + 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x0409 - Enable or Disable VMX + Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities + provided by Vanderpool Technology. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x040A - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x040B - AVX3 Ratio Offset + DEPRECATED. 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease + AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x040C - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x040D +**/ + UINT8 Rsvd090[1]; + +/** Offset 0x040E - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x0410 - Core Turbo Adaptive Voltage + Adaptive voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreAdaptiveVoltage; + +/** Offset 0x0412 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x0414 - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x0415 - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x0416 - Ring voltage mode + Ring voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x0417 - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x0418 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x041A - Ring Turbo Adaptive Voltage + Adaptive voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingAdaptiveVoltage; + +/** Offset 0x041C - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x041E - Enable or Disable TME + Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x041F - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x0420 - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x0421 - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x0422 - DFD Enable + Enable or Disable DFD. 0: Disable, 1:Enable + $EN_DIS +**/ + UINT8 DfdEnable; + +/** Offset 0x0423 +**/ + UINT8 Rsvd100[1]; + +/** Offset 0x0424 - Per-Atom-Cluster VF Offset + Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage + is specified in millivolts. +**/ + UINT16 PerAtomClusterVoltageOffset[8]; + +/** Offset 0x0434 - Per-Atom-Cluster VF Offset Prefix + Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected + Core; 0: Positive ; 1: Negative. +**/ + UINT8 PerAtomClusterVoltageOffsetPrefix[8]; + +/** Offset 0x043C - Per-Atom-Cluster Voltage Mode + Array used to specifies the selected Atom Core ClusterVoltage Mode. +**/ + UINT8 PerAtomClusterVoltageMode[8]; + +/** Offset 0x0444 - Per-Atom-Cluster Voltage Override + Array used to specifies the selected Atom Core Cluster Voltage Override. +**/ + UINT16 PerAtomClusterVoltageOverride[8]; + +/** Offset 0x0454 - Per-Atom-Cluster Adaptive Voltage + Array used to specifies the selected Atom Core Cluster Adaptive Voltage. +**/ + UINT16 PerAtomClusterAdaptiveVoltage[8]; + +/** Offset 0x0464 - Number of active small cores + Number of E-cores to enable in each processor package. Note: Number of P-Cores and + E-Cores are looked at together. When both are {0,0 + 0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores +**/ + UINT8 ActiveSmallCoreCount; + +/** Offset 0x0465 - Core VF Point Offset Mode + Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 CoreVfPointOffsetMode; + +/** Offset 0x0466 - Core VF Point Offset + Array used to specifies the Core Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x0484 - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x0493 - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x04A2 - Core VF Point Count + Number of supported Core Voltage & Frequency Point Offset +**/ + UINT8 CoreVfPointCount; + +/** Offset 0x04A3 - Core VF Configuration Scope + Alows both all-core VF curve or per-core VF curve configuration; 0: All-core; + 1: Per-core. + 0:All-core, 1:Per-core +**/ + UINT8 CoreVfConfigScope; + +/** Offset 0x04A4 - Per-core VF Offset + Array used to specifies the selected Core Offset Voltage. This voltage is specified + in millivolts. +**/ + UINT16 PerCoreVoltageOffset[8]; + +/** Offset 0x04B4 - Per-core VF Offset Prefix + Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; + 0: Positive ; 1: Negative. +**/ + UINT8 PerCoreVoltageOffsetPrefix[8]; + +/** Offset 0x04BC - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x04BD - Per-core Voltage Mode + Array used to specifies the selected Core Voltage Mode. +**/ + UINT8 PerCoreVoltageMode[8]; + +/** Offset 0x04C5 +**/ + UINT8 Rsvd110[1]; + +/** Offset 0x04C6 - Per-core Voltage Override + Array used to specifies the selected Core Voltage Override. +**/ + UINT16 PerCoreVoltageOverride[8]; + +/** Offset 0x04D6 - Per-core Adaptive Voltage + Array used to specifies the selected Core Adaptive Voltage. +**/ + UINT16 PerCoreAdaptiveVoltage[8]; + +/** Offset 0x04E6 - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[8]; + +/** Offset 0x04EE - OC TVB + Enable/Disable for OC TVB parameter programming using OCMB 0x24/0x25. 0:Disable + ; 1:Enable. + $EN_DIS +**/ + UINT8 OcTvb; + +/** Offset 0x04EF - Pcore TVB Temperature Threshold 0 + Pcore TVB Temp (in degrees C) - Temperature Threshold 0. Running ABOVE this temperature + will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB + ratio clipping is enabled. Default is 70. +**/ + UINT8 PcoreTvbTempThreshold0; + +/** Offset 0x04F0 - Pcore TVB Temperature Threshold 1 + Pcore TVB Temp (in degrees C) - Temperature Threshold 1. Running ABOVE this temperature + will clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB + ratio clipping is enabled. Default is 100. +**/ + UINT8 PcoreTvbTempThreshold1; + +/** Offset 0x04F1 - Ecore TVB Temperature Threshold 0 + Ecore TVB Temp (in degrees C) - Temperature Threshold 0. Running ABOVE this temperature + will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB + ratio clipping is enabled. Default is 70. +**/ + UINT8 EcoreTvbTempThreshold0; + +/** Offset 0x04F2 - Ecore TVB Temperature Threshold 1 + Ecore TVB Temp (in degrees C) - Temperature Threshold 1. Running ABOVE this temperature + will clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB + ratio clipping is enabled. Default is 100. +**/ + UINT8 EcoreTvbTempThreshold1; + +/** Offset 0x04F3 - OC TVB Configuration Limit Selection + Select one of the two OC TVB Configuration limits, between Per CCP Module or Per + P-core Group. 0: Per CCP Module; 1: Per P-core Group. + 0:Per CCP Module, 1:Per P-core Group +**/ + UINT8 TvbConfigLimitSelect; + +/** Offset 0x04F4 - Per Pcore Ratio Down Bin Above T0 + Array for the Per Pcore Down Bins (delta) for Temperature Threshold 0. When running + above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, + when TVB ratio clipping is enabled. Default is 1. +**/ + UINT8 PerPcoreRatioDownBinAboveT0[8]; + +/** Offset 0x04FC - Per Pcore Ratio Down Bin Above T1 + Array for the Per Pcore Down Bins (delta) for Temperature Threshold 1. When running + above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This value, + when TVB ratio clipping is enabled. Default is 2. +**/ + UINT8 PerPcoreRatioDownBinAboveT1[8]; + +/** Offset 0x0504 - Per Pcore Group Ratio Down Bin Above T0 + Array for the Per Pcore Group Down Bins (delta) for Temperature Threshold 0. When + running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This + value, when TVB ratio clipping is enabled. Default is 1. +**/ + UINT8 PerPcoreGrRatioDownBinAboveT0[8]; + +/** Offset 0x050C - Per Pcore Group Ratio Down Bin Above T1 + Array for the Per Pcore Group Down Bins (delta) for Temperature Threshold 1. When + running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This + value, when TVB ratio clipping is enabled. Default is 2. +**/ + UINT8 PerPcoreGrRatioDownBinAboveT1[8]; + +/** Offset 0x0514 - Per Ecore CCP Ratio Down Bin Above T0 + Array for the Per Ecore CCP Down Bins (delta) for Temperature Threshold 0. When + running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This + value, when TVB ratio clipping is enabled. Default is 0. +**/ + UINT8 PerEcoreCcpRatioDownBinAboveT0[8]; + +/** Offset 0x051C - Per Ecore CCP Ratio Down Bin Above T1 + Array for the Per Ecore Group Down Bins (delta) for Temperature Threshold 1. When + running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This + value, when TVB ratio clipping is enabled. Default is 0. +**/ + UINT8 PerEcoreCcpRatioDownBinAboveT1[8]; + +/** Offset 0x0524 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0525 +**/ + UINT8 Rsvd120[3]; + +/** Offset 0x0528 - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x052A - Atom Cluster Max Ratio + Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their + max core ratio will be aligned. +**/ + UINT8 AtomClusterRatio[8]; + +/** Offset 0x0532 - Core Ratio Extension Mode + Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to + enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 CoreRatioExtensionMode; + +/** Offset 0x0533 - Pvd Ratio Threshold for SOC/CPU die + Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio + (P0 to Pn) to select the multiplier so that the output is within the DCO frequency + range. As per the die selected, this threshold is applied to SA and MC/CMI PLL + for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold + is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default. +**/ + UINT8 PvdRatioThreshold[2]; + +/** Offset 0x0535 - Pvd Mode SOC/CPU die + Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock), + 0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 = + div-8 (VCO = 8x Output clock). +**/ + UINT8 PvdMode[2]; + +/** Offset 0x0537 - FLL Overclock Mode + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. +**/ + UINT8 FllOverclockMode; + +/** Offset 0x0538 - Number of Soc-North Atom cores + Number of SOC-North E-cores to enable in SOC North. 0: Disable all Soc-North Atom + cores; 1: 1; 2: 2; 0xFF: Active all Soc-North Atom cores + 0:Disable all Soc-North Atom cores, 1:1, 2:2, 0xFF:Active all cores +**/ + UINT8 ActiveSocNorthAtomCoreCount; + +/** Offset 0x0539 - Ring VF Point Offset Mode + Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 RingVfPointOffsetMode; + +/** Offset 0x053A - Ring VF Point Offset + Array used to specifies the Ring Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 RingVfPointOffset[15]; + +/** Offset 0x0558 - Ring VF Point Offset Prefix + Sets the RingVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. +**/ + UINT8 RingVfPointOffsetPrefix[15]; + +/** Offset 0x0567 - Ring VF Point Ratio + Array for the each selected Ring VF Point to display the ration. +**/ + UINT8 RingVfPointRatio[15]; + +/** Offset 0x0576 - Ring VF Point Count + Number of supported Ring Voltage & Frequency Point Offset +**/ + UINT8 RingVfPointCount; + +/** Offset 0x0577 - Compute Die SSC enable + Enable/Dsiable Compute-Die SSC Configuration. 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 ComputeDieSscEnable; + +/** Offset 0x0578 - Soc Die SSC enable + Enable/Dsiable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 SocDieSscEnable; + +/** Offset 0x0579 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use +**/ + UINT8 GpioOverride; + +/** Offset 0x057A +**/ + UINT8 Rsvd130[10]; + +/** Offset 0x0584 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is + 40Mhz-1000Mhz. +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x0588 - SOC BCLK OC Frequency + SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is + 40Mhz-1000Mhz. +**/ + UINT32 SocBclkOcFrequency; + +/** Offset 0x058C - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x058D +**/ + UINT8 Rsvd140[11]; + +/** Offset 0x0598 - Bitmask of disable cores + Core mask is a bitwise indication of which core should be disabled. 0x00=Default; + Bit 0 - core 0, bit 7 - core 7. +**/ + UINT64 DisablePerCoreMask; + +/** Offset 0x05A0 - Support IA Unlimited ICCMAX + Support IA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 IaIccUnlimitedMode; + +/** Offset 0x05A1 +**/ + UINT8 Rsvd150[1]; + +/** Offset 0x05A2 - IA ICCMAX + IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 + (HW default). Range is 4-2047. +**/ + UINT16 IaIccMax; + +/** Offset 0x05A4 - Support GT Unlimited ICCMAX + Support GT Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 GtIccUnlimitedMode; + +/** Offset 0x05A5 +**/ + UINT8 Rsvd160[1]; + +/** Offset 0x05A6 - GT ICCMAX + GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 + (HW default). Range is 4-2047. +**/ + UINT16 GtIccMax; + +/** Offset 0x05A8 - Support SA Unlimited ICCMAX + Support SA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 SaIccUnlimitedMode; + +/** Offset 0x05A9 +**/ + UINT8 Rsvd161[1]; + +/** Offset 0x05AA - SA ICCMAX + SA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 0 + (HW default). Range is 4-2047. +**/ + UINT16 SaIccMax; + +/** Offset 0x05AC - Memory Subsystem VF Point Offset + Array used to specifies the Memory Subsystem Voltage Offset applied to the each + selected VF Point. This voltage is specified in millivolts. +**/ + UINT16 MemSSVfPointOffset[15]; + +/** Offset 0x05CA - Memory Subsystem VF Point Offset Prefix + Sets the MemSSVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. +**/ + UINT8 MemSSVfPointOffsetPrefix[15]; + +/** Offset 0x05D9 - Memory Subsystem VF Point Ratio + Array for the each selected Memory Subsystem VF Point to display the ration. +**/ + UINT8 MemSSVfPointRatio[15]; + +/** Offset 0x05E8 - Memory Subsystem VF Point Count + Number of supported Memory Subsystem Voltage & Frequency Point Offset +**/ + UINT8 MemSSVfPointCount; + +/** Offset 0x05E9 - VCCSA Boot Voltage + Default: 0: Nominal 1: High Voltage(up to 1.2/1.3V) to support the voltage + needed for VCCSA boot voltage. + 0: Nominal , 1: High Voltage(up to 1.2/1.3V) +**/ + UINT8 VccsaBootVoltageSel; + +/** Offset 0x05EA - CPU D2D ratio setting + 0(Default)=No setting, 15=Minimal, 40=Maximum +**/ + UINT8 CpuD2dRatio; + +/** Offset 0x05EB - CPU Bandgap Reference Mode + Default: 0: Normal 1: Bandgap Bypassed) to support CPU Bandgap Reference Mode. + 0: Normal , 1: Bandgap Bypassed +**/ + UINT8 CpuBandgapRefMode; + +/** Offset 0x05EC - VCCIA Boot Voltage + Default: 0: Nominal 1: High Voltage to support the voltage higher than + 1.65v (max 2.01v)) + 0: Nominal , 1: High Voltage +**/ + UINT8 VcciaBootVoltageSel; + +/** Offset 0x05ED - Granular Ratio Override + Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 GranularRatioOverride; + +/** Offset 0x05EE - Granularity Bins Override for Core + Array used to specifies the selected Core Granularity Bins. +**/ + UINT8 PerCoreGranularityBins[8]; + +/** Offset 0x05F6 - Granularity Bins Override for AtomCluster + Array used to specifies the selected AtomCluster Granularity Bins. +**/ + UINT8 PerAtomClusterGranularityBins[8]; + +/** Offset 0x05FE - Sa PLL Frequency + Configure Sa PLL Frequency. 0: 2400MHz , 1: 1600MHz + 0: 2400MHz, 1: 1600MHz +**/ + UINT8 SaPllFreqOverride; + +/** Offset 0x05FF - TSC HW Fixup disable + TSC HW Fixup disable during TSC copy from PMA to APIC. 0: Enable; 1: Disable + 0:Enable, 1:Disable +**/ + UINT8 TscDisableHwFixup; + +/** Offset 0x0600 - Process Vmax Limit + Setting this bit will allow user to set any voltage. Note: Disabling the voltage + limit checks may cause permanent damage to processor. 1: Enable; 0: Disable + 1:Enable, 0:Disable +**/ + UINT8 ProcessVmaxLimit; + +/** Offset 0x0601 - P-Core Power Density Throttle + This control allow user to disable P-core Power Density Throttling for overclocking. + 1: Enable; 0: Disable + 1:Enable, 0:Disable +**/ + UINT8 PcorePowerDensityThrottle; + +/** Offset 0x0602 - Request Core Min Ratio + 0(Default)=No Request +**/ + UINT8 CoreMinRatio; + +/** Offset 0x0603 - ReservedCpuPreMem + Reserved for Cpu Pre-Mem + $EN_DIS +**/ + UINT8 ReservedCpuPreMem[24]; + +/** Offset 0x061B - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x061C - Platform Psys slope correction + PSYS Slope defined in 1/100 increments. 0 - Auto Specified in 1/100 increment + values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x061D +**/ + UINT8 Rsvd170[1]; + +/** Offset 0x061E - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0620 - Thermal Design Current current limit + TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current + Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, + [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 TdcCurrentLimit[6]; + +/** Offset 0x062C - AcLoadline + AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 AcLoadline[6]; + +/** Offset 0x0638 - DcLoadline + DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 DcLoadline[6]; + +/** Offset 0x0644 - Power State 1 Threshold current + PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi1Threshold[6]; + +/** Offset 0x0650 - Power State 2 Threshold current + PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi2Threshold[6]; + +/** Offset 0x065C - Power State 3 Threshold current + PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi3Threshold[6]; + +/** Offset 0x0668 - Power State 3 enable/disable + PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Psi3Enable[6]; + +/** Offset 0x066E - Power State 4 enable/disable + PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT8 Psi4Enable[6]; + +/** Offset 0x0674 - Imon slope correction + IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter + 125. 0: Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 ImonSlope[6]; + +/** Offset 0x0680 - Imon offset correction + IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, + 127999]. For an offset of 25.348, enter 25348. 0: Auto. [0] for IA, [1] + for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT32 ImonOffset[6]; + +/** Offset 0x0698 - Enable/Disable BIOS configuration of VR + VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + 0: Disable; 1: Enable. +**/ + UINT8 VrConfigEnable[6]; + +/** Offset 0x069E - Thermal Design Current enable/disable + Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, + [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 TdcEnable[6]; + +/** Offset 0x06A4 - Thermal Design Current time window + TDC Time Window, value in seconds. Range from 1s to 448s, 0 = Auto/HW default. 0: + Auto. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT32 TdcTimeWindow[6]; + +/** Offset 0x06BC - Thermal Design Current Lock + Thermal Design Current Lock; 0: Disable; 1: Enable. For all VR Indexes +**/ + UINT8 TdcLock[6]; + +/** Offset 0x06C2 - DLVR RFI Frequency + DLVR RFI Frequency in MHz. 0x055A: 1370 MHz. +**/ + UINT16 DlvrRfiFrequency; + +/** Offset 0x06C4 - DLVR RFI Spread Spectrum Percentage + DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 31 = 7.75%. 0x06: 1.5%; + u3.2 value from 0% - 7.75%. +**/ + UINT8 DlvrSpreadSpectrumPercentage; + +/** Offset 0x06C5 - DLVR RFI Enable + Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DlvrRfiEnable; + +/** Offset 0x06C6 - Pre Wake Randomization time + Set the maximum Pre Wake randomization time in micro ticks. This is for acoustic + noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0. +**/ + UINT8 PreWake; + +/** Offset 0x06C7 - Ramp Up Randomization time + Set the maximum Ramp Up randomization time in micro ticks. This is for acoustic + noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x06C8 - Ramp Down Randomization time + Set the maximum Ramp Down randomization time in micro ticks. This is for acoustic + noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x06C9 - Available power delivery segments + This field is required to be non-zero on Desktop platforms. Used to communicate + the power delivery design capability of the board. This value is an enum of the + available power delivery segments that are defined in the Platform Design Guide. + 0: Disable.. +**/ + UINT8 VrPowerDeliveryDesign; + +/** Offset 0x06CA - VR Voltage Limit + Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed + at any given time. Range is 0 - 7999mV. [0] for IA, [1] for GT, [2] for SA, [3] + through [5] are Reserved. +**/ + UINT16 VrVoltageLimit[6]; + +/** Offset 0x06D6 - Enable/Disable PS1 to PS0 Dynamic Cutoff + PS1 to PS0 Dynamic Cutoff Enable/Disable. 0: Disable; 1: Enable. [0] for + IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 PS1toPS0DynamicCutoffEnable[6]; + +/** Offset 0x06DC - PS1 to PS0 Dynamic Cutoff M Coef + PS1 to PS0 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter + 1250. Range: 0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 PS1toPS0MCoef[6]; + +/** Offset 0x06E8 - PS1 to PS0 Dynamic Cutoff C Coef + PS1 to PS0 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter + 1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846, + range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 PS1toPS0CCoef[6]; + +/** Offset 0x06F4 - Enable/Disable PS2 to PS1 Dynamic Cutoff + PS2 to PS1 Dynamic Cutoff Enable/Disable. 0: Disable; 1: Enable. [0] for + IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 PS2toPS1DynamicCutoffEnable[6]; + +/** Offset 0x06FA - PS2 to PS1 Dynamic Cutoff M Coef + PS2 to PS1 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter + 1250, range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 PS2toPS1MCoef[6]; + +/** Offset 0x0706 - PS2 to PS1 Dynamic Cutoff C Coef + PS2 to PS1 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter + 1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846, + range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 PS2toPS1CCoef[6]; + +/** Offset 0x0712 - VCCIN Demotion + DEPRECATED. En/Dis VCCIN Demotion. 0: Disable, 1: Enable with default threshold, + 2: Enable with user configured threshold. [0] for IA, [1] for GT, [2] for SA, [3] + through [5] are Reserved. +**/ + UINT8 VccInDemotionEnable[6]; + +/** Offset 0x0718 - VCCIN Demotion Quiescent Power in mW + DEPRECATED. User configured platform quiescent threshold in milli-watt when VCC + Demotion is enabled. Range is 0-255mW. [0] for IA, [1] for GT, [2] for SA, [3] + through [5] are Reserved. +**/ + UINT8 VccInDemotionQuiescentPowerInMw[6]; + +/** Offset 0x071E +**/ + UINT8 Rsvd190[2]; + +/** Offset 0x0720 - VCCIN Demotion Capacitance in uF + DEPRECATED. User configured VR's quiescent power threshold in micro-farad when VCC + Demotion is enabled. Range: 0-2000uF. [0] for IA, [1] for GT, [2] for SA, [3] through + [5] are Reserved. +**/ + UINT32 VccInDemotionCapacitanceInUf[6]; + +/** Offset 0x0738 - Platform Psys offset correction + PSYS Offset defined in 1/1000 increments. 0 - Auto This is an 32-bit signed + value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset + of 25.348, enter 25348. +**/ + UINT32 PsysOffset; + +/** Offset 0x073C - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x0742 - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x0748 - Icc Max limit + Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous + current allowed at any given time. The value is represented in 1/4 A increments. + A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccMax[6]; + +/** Offset 0x0754 - VR Fast Vmode Offset + Voltage Regulator Fast Vmode Offset. This value represents the ICC Max Offset(dV/dT) + to be configured if Fast Vmode is enabled. The value is represented in 1 mV increments. + 0 = Use processor default setting. Highly recommend to keep at the default setting. + IA, GT and SA, range 0-255. [0] for IA, [1] for GT, [2] for SA, [3] through [5] + are Reserved. +**/ + UINT8 FastVmodeOffset[6]; + +/** Offset 0x075A - SVID Stabiliation Delay + Configure SVID Stabiliation Delay being used for the FVM feature when it is enabled. + Note that this delay applies to all SVID domains equally (no unique values possible + for IA/GT/SA).The value is represented in 1 us increments. IA, GT and SA, range 0-255. +**/ + UINT8 SvidStabilizationDelay; + +/** Offset 0x075B - VCC Demotion Shutdown Threshold in msec + User configured time threshold in msec. Range is 0-255 msec. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 VccDemotionShutdownThreshold[6]; + +/** Offset 0x0761 +**/ + UINT8 Rsvd200[1]; + +/** Offset 0x0762 - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x076E - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; 0: Disable; 1: Enable. For all VR by domain + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x0774 - Enable CEP + Enable/Disable CEP (Current Excursion Protection) Support. 0: Disable; 1: Enable. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + $EN_DIS +**/ + UINT8 CepEnable[6]; + +/** Offset 0x077A - Enable SIRP + Enable/Disable SIRP (SoC Iccmax Reactive Protection) Support. 0: Disable; + 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + $EN_DIS +**/ + UINT8 SirpEnable[6]; + +/** Offset 0x0780 - Enable IRMS + Enable/Disable IRMS for VR domains - Current root mean square. 0: Disable; + 1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 Irms[6]; + +/** Offset 0x0786 - UnderVolt Protection + When UnderVolt Protection is enabled, user will be not be able to program under + voltage in OS runtime. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 UnderVoltProtection; + +/** Offset 0x0787 - Vsys Critical + PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255. +**/ + UINT8 EnableVsysCritical; + +/** Offset 0x0788 - Vsys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 VsysFullScale; + +/** Offset 0x078C - Vsys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 VsysCriticalThreshold; + +/** Offset 0x0790 - Psys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 PsysFullScale; + +/** Offset 0x0794 - Psys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 PsysCriticalThreshold; + +/** Offset 0x0798 - Assertion Deglitch Mantissa + Assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchMantissa; + +/** Offset 0x0799 - Assertion Deglitch Exponent + Assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchExponent; + +/** Offset 0x079A - De assertion Deglitch Mantissa + De assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchMantissa; + +/** Offset 0x079B - De assertion Deglitch Exponent + De assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchExponent; + +/** Offset 0x079C - Per Core Max OC Ratio + Array for the Per Core Max OC Ratio +**/ + UINT8 PerCoreMaxRatio[8]; + +/** Offset 0x07A4 - Per Atom Cluster Max OC Ratio + Array for the Per Atom Cluster Max OC Ratio +**/ + UINT8 PerAtomClusterMaxRatio[8]; + +/** Offset 0x07AC - OC Max Voltage limits + OC Max Voltage limits +**/ + UINT16 MaxVoltageLimit[8]; + +/** Offset 0x07BC - Core PLL Current Reference Tuning Offset + Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllCurrentRefTuningOffset; + +/** Offset 0x07BD - Ring PLL Current Reference Tuning Offset + DEPRECATED. Ring PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllCurrentRefTuningOffset; + +/** Offset 0x07BE - IaAtom PLL Current Reference Tuning Offset + IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15 +**/ + UINT8 IaAtomPllCurrentRefTuningOffset; + +/** Offset 0x07BF - Per Core Disable Configuration + This configuration can be used only when OC is enabled,user can either use legacy + num of cores option or the OC specific per core disable configuration. 0: Disable, 1: Enable +**/ + UINT8 PerCoreDisableConfiguration; + +/** Offset 0x07C0 - Maximum Npu turbo ratio override + DEPRECATED. Maximum Npu turbo ratio override allows to increase NPU frequency beyond + the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-120 +**/ + UINT8 NpuMaxOcRatio; + +/** Offset 0x07C1 - NPU voltage mode + DEPRECATED. NPU voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 NpuVoltageMode; + +/** Offset 0x07C2 - NPU voltage override + DEPRECATED. The NPU voltage override which is applied to the entire range of cpu + NPU frequencies. Valid Range 0 to 2000 +**/ + UINT16 NpuVoltageOverride; + +/** Offset 0x07C4 - adaptive voltage applied during turbo frequencies + DEPRECATED. 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 NpuAdaptiveVoltage; + +/** Offset 0x07C6 - NPU Turbo voltage Offset + DEPRECATED. The voltage offset applied to the NPU while operating in turbo mode. + Valid Range 0 to 1000 +**/ + UINT16 NpuVoltageOffset; + +/** Offset 0x07C8 - OC Max Voltage limits + DEPRECATED. OC Max Voltage limits +**/ + UINT16 MaxVoltageLimitNew[9]; + +/** Offset 0x07DA - Force Pcore Residency + Enable/Disable Force Pcore Residency. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ForcePcoreResidency; + +/** Offset 0x07DB - VR Limit Bypass + Enable/Disable VR Limit Bypass. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VrLimitBypass; + +/** Offset 0x07DC - Turbo Thermal Protection + This control allow user to disable Turbo Thermal Protection (TTP) for overclocking. + 1: Enable; 0: Disable + 1:Enable, 0:Disable +**/ + UINT8 TurboThermalProtection; + +/** Offset 0x07DD +**/ + UINT8 CpuFspmUpdRsvd[47]; + +/** Offset 0x080C - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x080D +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x080E - Txt + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x080F +**/ + UINT8 Rsvd210[1]; + +/** Offset 0x0810 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x0814 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0818 +**/ + UINT8 Rsvd220[8]; + +/** Offset 0x0820 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x0828 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x082C - TxtDprMemorySize + Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize + , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x0830 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x0834 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x0838 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x083C - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x0840 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0848 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0850 - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x0851 - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS +**/ + UINT8 ReservedSecurityPreMem[32]; + +/** Offset 0x0871 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[28]; + +/** Offset 0x088D - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[28]; + +/** Offset 0x08A9 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; + +/** Offset 0x08C5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; + +/** Offset 0x08E1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; + +/** Offset 0x08FD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; + +/** Offset 0x0919 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; + +/** Offset 0x0935 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; + +/** Offset 0x0951 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; + +/** Offset 0x096D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[28]; + +/** Offset 0x0989 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; + +/** Offset 0x09A5 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; + +/** Offset 0x09C1 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; + +/** Offset 0x09DD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; + +/** Offset 0x09F9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x0A01 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x0A09 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x0A11 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x0A19 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x0A21 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x0A29 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x0A31 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x0A39 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x0A41 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x0A49 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x0A51 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x0A59 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x0A61 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x0A69 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x0A71 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x0A79 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x0A81 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x0A89 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x0A8A - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x0A8B - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x0A8C - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0A8D +**/ + UINT8 Rsvd230[1]; + +/** Offset 0x0A8E - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0A90 - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0A91 - Usage type for SOC/IOE ClkSrc + 0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x0AA1 - Usage type for PCH ClkSrc + 0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PchPcieClkSrcUsage[16]; + +/** Offset 0x0AB1 - SOC/IOE ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x0AC1 - PCH ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PchPcieClkSrcClkReq[16]; + +/** Offset 0x0AD1 +**/ + UINT8 Rsvd240[1]; + +/** Offset 0x0AD2 - PCH additional MMIO reserved + Additional MMIO reserved for PCH usage (i.e dTBT) in MB +**/ + UINT16 PchAdditionalMmioRsvd; + +/** Offset 0x0AD4 - Clk Req GPIO Pin + Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. +**/ + UINT32 PcieClkReqGpioMux[8]; + +/** Offset 0x0AF4 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; + +/** Offset 0x0AF8 - Enable PCH PCIE RP Mask + Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, + bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PchPcieRpEnableMask; + +/** Offset 0x0AFC - Enable SOC/IOE PCIE RP Mask + Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each + port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT16 PcieRpEnableMask; + +/** Offset 0x0AFE - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x0AFF - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x0B00 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x0B01 - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x0B03 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x0B04 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0B06 - Discrete BT Offload Enabled + Enable/disable Discrete BT Offload. +**/ + UINT8 HdaDiscBtOffEnabled; + +/** Offset 0x0B07 - PCH additional IO reserved + Additional IO reserved for PCH usage in KB +**/ + UINT8 PchAdditionalIoRsvd; + +/** Offset 0x0B08 - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x0B10 - DMIC ClkB Pin Muxing + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x0B18 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0B19 - Discrete BT Offload Ssp Link + Select SSP link instance for Discrete BT Offload. Note that this SSP instance must + also be enabled. +**/ + UINT8 HdaDiscBtOffSspLink; + +/** Offset 0x0B1A - SoC additional MMIO reserved + Additional MMIO reserved for SoC usage (i.e TBT) in MB +**/ + UINT16 SocAdditionalMmioRsvd; + +/** Offset 0x0B1C - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0B24 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0B2A - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x0B2E - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x0B2F - Sndw0 Multiline enablement + SoundWire Link 0 Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines + enabled, 2: Three lines enabled, 3: Four Lines enabled. + $EN_DIS +**/ + UINT8 PchHdAudioSndwMultilaneEnable; + +/** Offset 0x0B30 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x0B31 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x0B32 +**/ + UINT8 Rsvd260[1]; + +/** Offset 0x0B33 - SoC additional IO reserved + Additional IO reserved for SoC usage in KB +**/ + UINT8 SocAdditionalIoRsvd; + +/** Offset 0x0B34 - Audio Sub System IDs + Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. +**/ + UINT32 PchHdaSubSystemIds; + +/** Offset 0x0B38 - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x0B39 - Extended BIOS Support + Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 ExtendedBiosDecodeRange; + +/** Offset 0x0B3A - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x0B3B +**/ + UINT8 Rsvd270[1]; + +/** Offset 0x0B3C - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x0B40 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; + +/** Offset 0x0B44 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0B45 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0B46 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0B47 +**/ + UINT8 Rsvd280[1]; + +/** Offset 0x0B48 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0B4C - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0B4D - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0B4E - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0B4F - SerialIo Uart PowerGating + Select SerialIo Uart Powergating mode + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 SerialIoUartPowerGating; + +/** Offset 0x0B50 - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0B54 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0B55 - CPU SA PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CpuSaPllVoltageOffset; + +/** Offset 0x0B56 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0B57 - System Agent PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0B58 - IA Atom PLL voltage offset + IA Atom PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 IaAtomPllVoltageOffset; + +/** Offset 0x0B59 - Memory Controller PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0B5A - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x0B5B - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0B5C - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0B5D - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x0B5E - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x0B5F - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x0B60 - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x0B61 - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x0B62 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0B63 - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0B64 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0B65 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0B66 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0B67 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0B68 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0B69 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0B6A - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0B6B - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x0B6C - Unmatched Write Time Centering 1D + Enable/Disable {Unmatched Write Time Centering 1D + $EN_DIS +**/ + UINT8 UNMATCHEDWRTC1D; + +/** Offset 0x0B6D - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x0B6E - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x0B6F - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x0B70 - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x0B71 - DDR5 ODT Timing Config + Enable/Disable DDR5 ODT TIMING CONFIG + $EN_DIS +**/ + UINT8 DDR5ODTTIMING; + +/** Offset 0x0B72 - View Pin Calibration + Enables/Disable View Pin Calibration + $EN_DIS +**/ + UINT8 VIEWPINCAL; + +/** Offset 0x0B73 - Read DQS ODT Training + Enables/Disable Read DQS ODT Training + $EN_DIS +**/ + UINT8 RDDQSODTT; + +/** Offset 0x0B74 +**/ + UINT8 Rsvd290[6]; + +/** Offset 0x0B7A - Read DQ ODT Training + Enables/Disable Read DQ ODT Training + $EN_DIS +**/ + UINT8 RDDQODTT; + +/** Offset 0x0B7B - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0B7C - Read CTLE Training + Enables/Disable Read CTLE Training + $EN_DIS +**/ + UINT8 RDCTLET; + +/** Offset 0x0B7D - Hard Post Package Repair + Enables/Disable Hard Post Package Repair + $EN_DIS +**/ + UINT8 PPR; + +/** Offset 0x0B7E - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0B7F - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0B80 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0B81 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0B82 - RxVref Per-Bit Training + Enable/Disable RxVref Per-Bit Training + $EN_DIS +**/ + UINT8 RXVREFPERBIT; + +/** Offset 0x0B83 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0B84 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0B85 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x0B86 - Rank Margin Tool + Enable/disable Rank Margin Tool + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0B87 - LVR Auto Trim + Enable/disable LVR Auto Trim + $EN_DIS +**/ + UINT8 LVRAUTOTRIM; + +/** Offset 0x0B88 - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x0B89 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x0B8A - Row Hammering Prevention + Enables/Disable Row Hammering Prevention + $EN_DIS +**/ + UINT8 ROWHAMMER; + +/** Offset 0x0B8B - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x0B8C - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x0B8D - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x0B8E - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x0B8F - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x0B90 - CMD Drive Strength + Enable/Disable CMD Drive Strength + $EN_DIS +**/ + UINT8 CMDDS; + +/** Offset 0x0B91 - CMD Tx Equalization + Enable/Disable CMD Tx Equalization + $EN_DIS +**/ + UINT8 CMDTXEQ; + +/** Offset 0x0B92 - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x0B93 - Write DQ/DQS Retraining + Enable/Disable Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 WRTRETRAIN; + +/** Offset 0x0B94 - Power Saving Meter Update + Enable/Disable Power Saving Meter Update + $EN_DIS +**/ + UINT8 PWRMETER; + +/** Offset 0x0B95 - Pre-Training Comp Calibration + Enable/Disable Pre-Training Comp Calibration + $EN_DIS +**/ + UINT8 DDRPRECOMP; + +/** Offset 0x0B96 - Read Vref Decap Training + Enable/Disable Read Vref Decap Training + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x0B97 - Vddq Training + Enable/Disable Vddq Training + $EN_DIS +**/ + UINT8 VDDQT; + +/** Offset 0x0B98 - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x0B99 - DQ/DQS Swizzle Training + Enable/Disable DQ/DQS Swizzle Training + $EN_DIS +**/ + UINT8 DQDQSSWZ; + +/** Offset 0x0B9A - Ref PI Calibration + Enable/Disable Ref PI Calibration + $EN_DIS +**/ + UINT8 REFPI; + +/** Offset 0x0B9B - Rx SAL Calibration + Enable/Disable Rx SAL Calibration + 0:Disable, 1:Enable +**/ + UINT8 RXSALCAL; + +/** Offset 0x0B9C - VccClk FF Offset Correction + Enable/Disable VccClk FF Offset Correction + 0:Disable, 1:Enable +**/ + UINT8 VCCCLKFF; + +/** Offset 0x0B9D - Duty Cycle Correction Training + Enable/Disable Duty Cycle Correction Training + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0B9E - Duty Cycle Correction Downstream Training + Enable/Disable Duty Cycle Correction Downstream - PI Serializer/LUT + $EN_DIS +**/ + UINT8 DCCDOWNSTREAM; + +/** Offset 0x0B9F - Duty Cycle Correction QCLK Calibration + Enable/Disable Duty Cycle Correction QCLK Calbration + $EN_DIS +**/ + UINT8 DCCQCLK; + +/** Offset 0x0BA0 - Duty Cycle Correction Rise/Fall Training + Enable/Disable Duty Cycle Correction Rise/Fall Training + $EN_DIS +**/ + UINT8 DCCRISEFALL; + +/** Offset 0x0BA1 - Functional Duty Cycle Correction for DDR5 DQS + Enable/Disable Functional Duty Cycle Correction for DDR5 DQS + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQS; + +/** Offset 0x0BA2 - Functional Duty Cycle Correction for DDR5 CLK + Enable/Disable Functional Duty Cycle Correction for DDR5 CLK + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCCLK; + +/** Offset 0x0BA3 +**/ + UINT8 FUNCDCCWCK; + +/** Offset 0x0BA4 - Functional Duty Cycle Correction for Data DQ + Enable/Disable Functional Duty Cycle Correction for Data DQ + 0:Disable, 1:Enable +**/ + UINT8 FUNCDCCDQ; + +/** Offset 0x0BA5 - Data PI Linearity Calibration + Enable/Disable {ata PI Linearity Calibration + $EN_DIS +**/ + UINT8 DATAPILIN; + +/** Offset 0x0BA6 - Ddr5 Rx Cross-Talk Cancellation + Enable/Disable Ddr5 Rx Cross-Talk Cancellation + $EN_DIS +**/ + UINT8 DDR5XTALK; + +/** Offset 0x0BA7 - Duty Cycle Correction for LP5 DCA + Enable/Disable Duty Cycle Correction for LP5 DCA + $EN_DIS +**/ + UINT8 DCCLP5WCKDCA; + +/** Offset 0x0BA8 - Unmatched Rx Calibration + Enable/Disable Rx Unmatched Calibration + $EN_DIS +**/ + UINT8 RXUNMATCHEDCAL; + +/** Offset 0x0BA9 - Write Rank-to-Rank Training + Enable/Disable Write Rank-to-Rank Training + $EN_DIS +**/ + UINT8 TXRK2RK; + +/** Offset 0x0BAA - Read Rank-to-Rank Training + Enable/Disable Read Rank-to-Rank Training + $EN_DIS +**/ + UINT8 RXRK2RK; + +/** Offset 0x0BAB - Compensation Optimization + Enable/Disable Compensation Optimization + $EN_DIS +**/ + UINT8 OPTIMIZECOMP; + +/** Offset 0x0BAC - DIMM DFE Training + Enable/Disable DIMM DFE Training + $EN_DIS +**/ + UINT8 WRTDIMMDFE; + +/** Offset 0x0BAD - Write Drive Strength + Enables/Disable Write Drive Strength + $EN_DIS +**/ + UINT8 WRTDS; + +/** Offset 0x0BAE - Write Equalization + Enables/Disable Write Equalization + $EN_DIS +**/ + UINT8 WRTEQ; + +/** Offset 0x0BAF - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0BB0 - Ibecc + In-Band ECC Support + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x0BB1 - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x0BB2 - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x0BB3 - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x0BBB +**/ + UINT8 Rsvd300[1]; + +/** Offset 0x0BBC - IbeccProtectedRegionBases + IBECC Protected Region Bases per IBECC instance +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x0BCC - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; + +/** Offset 0x0BDC - IbeccProtectedRegionOverallBases + IBECC Protected Region Bases based on enabled IBECC instance +**/ + UINT16 IbeccProtectedRegionOverallBase[8]; + +/** Offset 0x0BEC - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0BED - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x0BEE - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x0BEF - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x0BF0 - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x0BF1 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x0BF2 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0BF3 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0BF4 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x0BF5 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x0BF6 - Row Hammer Select + Row Hammer Select + 0:Disable, 1:RFM, 2:pTRR +**/ + UINT8 RhSelect; + +/** Offset 0x0BF7 - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x0BF8 - DCC Single Rank Tracking + Force DCC to track single rank only + $EN_DIS +**/ + UINT8 DccSingleRankTrack; + +/** Offset 0x0BF9 - DDR5 supports MR7 WICA 0.5 tCK offset + DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset, 0:False, 1:True + 0:False, 1:True +**/ + UINT8 IsDdr5MR7WicaSupported; + +/** Offset 0x0BFA - Write0 feature + Enables/Disable Write0 feature + $EN_DIS +**/ + UINT8 Write0; + +/** Offset 0x0BFB - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 DdpSharedClock; + +/** Offset 0x0BFC - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x0BFD - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0BFE - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0C00 - Base reference clock value + Base reference clock value, in Hertz(Default is 125Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0C04 - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x0C06 - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x0C08 - CMD Normalization + Enable/Disable CMD Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x0C09 - Early DQ Write Drive Strength and Equalization Training + Enable/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x0C0A - Idle Energy Mc0Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm0; + +/** Offset 0x0C0B - Idle Energy Mc0Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm1; + +/** Offset 0x0C0C - Idle Energy Mc0Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm0; + +/** Offset 0x0C0D - Idle Energy Mc0Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm1; + +/** Offset 0x0C0E - Idle Energy Mc1Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm0; + +/** Offset 0x0C0F - Idle Energy Mc1Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm1; + +/** Offset 0x0C10 - Idle Energy Mc1Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm0; + +/** Offset 0x0C11 - Idle Energy Mc1Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm1; + +/** Offset 0x0C12 - PowerDown Energy Mc0Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm0; + +/** Offset 0x0C13 - PowerDown Energy Mc0Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm1; + +/** Offset 0x0C14 - PowerDown Energy Mc0Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm0; + +/** Offset 0x0C15 - PowerDown Energy Mc0Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm1; + +/** Offset 0x0C16 - PowerDown Energy Mc1Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm0; + +/** Offset 0x0C17 - PowerDown Energy Mc1Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm1; + +/** Offset 0x0C18 - PowerDown Energy Mc1Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm0; + +/** Offset 0x0C19 - PowerDown Energy Mc1Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm1; + +/** Offset 0x0C1A - Activate Energy Mc0Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm0; + +/** Offset 0x0C1B - Activate Energy Mc0Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm1; + +/** Offset 0x0C1C - Activate Energy Mc0Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm0; + +/** Offset 0x0C1D - Activate Energy Mc0Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm1; + +/** Offset 0x0C1E - Activate Energy Mc1Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm0; + +/** Offset 0x0C1F - Activate Energy Mc1Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm1; + +/** Offset 0x0C20 - Activate Energy Mc1Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm0; + +/** Offset 0x0C21 - Activate Energy Mc1Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm1; + +/** Offset 0x0C22 - Read Energy Mc0Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm0; + +/** Offset 0x0C23 - Read Energy Mc0Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm1; + +/** Offset 0x0C24 - Read Energy Mc0Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm0; + +/** Offset 0x0C25 - Read Energy Mc0Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm1; + +/** Offset 0x0C26 - Read Energy Mc1Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm0; + +/** Offset 0x0C27 - Read Energy Mc1Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm1; + +/** Offset 0x0C28 - Read Energy Mc1Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm0; + +/** Offset 0x0C29 - Read Energy Mc1Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm1; + +/** Offset 0x0C2A - Write Energy Mc0Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm0; + +/** Offset 0x0C2B - Write Energy Mc0Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm1; + +/** Offset 0x0C2C - Write Energy Mc0Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm0; + +/** Offset 0x0C2D - Write Energy Mc0Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm1; + +/** Offset 0x0C2E - Write Energy Mc1Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm0; + +/** Offset 0x0C2F - Write Energy Mc1Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm1; + +/** Offset 0x0C30 - Write Energy Mc1Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm0; + +/** Offset 0x0C31 - Write Energy Mc1Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm1; + +/** Offset 0x0C32 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x0C33 - Allow Opp Ref Below Write Threhold + Allow opportunistic refreshes while we don't exit power down. + $EN_DIS +**/ + UINT8 AllowOppRefBelowWriteThrehold; + +/** Offset 0x0C34 - Write Threshold + Number of writes that can be accumulated while CKE is low before CKE is asserted. +**/ + UINT8 WriteThreshold; + +/** Offset 0x0C35 - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x0C36 - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x0C37 - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x0C38 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x0C39 - Energy Performance Gain + Enable/disable Energy Performance Gain. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x0C3A - RH pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) +**/ + UINT8 Lfsr0Mask; + +/** Offset 0x0C3B - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x0C3C - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x0C3D - Opportunistic Self Refresh + Enable\Disable Opportunistic Self Refresh. + 0:Disabled, 1:Enabled +**/ + UINT8 OpportunisticSref; + +/** Offset 0x0C3E - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x0C3F - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x0C40 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x0C41 - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, + Rank0 is terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x0C42 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0C43 - MRC Safe Mode Override + SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode + override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3] + Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4] + Enable SaGv safe mode override +**/ + UINT8 SafeModeOverride; + +/** Offset 0x0C44 - MRC Safe Mode Support + MrcSafeMode[0]: Safe Frequency, MrcSafeMode[1]: Safe Gear, SafeMode[2]: Safe VCC + IOG/CLK, SafeMode[3]: Safe VCC DDQ +**/ + UINT8 MrcSafeMode; + +/** Offset 0x0C45 - Retrain On Working Channel + Enables/Disable Retrain On Working Channel feature + $EN_DIS +**/ + UINT8 RetrainToWorkingChannel; + +/** Offset 0x0C46 - DDR Phy Safe Mode Support + DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: + Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]: + PLL Operation, DdrSafeMode[6]: Safe ODT/SenseAmp Timing, DdrSafeMode[7]: Vtt Termination, + DdrSafeMode[8]: Periodic Comp +**/ + UINT16 DdrSafeMode; + +/** Offset 0x0C48 - Mc Safe Mode Support + McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate, + McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]: + Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5 + Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]: + Power Saving +**/ + UINT16 McSafeMode; + +/** Offset 0x0C4A - Board Stack Up + 0: Typical, 1: Frequency Limited +**/ + UINT8 BoardStackUp; + +/** Offset 0x0C4B - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x0C4C - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x0C4D - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:Enable, 0x1:Disable, 0x2:Auto +**/ + UINT8 PwDownMode; + +/** Offset 0x0C4E - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x0C50 - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x0C51 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x0C52 - Pwr Down Idle Timer + Default 0 = AUTO. Range is 30 to 2000(in us) +**/ + UINT16 PwDownIdleTimer; + +/** Offset 0x0C54 - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No + RFI Tuning. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; + +/** Offset 0x0C64 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x0C66 - Enable PCIe IMR + 0: Disable(AUTO), 1: Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x0C67 - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS +**/ + UINT8 PcieImrRpLocation; + +/** Offset 0x0C68 - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; + +/** Offset 0x0C69 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x0C6A - DdrOneDpc + DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 DdrOneDpc; + +/** Offset 0x0C6B - Override Driver Type + Override Driver Type. 0=Auto, 1=CMOS, 2=NMOS +**/ + UINT8 OverrideDriverType; + +/** Offset 0x0C6C - Lp5 Bypass Vddq Limits + Bypass Lp5 Vccddq Fuse limits. Advised to keep disabled +**/ + UINT8 Lp5BypassVddqLimits; + +/** Offset 0x0C6D - Enable/Disable I2cPostcode + Enable (Default): Postcode via I2C, Disable: Postcode via Port80 + $EN_DIS +**/ + UINT8 I2cPostCodeEnable; + +/** Offset 0x0C6E - Vddq Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VddqVoltageOverride; + +/** Offset 0x0C70 - VccIog Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccIogVoltageOverride; + +/** Offset 0x0C72 - VccClk Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VccClkVoltageOverride; + +/** Offset 0x0C74 - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x0C75 - RH pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x0C76 - Refresh Watermarks + Refresh Watermarks: 0-Low, 1-High (default) + 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) +**/ + UINT8 RefreshWm; + +/** Offset 0x0C77 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x0C78 - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x0C79 - Skip override boot mode When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to + BOOT_WITH_FULL_CONFIGURATION in PEI memory init. + $EN_DIS +**/ + UINT8 SiSkipOverrideBootModeWhenFwUpdate; + +/** Offset 0x0C7A - Opportunistic Self Refresh IdleTimer + Default 0 = AUTO. Range is 500 to 10000(in us) +**/ + UINT16 OppSrefIdleTmr; + +/** Offset 0x0C7C - LowerBasicMemTestSize + Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 LowerBasicMemTestSize; + +/** Offset 0x0C7D - Board Topology + 0: Daisy, 1: Tee +**/ + UINT8 BoardTopology; + +/** Offset 0x0C7E - RxDqsDelayTempCoeff + Default = 4. Range from 0-255 +**/ + UINT8 RxDqsDelayTempCoeff; + +/** Offset 0x0C7F +**/ + UINT8 MrcFspmUpdRsvd[15]; + +/** Offset 0x0C8E - PPR Test Type + Select memory tests used in Post Package Repair flow. This option is only valid + if PPR=1, otherwise ignored. Bit 0: WCMATS8 test, Bit 1: Data Retention test, Bit + 2: X March test, Bit 3: X March G test, Bit 4: Y March Short test, Bit 5: Y March + Long test. Default=0x3, WCMATS8 and data retention +**/ + UINT8 PprTestType; + +/** Offset 0x0C8F - PreMemRsvd + Reserved for Pre-Mem + $EN_DIS +**/ + UINT8 ReservedFspmUpd[2]; + +/** Offset 0x0C91 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0C92 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0C93 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0C94 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0C95 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0C96 +**/ + UINT8 Rsvd330[2]; + +/** Offset 0x0C98 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x0C9C - The policy for VTd driver behavior + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x0C9D +**/ + UINT8 Rsvd340[1]; + +/** Offset 0x0C9E - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelay; + +/** Offset 0x0CA0 - HgSubSystemId + Hybrid Graphics SubSystemId +**/ + UINT16 HgSubSystemId; + +/** Offset 0x0CA2 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0CA3 - Control VGA Initialition sequence + Initialise VGA Init, Set BIT0 - 0 (No VGA Support), BIT0 = 1 (VGA Supported) BIT1 + = 1 (VGA Exit) + 0x0: NO VGA Init, 0x1: VGA Init, 0x3: VGA Init and VGA Exit +**/ + UINT8 VgaInitControl; + +/** Offset 0x0CA4 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 VbtPtr; + +/** Offset 0x0CA8 - Intel Graphics VBT (Video BIOS Table) Size + Size of Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0CAC - VGA Training Message Pointer + Points to VGA Message Array +**/ + UINT32 VgaMessage; + +/** Offset 0x0CB0 - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SaPreMemTestRsvd[75]; + +/** Offset 0x0CFB - PPR Run Once + When Eanble, PPR will run only once and then is disabled at next training cycle + $EN_DIS +**/ + UINT8 PprRunOnce; + +/** Offset 0x0CFC - PPR Run During Fastboot + When Eanble, PPR will run during fastboot + $EN_DIS +**/ + UINT8 PprRunAtFastboot; + +/** Offset 0x0CFD - PPR Repair Type + PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair + 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair +**/ + UINT8 PprRepairType; + +/** Offset 0x0CFE - PPR Error Injection + When Eanble, PPR will inject bad rows during testing + $EN_DIS +**/ + UINT8 PprErrorInjection; + +/** Offset 0x0CFF - PPR ForceRepair + When Eanble, PPR will force repair some rows many times (90) + $EN_DIS +**/ + UINT8 PprForceRepair; + +/** Offset 0x0D00 - PPR Repair Controller + PPR repair controller: User chooses to force repair specifc address +**/ + UINT8 PprRepairController; + +/** Offset 0x0D01 - PPR Repair Channel + PPR repair Channel: User chooses to force repair specifc address +**/ + UINT8 PprRepairChannel; + +/** Offset 0x0D02 - PPR Repair Dimm + PPR repair Dimm: User chooses to force repair specifc address +**/ + UINT8 PprRepairDimm; + +/** Offset 0x0D03 - PPR Repair Rank + PPR repair Rank: User chooses to force repair specifc address +**/ + UINT8 PprRepairRank; + +/** Offset 0x0D04 - PPR Repair Row + PPR repair Row: User chooses to force repair specifc address +**/ + UINT32 PprRepairRow; + +/** Offset 0x0D08 - PPR Repair Physical Address Low + PPR repair Physical Address Low: User chooses to force repair specifc address +**/ + UINT32 PprRepairPhysicalAddrLow; + +/** Offset 0x0D0C - PPR Repair Physical Address High + PPR repair Physical Address High: User chooses to force repair specifc address +**/ + UINT32 PprRepairPhysicalAddrHigh; + +/** Offset 0x0D10 - PPR Repair BankGroup + PPR repair BankGroup: User chooses to force repair specifc address +**/ + UINT8 PprRepairBankGroup; + +/** Offset 0x0D11 - PPR Repair Bank + PPR repair Bank: User chooses to force repair specifc address +**/ + UINT8 PprRepairBank; + +/** Offset 0x0D12 - DIMM CA ODT Split Training + Enable/Disable DIMM CA ODT Split Training + $EN_DIS +**/ + UINT8 DIMMODTCASPLIT; + +/** Offset 0x0D13 - CMD Drive Strength Split + Enable/Disable CMD Drive Strength Split + $EN_DIS +**/ + UINT8 CMDDSSPLIT; + +/** Offset 0x0D14 - CMD Slew Rate Split Training + Enable/Disable CMD Slew Rate Split Training + $EN_DIS +**/ + UINT8 CMDSRSPLIT; + +/** Offset 0x0D15 +**/ + UINT8 SaFspmUpdRsvd[23]; + +/** Offset 0x0D2C - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + UINT16 TotalFlashSize; + +/** Offset 0x0D2E - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x0D30 - SecurityTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SecurityTestRsvd[12]; + +/** Offset 0x0D3C +**/ + UINT8 SecFspmUpdRsvd[16]; + +/** Offset 0x0D4C - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0D4D - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x0D4E - SoC BCLK PLL configuration + Configure SoC BCLK PLL state + $EN_DIS +**/ + UINT8 SocBclkPllOn; + +/** Offset 0x0D4F - CPU BCLK PLL configuration + Configure CPU BCLK PLL state + $EN_DIS +**/ + UINT8 CpuBclkPllOn; + +/** Offset 0x0D50 - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x0D51 - Dmi Tran Co Over En + Enable/Disable Lane Transmitter Coefficient. +**/ + UINT8 PchDmiTranCoOverEn[8]; + +/** Offset 0x0D59 - Dmi Tran Co Over Post Cur + Lane Transmitter Post-Cursor Coefficient Override. +**/ + UINT8 PchDmiTranCoOverPostCur[8]; + +/** Offset 0x0D61 - Dmi Tran Co Over Pre Cur + Lane Transmitter Pre-Cursor Coefficient Override. +**/ + UINT8 PchDmiTranCoOverPreCur[8]; + +/** Offset 0x0D69 - Dmi Up Port Tran Preset + Upstream Port Lane Transmitter Preset. +**/ + UINT8 PchDmiUpPortTranPreset[8]; + +/** Offset 0x0D71 - Dmi UpPort Tran Preset En + 0: POR setting, 1: force enable, 2: force disable. +**/ + UINT8 PchDmiUpPortTranPresetEn; + +/** Offset 0x0D72 - Dmi Rtlepceb + DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB). +**/ + UINT8 PchDmiRtlepceb; + +/** Offset 0x0D73 - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x0D74 - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x0D75 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x0D76 - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x0D77 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0D78 - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x0D79 - Enable KT device + Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0D7A - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0D7B +**/ + UINT8 PchMeFspmUpdRsvd[100]; + +/** Offset 0x0DDF - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x0DE0 - Avx512 Voltage Guardband Scaling Factor + DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range + is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x0DE1 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0DE2 +**/ + UINT16 Rsvd391; + +/** Offset 0x0DE4 - SerialIoUartDebugRxPinMux - FSPM + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0DE8 - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x0DEC - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0DF0 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0DF4 - Serial Io Uart Debug Pci Base + Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0 +**/ + UINT32 SerialIoUartDebugPciCfgBase; + +/** Offset 0x0DF8 - Memory Subsystem voltage mode + Memory Subsystem voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 MemSSVoltageMode; + +/** Offset 0x0DF9 +**/ + UINT8 Rsvd390; + +/** Offset 0x0DFA - Memory Subsystem Adaptive Voltage + Adaptive voltage applied to the memory when the cpu is operating in adaptive mode. + Valid Range 0 to 2000 +**/ + UINT16 MemSSAdaptiveVoltage; + +/** Offset 0x0DFC - Memory Subsystem voltage override + The Memory Subsystem voltage override which is applied to the entire range of memory + frequencies. Valid Range 0 to 2000 +**/ + UINT16 MemSSVoltageOverride; + +/** Offset 0x0DFE - Memory Subsystem VF Point Offset Mode + Selects Memory Subsystem Voltage & Frequency Offset mode between Legacy and Selection + modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection + Mode, setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 MemSSVfPointOffsetMode; + +/** Offset 0x0DFF - Maximum Memory Subsystem turbo ratio override + Maximum Memory Subsystem turbo ratio override allows to increase memory frequency + beyond the fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 MemSSMaxOcRatio; + +/** Offset 0x0E00 - Memory Subsystem Turbo voltage Offset + The voltage offset applied to the memory while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 MemSSVoltageOffset; + +/** Offset 0x0E02 - Select Core(s) and RING DLVR Mode + DEPRECATED. Select Core(s) and RING DLVR Mode). 0: Regulation Mode; 1: Power Gate Mode + 0:Regulation Mode, 1:Power Gate Mode +**/ + UINT8 CpuDlvrMode; + +/** Offset 0x0E03 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 NguMaxOcRatio; + +/** Offset 0x0E04 - NGU voltage mode + NGU voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 NguVoltageMode; + +/** Offset 0x0E05 - NGU Ratio + Sets the Ratio for NGU when SAGV is enabled, using SAVG B2P Mailbox cmd 0x22 and + subcommand 0x1. When this value is zero, dynamic mode is selected and NGU ratio + can be modified using OCMB cmd 0x11. When valid ratio value is set, static mode + is selected with the fixed ratio specified by this value.. 0: Hardware defaults. + Range: 0-85 +**/ + UINT8 NguRatio; + +/** Offset 0x0E06 - NGU voltage override + The NGU voltage override which is applied to the entire range of cpu NGU frequencies. + Valid Range 0 to 2000 +**/ + UINT16 NguVoltageOverride; + +/** Offset 0x0E08 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 NguAdaptiveVoltage; + +/** Offset 0x0E0A - NGU Turbo voltage Offset + The voltage offset applied to the NGU while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 NguVoltageOffset; + +/** Offset 0x0E0C - NGU VF Point Offset Mode + Selects NGU Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 NguVfPointOffsetMode; + +/** Offset 0x0E0D +**/ + UINT8 Rsvd410[1]; + +/** Offset 0x0E0E - NGU VF Point Offset + Array used to specifies the NGU Voltage Offset applied to the each selected VF Point. + This voltage is specified in millivolts. +**/ + UINT16 NguVfPointOffset[15]; + +/** Offset 0x0E2C - NGU VF Point Offset Prefix + Sets the NguVfPointOffset value as positive or negative for corresponding core VF + Point; 0: Positive ; 1: Negative. +**/ + UINT8 NguVfPointOffsetPrefix[15]; + +/** Offset 0x0E3B - NGU VF Point Ratio + Array for the each selected NGU VF Point to display the ration. +**/ + UINT8 NguVfPointRatio[15]; + +/** Offset 0x0E4A - NGU VF Point Count + Number of supported NGU Voltage & Frequency Point Offset +**/ + UINT8 NguVfPointCount; + +/** Offset 0x0E4B +**/ + UINT8 Rsvd420[11]; + +/** Offset 0x0E56 - GT VF Point Offset Mode + Selects GT Voltage & Frequency Offset mode between Legacy and Selection modes. In + Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 GtVfPointOffsetMode; + +/** Offset 0x0E57 +**/ + UINT8 Rsvd430[1]; + +/** Offset 0x0E58 - GT VF Point Offset + Array used to specifies the GT Voltage Offset applied to the each selected VF Point. + This voltage is specified in millivolts. +**/ + UINT16 GtVfPointOffset[15]; + +/** Offset 0x0E76 - GT VF Point Offset Prefix + Sets the GtVfPointOffset value as positive or negative for corresponding core VF + Point; 0: Positive ; 1: Negative. +**/ + UINT8 GtVfPointOffsetPrefix[15]; + +/** Offset 0x0E85 - GT VF Point Ratio + Array for the each selected GT VF Point to display the ration. +**/ + UINT8 GtVfPointRatio[15]; + +/** Offset 0x0E94 - GT VF Point Count + Number of supported GT Voltage & Frequency Point Offset +**/ + UINT8 GtVfPointCount; + +/** Offset 0x0E95 - Time Measure + Time Measure: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x0E96 - Must use static SPD data from VPD + Must use static SPD data from VPD and Spd Address is correct: Each bit maps to one dimm +**/ + UINT16 MrcMustStaticSpdData; + +/** Offset 0x0E98 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x0EA0 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x0EA8 - Generate New TME Key + Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x0EA9 - CkdAddress Tabl + Specify CKD Address table for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 CkdAddressTable[16]; + +/** Offset 0x0EB9 - Channel to CKD QCK Mapping + Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 ChannelToCkdQckMapping[8]; + +/** Offset 0x0EC1 - DDRIO Clock to CKD DIMM + Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1 +**/ + UINT8 PhyClockToCkdDimm[8]; + +/** Offset 0x0EC9 +**/ + UINT8 ReservedFspmUpd2[7]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0ED0 +**/ + UINT8 Rsvd500[6]; + +/** Offset 0x0ED6 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspsUpd.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspsUpd.h new file mode 100644 index 00000000..6e35b4c6 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FspsUpd.h @@ -0,0 +1,4565 @@ +/** @file + +Copyright (c) 2025, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Logo Pointer + Points to PEI Display Logo Image +**/ + UINT32 LogoPtr; + +/** Offset 0x0044 - Logo Size + Size of PEI Display Logo Image +**/ + UINT32 LogoSize; + +/** Offset 0x0048 - Blt Buffer Address + Address of Blt buffer +**/ + UINT32 BltBufferAddress; + +/** Offset 0x004C - Blt Buffer Size + Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of + EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +**/ + UINT32 BltBufferSize; + +/** Offset 0x0050 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0054 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0055 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x0056 +**/ + UINT8 Rsvd010[2]; + +/** Offset 0x0058 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x005C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0060 - Turbo Mode + Enable/Disable processor Turbo Mode. 0:disable, 1: Enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0061 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0062 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x006A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0072 +**/ + UINT8 Rsvd020[2]; + +/** Offset 0x0074 - SATA DEVSLP GPIO Pin + Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values. +**/ + UINT32 SataPortDevSlpPinMux[8]; + +/** Offset 0x0094 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x00A4 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x00AE - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x00AF +**/ + UINT8 Rsvd030; + +/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x00B4 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x00B5 - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x00BD - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x00BE - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x00BF - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x00C0 - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x00C1 - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x00C2 +**/ + UINT8 Rsvd040[2]; + +/** Offset 0x00C4 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT32 PchHdaVerbTablePtr; + +/** Offset 0x00C8 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x00C9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00CA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00CB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00D2 - SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 SerialIoSpiCsPolarity[14]; + +/** Offset 0x00E0 - SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpiCsEnable[14]; + +/** Offset 0x00EE - SPIn Default Chip Select Output + Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available + options: 0:CS0, 1:CS1 +**/ + UINT8 SerialIoSpiDefaultCsOutput[7]; + +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00FC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x0103 +**/ + UINT8 Rsvd050[1]; + +/** Offset 0x0104 - Serial IO SPI CS Pin Muxing + Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for + possible values. +**/ + UINT32 SerialIoSpiCsPinMux[14]; + +/** Offset 0x013C - Serial IO SPI CLK Pin Muxing + Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for + possible values. +**/ + UINT32 SerialIoSpiClkPinMux[7]; + +/** Offset 0x0158 - Serial IO SPI MISO Pin Muxing + Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO* + for possible values. +**/ + UINT32 SerialIoSpiMisoPinMux[7]; + +/** Offset 0x0174 - Serial IO SPI MOSI Pin Muxing + Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI* + for possible values. +**/ + UINT32 SerialIoSpiMosiPinMux[7]; + +/** Offset 0x0190 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x0197 +**/ + UINT8 Rsvd060[1]; + +/** Offset 0x0198 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x01B4 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x01BB - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x01C2 - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x01C9 - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x01D0 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x01D7 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x01DE +**/ + UINT8 Rsvd070[2]; + +/** Offset 0x01E0 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x01FC - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x0218 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0234 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0250 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x0257 - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x025F +**/ + UINT8 Rsvd080[1]; + +/** Offset 0x0260 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x0280 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x02A0 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x02A8 - I3C Device Mode + Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, + 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) +**/ + UINT8 SerialIoI3cMode[2]; + +/** Offset 0x02AA +**/ + UINT8 Rsvd090[2]; + +/** Offset 0x02AC - Serial IO I3C SDA Pin Muxing + Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for + possible values. +**/ + UINT32 SerialIoI3cSdaPinMux[2]; + +/** Offset 0x02B4 - Serial IO I3C SDA Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSdaPadTermination[2]; + +/** Offset 0x02B6 +**/ + UINT8 Rsvd100[2]; + +/** Offset 0x02B8 - Serial IO I3C SCL Pin Muxing + Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for + possible values. +**/ + UINT32 SerialIoI3cSclPinMux[2]; + +/** Offset 0x02C0 - Serial IO I3C SCL Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclPadTermination[2]; + +/** Offset 0x02C2 +**/ + UINT8 Rsvd110[2]; + +/** Offset 0x02C4 - Serial IO I3C SCL FB Pin Muxing + Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB* + for possible values. +**/ + UINT32 SerialIoI3cSclFbPinMux[2]; + +/** Offset 0x02CC - Serial IO I3C SCL FB Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination + respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on. +**/ + UINT8 SerialIoI3cSclFbPadTermination[2]; + +/** Offset 0x02CE +**/ + UINT8 Rsvd120[2]; + +/** Offset 0x02D0 - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[12]; + +/** Offset 0x0300 - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x030C - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0318 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0324 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x0330 - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x033C - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0348 - ISH I3C SDA Pin Muxing + Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values. +**/ + UINT32 IshI3cSdaPinMuxing; + +/** Offset 0x034C - ISH I3C SCL Pin Muxing + Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values. +**/ + UINT32 IshI3cSclPinMuxing; + +/** Offset 0x0350 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x0358 - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0360 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x0368 - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x0378 - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[12]; + +/** Offset 0x0384 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x0387 - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x038A - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x038D - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x0390 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x0393 - ISH I3C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI3cSdaPadTermination; + +/** Offset 0x0394 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x0397 - ISH I3C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI3cSclPadTermination; + +/** Offset 0x0398 - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x039A - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x039C - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x039E - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x03A2 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + +/** Offset 0x03A6 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x03B6 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x03C6 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x03D6 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x03E6 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x03F0 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x03FA - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0404 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x040E +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x0418 +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x0422 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x042C +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x0436 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x0440 +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x044A +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x0454 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x045E - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x045F - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS +**/ + UINT8 PchTsnEnable; + +/** Offset 0x0460 - TSN Link Speed + Set TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PchTsnLinkSpeed; + +/** Offset 0x0461 +**/ + UINT8 Rsvd130[3]; + +/** Offset 0x0464 - PCH TSN MAC Address High Bits + Set TSN MAC Address High. +**/ + UINT32 PchTsnMacAddressHigh; + +/** Offset 0x0468 - PCH TSN MAC Address Low Bits + Set TSN MAC Address Low. +**/ + UINT32 PchTsnMacAddressLow; + +/** Offset 0x046C - PCH TSN MAC Address High Bits + Set TSN MAC Address High. +**/ + UINT32 PchTsn1MacAddressHigh; + +/** Offset 0x0470 - PCH TSN MAC Address Low Bits + Set TSN MAC Address Low. +**/ + UINT32 PchTsn1MacAddressLow; + +/** Offset 0x0474 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[29]; + +/** Offset 0x0491 - Disable DMI Power Gating + Enable/disable DMI Power Gating Disable. + $EN_DIS +**/ + UINT8 DmiPowerGatingDis; + +/** Offset 0x0492 +**/ + UINT8 Rsvd135[28]; + +/** Offset 0x04AE - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x04AF +**/ + UINT8 Rsvd140[5]; + +/** Offset 0x04B4 - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x04B8 - PCH eSPI Host and Device BME enabled + PCH eSPI Host and Device BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeHostDeviceEnabled; + +/** Offset 0x04B9 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x04BA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x04BB - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x04BC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x04BE - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x04BF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x04C0 - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x04C1 +**/ + UINT8 Rsvd150; + +/** Offset 0x04C2 - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x04C4 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x04C5 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x04C6 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x04C8 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x04C9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x04CA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x04CB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x04CC - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x04CE - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x04CF +**/ + UINT8 Rsvd160; + +/** Offset 0x04D0 - Pointer to ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x04D4 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x04D8 - Pointer to NPHY Binary + Nphy Binary Pointer. +**/ + UINT32 NphyBinPtr; + +/** Offset 0x04DC - Length of NPHY Binary + Nphy Binary Length. +**/ + UINT32 NphyBinLen; + +/** Offset 0x04E0 - Pointer to SYNPS PHY Binary + Synps Binary Pointer. +**/ + UINT32 SynpsPhyBinPtr; + +/** Offset 0x04E4 - Length of SYNPS PHY Binary + Synps Binary Length. +**/ + UINT32 SynpsPhyBinLen; + +/** Offset 0x04E8 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x04E9 +**/ + UINT8 Rsvd170; + +/** Offset 0x04EA - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x04EC - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x04EE - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x04F0 - USB Audio Offload enable + Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default) + $EN_DIS +**/ + UINT8 PchXhciUaolEnable; + +/** Offset 0x04F1 - PCH xHCI enable HS Interrupt IN Alarm + PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchXhciHsiiEnable; + +/** Offset 0x04F2 +**/ + UINT8 Rsvd175[2]; + +/** Offset 0x04F4 - PCH GPIOV2 Unlock Data Buffer Address + Address of GPIO Unlock Data buffer +**/ + UINT32 PchGpioUnlockDataPtr; + +/** Offset 0x04F8 - PCH GPIOV2 Unlock Data Buffer Size + Size of PCH GPIO Unlock Data Buffer +**/ + UINT32 PchGpioUnlockDataSize; + +/** Offset 0x04FC - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd[2]; + +/** Offset 0x04FE - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x04FF - CNVi Wi-Fi Core + Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviWifiCore; + +/** Offset 0x0500 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x0501 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x0502 +**/ + UINT8 Rsvd180[2]; + +/** Offset 0x0504 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0508 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x050C - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x050D - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x050E - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x050F - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0510 - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x0511 - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; + +/** Offset 0x0512 - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x051A - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x051B - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x051C - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x051D - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x051E - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x051F - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 FwProgress; + +/** Offset 0x0520 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x0521 +**/ + UINT8 Rsvd190; + +/** Offset 0x0522 - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0524 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x0526 - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[29]; + +/** Offset 0x0543 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[29]; + +/** Offset 0x0560 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[29]; + +/** Offset 0x057D +**/ + UINT8 Rsvd200[3]; + +/** Offset 0x0580 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[29]; + +/** Offset 0x05BA - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x05BB - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x05BC - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x05BD - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x05BE - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x05BF - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x05C0 - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x05C1 +**/ + UINT8 Rsvd210[3]; + +/** Offset 0x05C4 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl + = MeteorLake) +**/ + UINT32 IomTypeCPortPadCfg[12]; + +/** Offset 0x05F4 - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x05FC - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x05FD - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS +**/ + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x05FE - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS +**/ + UINT8 SkipFspGop; + +/** Offset 0x05FF - Enable/Disable VPU Device + Enable(Default): Enable VPU Device, Disable: Disable VPU Device + $EN_DIS +**/ + UINT8 VpuEnable; + +/** Offset 0x0600 - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x0601 - Display port support policy in TCSS + This policy will enable/disable Display port support in IOM + $EN_DIS +**/ + UINT8 TcNotifyIgd; + +/** Offset 0x0602 +**/ + UINT8 Rsvd220[2]; + +/** Offset 0x0604 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0608 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0609 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 SaPostMemRsvd[8]; + +/** Offset 0x0611 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0612 - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0613 - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0632 - VMD Port Bus + VMD Root port bus number. +**/ + UINT8 VmdPortBus[31]; + +/** Offset 0x0651 - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0670 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x068F +**/ + UINT8 Rsvd230; + +/** Offset 0x0690 - VMD Variable + VMD Variable Pointer. +**/ + UINT32 VmdVariablePtr; + +/** Offset 0x0694 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x0698 - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x069C - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x06A0 - TCSS CPU USB PDO Programming + Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow + for programming during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 TcssCpuUsbPdoProgramming; + +/** Offset 0x06A1 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x06A2 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x06A4 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x06A6 - USB override in IOM + This policy will enable/disable USB Connect override in IOM + $EN_DIS +**/ + UINT8 UsbOverride; + +/** Offset 0x06A7 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x06AB - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x06AC - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x06AE - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x06B0 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x06B1 +**/ + UINT8 Rsvd240[1]; + +/** Offset 0x06B2 - ITBT DMA LTR + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x06B6 - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x06B7 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x06BB - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x06BF - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x06C3 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x06C7 +**/ + UINT8 Rsvd250[1]; + +/** Offset 0x06C8 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x06D0 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x06D4 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x06D8 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x06E0 - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x06E4 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x06E8 - Enable or Disable TXT + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x06E9 +**/ + UINT8 Rsvd260[3]; + +/** Offset 0x06EC - CpuBistData + Pointer CPU BIST Data +**/ + UINT32 CpuBistData; + +/** Offset 0x06F0 - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x06F4 - Boot frequency + Select the performance state that the BIOS will set starting from reset vector. + 0: Maximum battery performance. 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x06F5 +**/ + UINT8 CpuPostMemRsvd[2]; + +/** Offset 0x06F7 +**/ + UINT8 Rsvd270[1]; + +/** Offset 0x06F8 - PpinSupport to view Protected Processor Inventory Number + PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn + off this feature. When 'PPIN Enable Mode' is selected, this shows second option + where feature can be enabled based on EOM (End of Manufacturing) flag or it is + always enabled + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x06F9 - Memory size per thread allocated for Processor Trace + Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment + and size in bytes per thread, from 4KB to 128MB.\n + 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, + 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M +**/ + UINT8 ProcessorTraceMemSize; + +/** Offset 0x06FA - Smbios Type4 Max Speed Override + Provide the option for platform to override the MaxSpeed field of Smbios Type 4. + If this value is not zero, it dominates the field. +**/ + UINT16 SmbiosType4MaxSpeedOverride; + +/** Offset 0x06FC - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x06FD - AvxDisable + Enable/Disable the AVX and AVX2 Instructions + 0: Enable, 1: Disable +**/ + UINT8 AvxDisable; + +/** Offset 0x06FE - X2ApicEnable + Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled', + 'VT-d' option must be 'Enabled' and 'X2APIC Opt Out' option must be 'Disabled' as well. + $EN_DIS +**/ + UINT8 X2ApicEnable; + +/** Offset 0x06FF - ProcHot Demotion Algorithm configuration + ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable; + 1: Hardware Default + 0: Disable, 1: Hardware Default +**/ + UINT8 ProcHotDemotion; + +/** Offset 0x0700 - ReservedCpuPostMemProduction + Reserved for CPU Post-Mem Production + $EN_DIS +**/ + UINT8 ReservedCpuPostMemProduction[56]; + +/** Offset 0x0738 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x0739 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x073E - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x0743 +**/ + UINT8 Rsvd280[1]; + +/** Offset 0x0744 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x074E - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x0758 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x0759 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x075A - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x075B - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x075C - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x075D - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x075E - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x0760 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x0763 - Enable PCH ISH I3C pins assigned + Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI3cEnable; + +/** Offset 0x0764 - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[12]; + +/** Offset 0x0770 - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x0771 - PCH ISH Disable MSI Interrupts + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshMsiInterrupt; + +/** Offset 0x0772 - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x0773 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x0774 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x0775 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x0776 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0777 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[29]; + +/** Offset 0x0794 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. + $EN_DIS +**/ + UINT8 PcieRpPmSci[29]; + +/** Offset 0x07B1 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[29]; + +/** Offset 0x07CE - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[29]; + +/** Offset 0x07EB - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[29]; + +/** Offset 0x0808 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[29]; + +/** Offset 0x0825 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[29]; + +/** Offset 0x0842 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[29]; + +/** Offset 0x085F - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[29]; + +/** Offset 0x087C - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[29]; + +/** Offset 0x0899 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[29]; + +/** Offset 0x08B6 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[29]; + +/** Offset 0x08D3 - PCIE RP Max Payload + Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[29]; + +/** Offset 0x08F0 - Touch Host Controller Assignment + Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcAssignment[2]; + +/** Offset 0x08F2 - Touch Host Controller Interrupt Pin Mux + Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* + for possible values. +**/ + UINT8 ThcInterruptPinMuxing[8]; + +/** Offset 0x08FA - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid +**/ + UINT8 ThcMode[2]; + +/** Offset 0x08FC - Touch Host Controller Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI +**/ + UINT8 ThcWakeOnTouch[2]; + +/** Offset 0x08FE +**/ + UINT8 Rsvd290[2]; + +/** Offset 0x0900 - Touch Host Controller Active Ltr + Expose Active Ltr for OS driver to set +**/ + UINT32 ThcActiveLtr[2]; + +/** Offset 0x0908 - Touch Host Controller Idle Ltr + Expose Idle Ltr for OS driver to set +**/ + UINT32 ThcIdleLtr[2]; + +/** Offset 0x0910 - Touch Host Controller Hid Over Spi ResetPad + Hid Over Spi ResetPad +**/ + UINT32 ThcResetPad[2]; + +/** Offset 0x0918 - Touch Host Controller Hid Over Spi ResetPad Trigger + Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High +**/ + UINT32 ThcResetPadTrigger[2]; + +/** Offset 0x0920 - Touch Host Controller Hid Over Spi Connection Speed + Hid Over Spi Connection Speed - SPI Frequency +**/ + UINT32 ThcHidSpiConnectionSpeed[2]; + +/** Offset 0x0928 - Touch Host Controller Hid Over Spi Limit PacketSize + When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc + packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes +**/ + UINT32 ThcHidSpiLimitPacketSize[2]; + +/** Offset 0x0930 - Touch Host Controller Hid Over Spi Limit PacketSize + Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation + and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, + 1-65535 (0xFFFF) - up to 655350 us +**/ + UINT32 ThcPerformanceLimitation[2]; + +/** Offset 0x0938 - Touch Host Controller Hid Over Spi Input Report Header Address + Hid Over Spi Input Report Header Address +**/ + UINT32 ThcHidSpiInputReportHeaderAddress[2]; + +/** Offset 0x0940 - Touch Host Controller Hid Over Spi Input Report Body Address + Hid Over Spi Input Report Body Address +**/ + UINT32 ThcHidSpiInputReportBodyAddress[2]; + +/** Offset 0x0948 - Touch Host Controller Hid Over Spi Output Report Address + Hid Over Spi Output Report Address +**/ + UINT32 ThcHidSpiOutputReportAddress[2]; + +/** Offset 0x0950 - Touch Host Controller Hid Over Spi Read Opcode + Hid Over Spi Read Opcode +**/ + UINT32 ThcHidSpiReadOpcode[2]; + +/** Offset 0x0958 - Touch Host Controller Hid Over Spi Write Opcode + Hid Over Spi Write Opcode +**/ + UINT32 ThcHidSpiWriteOpcode[2]; + +/** Offset 0x0960 - Touch Host Controller Hid Over Spi Flags + Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode +**/ + UINT32 ThcHidSpiFlags[2]; + +/** Offset 0x0968 - Touch Host Controller Hid Over Spi Reset Sequencing Delay [ms] + Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms +**/ + UINT16 ThcResetSequencingDelay[2]; + +/** Offset 0x096C - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[29]; + +/** Offset 0x0989 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[29]; + +/** Offset 0x09A6 - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[29]; + +/** Offset 0x09C3 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[29]; + +/** Offset 0x09E0 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[29]; + +/** Offset 0x09FD - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[29]; + +/** Offset 0x0A1A - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[29]; + +/** Offset 0x0A37 - PCIE RP override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault[29]; + +/** Offset 0x0A54 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen3EqMethod[29]; + +/** Offset 0x0A71 - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen3EqMode[29]; + +/** Offset 0x0A8E - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen3EqLocalTxOverrideEn[29]; + +/** Offset 0x0AAB - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen3EqPh3NoOfPresetOrCoeff[29]; + +/** Offset 0x0AC8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor0List[29]; + +/** Offset 0x0AE5 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor0List[29]; + +/** Offset 0x0B02 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor1List[29]; + +/** Offset 0x0B1F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor1List[29]; + +/** Offset 0x0B3C - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor2List[29]; + +/** Offset 0x0B59 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor2List[29]; + +/** Offset 0x0B76 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor3List[29]; + +/** Offset 0x0B93 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor3List[29]; + +/** Offset 0x0BB0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor4List[29]; + +/** Offset 0x0BCD - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor4List[29]; + +/** Offset 0x0BEA - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor5List[29]; + +/** Offset 0x0C07 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor5List[29]; + +/** Offset 0x0C24 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor6List[29]; + +/** Offset 0x0C41 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor6List[29]; + +/** Offset 0x0C5E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor7List[29]; + +/** Offset 0x0C7B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor7List[29]; + +/** Offset 0x0C98 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor8List[29]; + +/** Offset 0x0CB5 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor8List[29]; + +/** Offset 0x0CD2 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PreCursor9List[29]; + +/** Offset 0x0CEF - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3PostCursor9List[29]; + +/** Offset 0x0D0C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset0List[29]; + +/** Offset 0x0D29 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset1List[29]; + +/** Offset 0x0D46 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset2List[29]; + +/** Offset 0x0D63 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset3List[29]; + +/** Offset 0x0D80 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset4List[29]; + +/** Offset 0x0D9D - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset5List[29]; + +/** Offset 0x0DBA - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset6List[29]; + +/** Offset 0x0DD7 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset7List[29]; + +/** Offset 0x0DF4 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset8List[29]; + +/** Offset 0x0E11 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset9List[29]; + +/** Offset 0x0E2E - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen3EqPh3Preset10List[29]; + +/** Offset 0x0E4B - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen3EqPh1DpTxPreset[29]; + +/** Offset 0x0E68 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen3EqPh1UpTxPreset[29]; + +/** Offset 0x0E85 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen3EqPh2LocalTxOverridePreset[29]; + +/** Offset 0x0EA2 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen4EqMethod[29]; + +/** Offset 0x0EBF - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen4EqMode[29]; + +/** Offset 0x0EDC - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen4EqLocalTxOverrideEn[29]; + +/** Offset 0x0EF9 - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen4EqPh3NoOfPresetOrCoeff[29]; + +/** Offset 0x0F16 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor0List[29]; + +/** Offset 0x0F33 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor0List[29]; + +/** Offset 0x0F50 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor1List[29]; + +/** Offset 0x0F6D - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor1List[29]; + +/** Offset 0x0F8A - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor2List[29]; + +/** Offset 0x0FA7 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor2List[29]; + +/** Offset 0x0FC4 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor3List[29]; + +/** Offset 0x0FE1 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor3List[29]; + +/** Offset 0x0FFE - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor4List[29]; + +/** Offset 0x101B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor4List[29]; + +/** Offset 0x1038 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor5List[29]; + +/** Offset 0x1055 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor5List[29]; + +/** Offset 0x1072 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor6List[29]; + +/** Offset 0x108F - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor6List[29]; + +/** Offset 0x10AC - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor7List[29]; + +/** Offset 0x10C9 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor7List[29]; + +/** Offset 0x10E6 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor8List[29]; + +/** Offset 0x1103 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor8List[29]; + +/** Offset 0x1120 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PreCursor9List[29]; + +/** Offset 0x113D - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3PostCursor9List[29]; + +/** Offset 0x115A - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset0List[29]; + +/** Offset 0x1177 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset1List[29]; + +/** Offset 0x1194 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset2List[29]; + +/** Offset 0x11B1 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset3List[29]; + +/** Offset 0x11CE - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset4List[29]; + +/** Offset 0x11EB - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset5List[29]; + +/** Offset 0x1208 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset6List[29]; + +/** Offset 0x1225 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset7List[29]; + +/** Offset 0x1242 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset8List[29]; + +/** Offset 0x125F - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset9List[29]; + +/** Offset 0x127C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen4EqPh3Preset10List[29]; + +/** Offset 0x1299 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen4EqPh1DpTxPreset[29]; + +/** Offset 0x12B6 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen4EqPh1UpTxPreset[29]; + +/** Offset 0x12D3 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen4EqPh2LocalTxOverridePreset[29]; + +/** Offset 0x12F0 - PCIE RP choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieGen5EqMethod[29]; + +/** Offset 0x130D - PCIE RP choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieGen5EqMode[29]; + +/** Offset 0x132A - PCIE RP EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieGen5EqLocalTxOverrideEn[29]; + +/** Offset 0x1347 - PCI RP number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieGen5EqPh3NoOfPresetOrCoeff[29]; + +/** Offset 0x1364 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor0List[29]; + +/** Offset 0x1381 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor0List[29]; + +/** Offset 0x139E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor1List[29]; + +/** Offset 0x13BB - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor1List[29]; + +/** Offset 0x13D8 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor2List[29]; + +/** Offset 0x13F5 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor2List[29]; + +/** Offset 0x1412 - PCIR RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor3List[29]; + +/** Offset 0x142F - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor3List[29]; + +/** Offset 0x144C - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor4List[29]; + +/** Offset 0x1469 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor4List[29]; + +/** Offset 0x1486 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor5List[29]; + +/** Offset 0x14A3 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor5List[29]; + +/** Offset 0x14C0 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor6List[29]; + +/** Offset 0x14DD - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor6List[29]; + +/** Offset 0x14FA - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor7List[29]; + +/** Offset 0x1517 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor7List[29]; + +/** Offset 0x1534 - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor8List[29]; + +/** Offset 0x1551 - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor8List[29]; + +/** Offset 0x156E - PCIE RP pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PreCursor9List[29]; + +/** Offset 0x158B - PCIE RP post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3PostCursor9List[29]; + +/** Offset 0x15A8 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset0List[29]; + +/** Offset 0x15C5 - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset1List[29]; + +/** Offset 0x15E2 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset2List[29]; + +/** Offset 0x15FF - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset3List[29]; + +/** Offset 0x161C - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset4List[29]; + +/** Offset 0x1639 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset5List[29]; + +/** Offset 0x1656 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset6List[29]; + +/** Offset 0x1673 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset7List[29]; + +/** Offset 0x1690 - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset8List[29]; + +/** Offset 0x16AD - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset9List[29]; + +/** Offset 0x16CA - PCIE RP preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieGen5EqPh3Preset10List[29]; + +/** Offset 0x16E7 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT8 PcieGen5EqPh1DpTxPreset[29]; + +/** Offset 0x1704 - PCIE RP EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT8 PcieGen5EqPh1UpTxPreset[29]; + +/** Offset 0x1721 - PCIE RP EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieGen5EqPh2LocalTxOverridePreset[29]; + +/** Offset 0x173E - Phase3 RP Gen3 EQ enable + Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh3Bypass[29]; + +/** Offset 0x175B - Phase3 RP Gen3 EQ enable + Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh3Bypass[29]; + +/** Offset 0x1778 - Phase3 RP Gen5 EQ enable + Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh3Bypass[29]; + +/** Offset 0x1795 - Phase2-3 RP Gen3 EQ enable + Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPh23Bypass[29]; + +/** Offset 0x17B2 - Phase2-3 RP Gen4 EQ enable + Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPh23Bypass[29]; + +/** Offset 0x17CF - Phase2-3 RP Gen5 EQ enable + Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1): + Enable Phase2-3 + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPh23Bypass[29]; + +/** Offset 0x17EC - RP Gen3 EQ Phase enable + Gen3 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen3EqPhBypass[29]; + +/** Offset 0x1809 - RP Gen4 EQ Phase enable + Gen4 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen4EqPhBypass[29]; + +/** Offset 0x1826 - RP Gen5 EQ Phase enable + Gen5 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 PcieRpGen5EqPhBypass[29]; + +/** Offset 0x1843 - PCET Timer + Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen3PcetTimer[29]; + +/** Offset 0x1860 - Gen4 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen4PcetTimer[29]; + +/** Offset 0x187D - Gen5 PCET Timer + Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default + is 0x0(2ms) +**/ + UINT8 PcieGen5PcetTimer[29]; + +/** Offset 0x189A - TS Lock Timer for Gen3 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock + Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen3TsLockTimer[29]; + +/** Offset 0x18B7 - PTS Lock Timer for Gen4 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock + Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen4TsLockTimer[29]; + +/** Offset 0x18D4 - PTS Lock Timer for Gen5 + Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock + Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0 +**/ + UINT8 PcieGen5TsLockTimer[29]; + +/** Offset 0x18F1 - PCIE Secure Register Lock + Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, + load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 PcieSetSecuredRegisterLock; + +/** Offset 0x18F2 - DG Wait + 0(Default) = Disable, 1 = Enable + $EN_DIS +**/ + UINT8 DGWait; + +/** Offset 0x18F3 - Enable/Disable ASPM Optionality Compliance + Enable/Disable ASPM Optionality Compliance. +**/ + UINT8 PcieRpTestAspmOc[29]; + +/** Offset 0x1910 - PCIe Configuration Dump + Enable/Disable ASPM Optionality Compliance. + 0:Disable, 1:Enable +**/ + UINT8 PcieCfgDump[29]; + +/** Offset 0x192D - PCIE RP Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite[29]; + +/** Offset 0x194A - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x194B - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x194C - PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieFiaProgramming; + +/** Offset 0x194D - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x194E - PCIE IMR + Enables Isolated Memory Region for PCIe. + $EN_DIS +**/ + UINT8 PcieRpImrEnabled; + +/** Offset 0x194F - PCIE IMR port number + Selects PCIE root port number for IMR feature. +**/ + UINT8 PcieRpImrSelection; + +/** Offset 0x1950 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x1951 - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x1952 - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x1953 - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x1954 - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + UINT8 PchPmDeepSxPol; + +/** Offset 0x1955 - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + UINT8 PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x1956 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x1957 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x1958 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x1959 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x195A - USB Overcurrent Override for VISA + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when VISA pin is muxed with USB OC + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x195B - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x195C - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x195D - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x195E - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x195F - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x1960 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x1961 - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x1962 - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x1963 - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x1964 - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x1965 - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + UINT8 EsataSpeedLimit; + +/** Offset 0x1966 - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + UINT8 SataSpeedLimit; + +/** Offset 0x1967 - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x196F - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + UINT8 SataPortsInterlockSw[8]; + +/** Offset 0x1977 - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x197F - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x1987 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x198F - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x1997 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x199F - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspm; + +/** Offset 0x19A0 +**/ + UINT8 Rsvd300[1]; + +/** Offset 0x19A1 +**/ + UINT8 UnusedUpdSpace0[1]; + +/** Offset 0x19A2 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x19B2 - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + UINT8 SataPortsZpOdd[8]; + +/** Offset 0x19BA - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + UINT8 SataRstRaidDeviceId; + +/** Offset 0x19BB - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + UINT8 SataRstPcieEnable[3]; + +/** Offset 0x19BE - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + UINT8 SataRstPcieStoragePort[3]; + +/** Offset 0x19C1 - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + UINT8 SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x19C4 - UFS enable/disable + Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller + 0 and (0,1) to enable controller 1 + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x19C6 - UFS Inline Encryption enable/disable + Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0) + to enable Inline Encryption for controller 0 and (0,1) to enable Inline Encryption + for controller 1 + $EN_DIS +**/ + UINT8 UfsInlineEncryption[2]; + +/** Offset 0x19C8 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x19C9 - SOC Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels + are ignored but with native settings. + $EN_DIS +**/ + UINT8 SocTTSuggestedSetting; + +/** Offset 0x19CA - SOC Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 SocT0Level; + +/** Offset 0x19CC - SOC Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 SocT1Level; + +/** Offset 0x19CE - SOC Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 SocT2Level; + +/** Offset 0x19D0 - Enable SOC Thermal Throttle + Enable thermal throttle function. + $EN_DIS +**/ + UINT8 SocTTEnable; + +/** Offset 0x19D1 - SOC PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 SocTTState13Enable; + +/** Offset 0x19D2 - SOC Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 SocTTLock; + +/** Offset 0x19D3 - PCH Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels + are ignored but with native settings. + $EN_DIS +**/ + UINT8 PchTTSuggestedSetting; + +/** Offset 0x19D4 - PCH Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x19D6 - PCH Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x19D8 - PCH Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x19DA - Enable PCH Thermal Throttle + Enable thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x19DB - PCH PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x19DC - PCH Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x19DD - IOE Thermal Throttling Suggested Setting + IOE Thermal Throttling Suggested Setting. When it is enabled, customized throttle + levels are ignored but with native settings. + $EN_DIS +**/ + UINT8 IoeTTSuggestedSetting; + +/** Offset 0x19DE - IOE Thermal Throttling Custimized T0Level Value + Custimized IOE T0Level value. +**/ + UINT16 IoeT0Level; + +/** Offset 0x19E0 - IOE Thermal Throttling Custimized T1Level Value + Custimized IOE T1Level value. +**/ + UINT16 IoeT1Level; + +/** Offset 0x19E2 - IOE Thermal Throttling Custimized T2Level Value + Custimized IOE T2Level value. +**/ + UINT16 IoeT2Level; + +/** Offset 0x19E4 - Enable IOE Thermal Throttle + Enable thermal throttle function. + $EN_DIS +**/ + UINT8 IoeTTEnable; + +/** Offset 0x19E5 - IOE Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 IoeTTLock; + +/** Offset 0x19E6 - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + UINT8 PchDmiTsawEn; + +/** Offset 0x19E7 - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + UINT8 DmiSuggestedSetting; + +/** Offset 0x19E8 - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS0TW; + +/** Offset 0x19E9 - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS1TW; + +/** Offset 0x19EA - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS2TW; + +/** Offset 0x19EB - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS3TW; + +/** Offset 0x19EC - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x19ED - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x19EE - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x19EF - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x19F0 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x19F1 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x19F2 - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x19F3 - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x19F4 - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x19F5 - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x19F6 - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x19F7 - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x19F8 - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x19F9 +**/ + UINT8 Rsvd310; + +/** Offset 0x19FA - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x19FC - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x1A0C - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x1A16 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x1A17 +**/ + UINT8 Rsvd320[1]; + +/** Offset 0x1A18 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x1A1C - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x1A20 - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x1A24 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x1A25 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x1A26 - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x1A27 +**/ + UINT8 Rsvd330[5]; + +/** Offset 0x1A2C +**/ + UINT8 UnusedUpdSpace1[4]; + +/** Offset 0x1A30 - BgpdtHash[4] + BgpdtHash values +**/ + UINT64 BgpdtHash[4]; + +/** Offset 0x1A50 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x1A54 +**/ + UINT8 Rsvd340[4]; + +/** Offset 0x1A58 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x1A60 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + UINT64 SendEcCmd; + +/** Offset 0x1A68 - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + UINT8 EcCmdProvisionEav; + +/** Offset 0x1A69 - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + UINT8 EcCmdLock; + +/** Offset 0x1A6A +**/ + UINT8 Rsvd350[6]; + +/** Offset 0x1A70 - EcProvisionEav + EcProvisionEav function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8 + *ReturnValue); @endcode +**/ + UINT64 EcProvisionEav; + +/** Offset 0x1A78 - EcBiosGuardCmdLock + EcBiosGuardCmdLock function pointer. \n + @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode +**/ + UINT64 EcBiosGuardCmdLock; + +/** Offset 0x1A80 - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x1A81 +**/ + UINT8 Rsvd360; + +/** Offset 0x1A82 - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x1A84 - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x1A86 +**/ + UINT8 Rsvd370[2]; + +/** Offset 0x1A88 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT32 SiSsidTablePtr; + +/** Offset 0x1A8C - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x1A8E - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x1A9E - SATA RST Interrupt Mode + Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. + 0:Msix, 1:Msi, 2:Legacy +**/ + UINT8 SataRstInterrupt; + +/** Offset 0x1A9F - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x1AA0 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x1AA1 - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x1AA2 - PchDmiCwbEnable + Central Write Buffer feature configurable and enabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x1AA3 - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x1AA4 - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x1AA5 - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x1AA6 - PMC ADR enable + Enable/disable asynchronous DRAM refresh + $EN_DIS +**/ + UINT8 PmcAdrEn; + +/** Offset 0x1AA7 - PMC ADR timer configuration enable + Enable/disable ADR timer configuration + $EN_DIS +**/ + UINT8 PmcAdrTimerEn; + +/** Offset 0x1AA8 - PMC ADR phase 1 timer value + Enable/disable ADR timer configuration +**/ + UINT8 PmcAdrTimer1Val; + +/** Offset 0x1AA9 - PMC ADR phase 1 timer multiplier value + Specify the multiplier value for phase 1 ADR timer +**/ + UINT8 PmcAdrMultiplier1Val; + +/** Offset 0x1AAA - PMC ADR host reset partition enable + Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message + $EN_DIS +**/ + UINT8 PmcAdrHostPartitionReset; + +/** Offset 0x1AAB - PMC ADR source select override enable + Tells the FSP to update the source select with platform value + $EN_DIS +**/ + UINT8 PmcAdrSrcOverride; + +/** Offset 0x1AAC - PMC ADR source selection + Specify which sources should cause ADR flow +**/ + UINT32 PmcAdrSrcSel; + +/** Offset 0x1AB0 - PMC WDT enable + Enable/disable PMC WDT configuration + $EN_DIS +**/ + UINT8 PmcWdtTimerEn; + +/** Offset 0x1AB1 - PCIe RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PcieClockGating[29]; + +/** Offset 0x1ACE - PCIe RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PciePowerGating[29]; + +/** Offset 0x1AEB - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 PcieFomsCp[29]; + +/** Offset 0x1B08 - PCIe GPIO Assertion in Link Down + Describes whether the PCIe GPIO Assertion in Link Down programming is enabled for + each root portby platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 LinkDownGpios[29]; + +/** Offset 0x1B25 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x1B2F - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x1B39 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x1B43 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x1B4D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x1B57 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x1B61 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x1B6B - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x1B75 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x1B76 - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x1B77 - Enable/Disable GT Configuration + Enable(Default): Configure GT for use, Disable: Skip GT Configuration + $EN_DIS +**/ + UINT8 ConfigureGT; + +/** Offset 0x1B78 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x1B79 - Disable Turbo GT + 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency + $EN_DIS +**/ + UINT8 DisableTurboGt; + +/** Offset 0x1B7A - Enable RC1p GT frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pGtFreqEnable; + +/** Offset 0x1B7B - Enable RC1p Media frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 RC1pMediaFreqEnable; + +/** Offset 0x1B7C - Enable TSN Multi-VC + Enable/disable Multi Virtual Channels(VC) in TSN. + $EN_DIS +**/ + UINT8 PchTsnMultiVcEnable; + +/** Offset 0x1B7D - PMC Limit Powergating + Enable/disable Limit PSF powergating to C3 and deeper states + $EN_DIS +**/ + UINT8 PmcLimitC3AndDeeperWA; + +/** Offset 0x1B7E +**/ + UINT8 Rsvd380[10]; + +/** Offset 0x1B88 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x1B8C - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x1B90 - Enable/Disable Media Configuration + Enable(Default): Configure Media for use, Disable: Skip Media Configuration + $EN_DIS +**/ + UINT8 ConfigureMedia; + +/** Offset 0x1B91 - ITbt Usb4CmMode value + ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM +**/ + UINT8 Usb4CmMode; + +/** Offset 0x1B92 +**/ + UINT8 Rsvd390[2]; + +/** Offset 0x1B94 - HorizontalResolution for PEI Logo + HorizontalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 HorizontalResolution; + +/** Offset 0x1B98 - VerticalResolution for PEI Logo + VerticalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 VerticalResolution; + +/** Offset 0x1B9C - Enable/Disable IGFX Media Standby + Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby + $EN_DIS +**/ + UINT8 MediaStandby; + +/** Offset 0x1B9D - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + UINT8 SaPostMemTestRsvd[32]; + +/** Offset 0x1BBD +**/ + UINT8 SaFspsUpdRsvd[32]; + +/** Offset 0x1BDD - RSR feature + Enable or Disable RSR feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableRsr; + +/** Offset 0x1BDE - ReservedCpuPostMem1 + Reserved for CPU Post-Mem 1 + $EN_DIS +**/ + UINT8 ReservedCpuPostMem1[4]; + +/** Offset 0x1BE2 - Enable or Disable HWP + Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the + CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: + Enable; + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x1BE3 - Package Long duration turbo mode time + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. Valid values(Unit + in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , + 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x1BE4 - Short Duration Turbo Mode + Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program + the default values for Power Limit 2. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x1BE5 - Turbo settings Lock + Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT + MSR will be locked and a reset will be required to unlock the register. 0: Disable; + 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x1BE6 - Package PL3 time window + Power Limit 3 Time Window value in Milli seconds. Indicates the time window over + which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves + the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, + 28, 32, 40, 48, 56, 64. +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x1BE7 - Package PL3 Duty Cycle + Specify the duty cycle in percentage that the CPU is required to maintain over the + configured time window. Range is 0-100. +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x1BE8 - Package PL3 Lock + Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled + PL3 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x1BE9 - Package PL4 Lock + Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled + PL4 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x1BEA - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts. Default = 0h. +**/ + UINT8 TccActivationOffset; + +/** Offset 0x1BEB - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1. 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetClamp; + +/** Offset 0x1BEC - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x1BED - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table. Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x1BEE - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom1PowerLimit1Time; + +/** Offset 0x1BEF - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom1TurboActivationRatio; + +/** Offset 0x1BF0 - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom1ConfigTdpControl; + +/** Offset 0x1BF1 - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom2PowerLimit1Time; + +/** Offset 0x1BF2 - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom2TurboActivationRatio; + +/** Offset 0x1BF3 - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom2ConfigTdpControl; + +/** Offset 0x1BF4 - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom3PowerLimit1Time; + +/** Offset 0x1BF5 - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom3TurboActivationRatio; + +/** Offset 0x1BF6 - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom3ConfigTdpControl; + +/** Offset 0x1BF7 - ConfigTdp mode settings Lock + cTDP(Assured Power) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. + Note: When CTDP(Assured Power) Lock is enabled Custom ConfigTDP Count will be forced + to 1 and Custom ConfigTDP Boot Index will be forced to 0. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x1BF8 - Load Configurable TDP SSDT + Enables cTDP(Assured Power) control via runtime ACPI BIOS methods. This 'BIOS only' + feature does not require EC or driver support. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x1BF9 - PL1 Enable value + Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it + activates the PL1 value to be used by the processor to limit the average power + of given time window. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x1BFA - PL1 timewindow + Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to + 128. 0 = default values. Indicates the time window over which Platform Processor + Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to + 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x1BFB - PL2 Enable Value + Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS + will program the default values for Platform Power Limit 2. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x1BFC - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x1BFD - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x1BFE - Enable or Disable Monitor /MWAIT instructions + Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner + should not set in MWAIT Loop. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x1BFF - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x1C00 - AP Idle Manner of waiting for SIPI + AP threads Idle Manner for waiting signal to run. 1: HALT loop; 2: MWAIT loop; + 3: RUN loop. + 1: HALT loop, 2: MWAIT loop, 3: RUN loop +**/ + UINT8 ApIdleManner; + +/** Offset 0x1C01 - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x1C02 - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x1C03 - Enable or Disable Intel SpeedStep Technology + Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x1C04 - Enable or Disable Energy Efficient P-state + Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access + to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support + for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS + MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is + supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x1C05 - Enable or Disable Energy Efficient Turbo + Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically + lower the turbo frequency to increase efficiency. Recommended only to disable in + overclocking situations where turbo frequency must remain constant. Otherwise, + leave enabled. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x1C06 - Enable or Disable T states + Enable or Disable T states; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x1C07 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x1C08 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableProcHotOut; + +/** Offset 0x1C09 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcHotResponse; + +/** Offset 0x1C0A - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x1C0B - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x1C0C - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x1C0D - Enable or Disable CPU power states (C-states) + Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not + 100% utilized. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x1C0E - Configure C-State Configuration Lock + Configure MSR to CFG Lock bit. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x1C0F - Enable or Disable Enhanced C-states + Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores + enter C-State. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x1C10 - Enable or Disable Package Cstate Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x1C11 - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x1C12 - Enable or Disable CState-Pre wake + Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x1C13 - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x1C14 - Enable or Disable IO to MWAIT redirection + When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset + to MWAIT(offset). 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CstCfgCtrIoMwaitRedirection; + +/** Offset 0x1C15 - Set the Max Pkg Cstate + Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. + Auto: Initializes to deepest available Package C State Limit. Valid values 0 - + C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - + CPU Default, 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x1C16 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: + Round robin; 2: Hash vector; 7: No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x1C17 - Lock prochot configuration + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ProcHotLock; + +/** Offset 0x1C18 - Configuration for boot TDP selection + cTDP(Assured Power) Mode as Nominal/Level1/Level2/Deactivate TDP(Base Power) selection. + Deactivate option will set MSR to Nominal and MMIO to Zero. 0: TDP(Base Power) + Nominal; 1: TDP(Base Power) Down; 2: TDP(Base Power) Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x1C19 - Max P-State Ratio + Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x1C1A - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x1C42 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x1C52 +**/ + UINT8 Rsvd400[2]; + +/** Offset 0x1C54 - Package Long duration turbo mode power limit + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor + Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid + Range 0 to 32767. +**/ + UINT32 PowerLimit1; + +/** Offset 0x1C58 - Package Short duration turbo mode power limit + Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor + Base Power (TDP). Processor applies control policies such that the package power + does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x1C5C - Package PL3 power limit + Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value + must be between Max and Min Power Limits. Other SKUs: This value must be between + Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves + the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit3; + +/** Offset 0x1C60 - Package PL4 power limit + Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based + on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767. +**/ + UINT32 PowerLimit4; + +/** Offset 0x1C64 - Package PL4 boost configuration + Configure Power Limit 4 Boost in Watts. Valid Range 0 to 1023 in step size of 1 + Watt. The value 0 means disable. +**/ + UINT16 PowerLimit4Boost; + +/** Offset 0x1C66 +**/ + UINT8 Rsvd410[2]; + +/** Offset 0x1C68 - Tcc Offset Time Window for RATL +**/ + UINT32 TccOffsetTimeWindowForRatl; + +/** Offset 0x1C6C - Short term Power Limit value for custom cTDP level 1 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x1C70 - Long term Power Limit value for custom cTDP level 1 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x1C74 - Short term Power Limit value for custom cTDP level 2 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom2PowerLimit1; + +/** Offset 0x1C78 - Long term Power Limit value for custom cTDP level 2 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom2PowerLimit2; + +/** Offset 0x1C7C - Short term Power Limit value for custom cTDP level 3 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom3PowerLimit1; + +/** Offset 0x1C80 - Long term Power Limit value for custom cTDP level 3 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom3PowerLimit2; + +/** Offset 0x1C84 - Platform PL1 power + Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new PL1 value for the Package + RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range + 0 to 32767. +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x1C88 - Platform PL2 power + Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value + for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x1C8C - CCF AutoGV + Enable/Disable CCF AutoGV; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CcfAutoGv; + +/** Offset 0x1C8D - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x1C8E - Enable or Disable Three Strike Counter + Enable (default): Three Strike counter will be incremented. Disable: Prevents Three + Strike counter from incrementing; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThreeStrikeCounter; + +/** Offset 0x1C8F - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x1C90 - ReservedCpuPostMem2 + Reserved for CPU Post-Mem 2 + $EN_DIS +**/ + UINT8 ReservedCpuPostMem2[4]; + +/** Offset 0x1C94 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x1C95 - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x1C96 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x1C97 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x1C98 - Enable or Disable Per Core P State OS control + Enable/Disable Per Core P state OS control mode. When set, the highest core request + is used for all other core requests. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnablePerCorePState; + +/** Offset 0x1C99 - Enable or Disable HwP Autonomous Per Core P State OS control + Disable Autonomous PCPS Autonomous will request the same value for all cores all + the time. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x1C9A - Enable or Disable HwP Autonomous EPP Grouping + Enable EPP grouping Autonomous will request the same values for all cores with same + EPP. Disable EPP grouping autonomous will not necessarily request same values for + all cores with same EPP. 0: Disable ; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x1C9B - Enable Configurable TDP + Applies cTDP(Assured Power) initialization settings based on non-cTDP(Assured Power) + or cTDP(Assured Power). Default is 1: Applies to cTDP(Assured Power); if 0 then + applies non-cTDP(Assured Power) and BIOS will bypass cTDP(Assured Power) initialzation flow + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x1C9C - Misc Power Management MSR Lock + Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, 1: + Enable + $EN_DIS +**/ + UINT8 HwpLock; + +/** Offset 0x1C9D - Dual Tau Boost + Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W + sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 DualTauBoost; + +/** Offset 0x1C9E - Response Mode + Use Response Mode to adjust Psys_PL3 power reduction behavior. Battery-enabled systems + use Gradual Power Reduction. 0: Gradual Power Reduction ; 1: Aggressive + Power Reduction + 0: Gradual Power Reduction, 1: Aggressive Power Reduction +**/ + UINT8 StepDownMode; + +/** Offset 0x1C9F - Power Floor Managment for SOC + Option to disable Power Floor Managment for SOC. Disabling this might effectively + raise power floor of the SoC and may lead to stability issues. 0: Disable, 1: + Enable + $EN_DIS +**/ + UINT8 PowerFloorManagement; + +/** Offset 0x1CA0 - Power Floor Disaplay Disconnect + SoC can disconnect secondary/external display to lower SoC floor power (Default + enabled). 0: Disable: Display disconnect will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorDisplayDisconnect; + +/** Offset 0x1CA1 - Resource Priority Feature + Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 EnableRp; + +/** Offset 0x1CA2 - Power Floor PCIe Gen Downgrade + SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0: + Disable: Reduction in PCIe gen speed will not be used by SoC., 1: Enable + $EN_DIS +**/ + UINT8 PowerFloorPcieGenDowngrade; + +/** Offset 0x1CA3 - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + UINT8 ReservedCpuPostMemTest[13]; + +/** Offset 0x1CB0 +**/ + UINT8 SecurityPostMemRsvd[16]; + +/** Offset 0x1CC0 - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x1CC1 - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x1CC2 - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x1CC3 - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x1CC4 - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x1CC5 - CSE Data Resilience Support + 0: Disable CSE Data Resilience Support. 1: Enable CSE Data Resilience Support. + $EN_DIS +**/ + UINT8 CseDataResilience; + +/** Offset 0x1CC6 - MePostMemRsvd + Reserved for ME Post-Mem + $EN_DIS +**/ + UINT8 MePostMemRsvd[16]; + +/** Offset 0x1CD6 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x1CD7 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x1CD8 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x1CD9 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x1CDA +**/ + UINT8 Rsvd420[2]; + +/** Offset 0x1CDC - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[29]; + +/** Offset 0x1D16 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[29]; + +/** Offset 0x1D50 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[29]; + +/** Offset 0x1D6D - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[29]; + +/** Offset 0x1D8A - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[29]; + +/** Offset 0x1DC4 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[29]; + +/** Offset 0x1DE1 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29]; + +/** Offset 0x1DFE - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[29]; + +/** Offset 0x1E38 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[29]; + +/** Offset 0x1E55 +**/ + UINT8 Rsvd430[1]; + +/** Offset 0x1E56 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[29]; + +/** Offset 0x1E90 - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x1E91 - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x1E92 - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x1E93 - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x1E94 - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x1E95 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x1E96 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcPchLpmS0ixSubStateEnableMask; + +/** Offset 0x1E97 - PCH PMC ER Debug mode + Disable/Enable Energy Reporting Debug Mode. + $EN_DIS +**/ + UINT8 PchPmErDebugMode; + +/** Offset 0x1E98 - CPPM Forced Alignment Enable + Enable/Disable CPPM Force Alignment. When enabled, PMC allows stalling of the backbone + or blocking the DMI transmit arbiter + $EN_DIS +**/ + UINT8 CppmFaEn; + +/** Offset 0x1E99 - PCH Lan WOL Fast Support + Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm. + $EN_DIS +**/ + UINT8 PchLanWOLFastSupport; + +/** Offset 0x1E9A - Platform ATX Telemetry Unit + Set ATX Telemetry Unit in Watts or Percentage; 0: Watts; 1: Percent + $EN_DIS +**/ + UINT8 PlatformAtxTelemetryUnit; + +/** Offset 0x1E9B - PCIE RP LTR Override Spec Complaint + Override LTR based on Ep capability. +**/ + UINT8 PcieRpLtrOverrideSpecComplaint[29]; + +/** Offset 0x1EB8 +**/ + UINT8 PchMeFspsUpdRsvd[71]; + +/** Offset 0x1EFF - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x1F00 - Turbo Ratio Limit Ratio array + Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max + is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio + Limit Ratio0 must be greater than or equal all other ratio values. If this value + is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio + Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit + Ratio1 must be <= to Turbo Ratio Limit Ratio0~6. +**/ + UINT8 TurboRatioLimitRatio[8]; + +/** Offset 0x1F08 - Turbo Ratio Limit Num Core array + Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio + is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored. +**/ + UINT8 TurboRatioLimitNumCore[8]; + +/** Offset 0x1F10 - ATOM Turbo Ratio Limit Ratio array + Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective + of the core extension mode), the core range is defined in E-core Turbo Ratio Limit + CoreCount0-7. +**/ + UINT8 AtomTurboRatioLimitRatio[8]; + +/** Offset 0x1F18 - ATOM Turbo Ratio Limit Num Core array + Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo + ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry + is ignored. +**/ + UINT8 AtomTurboRatioLimitNumCore[8]; + +/** Offset 0x1F20 +**/ + UINT8 Rsvd440[4]; + +/** Offset 0x1F24 - FspEventHandler + Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. +**/ + UINT32 FspEventHandler; + +/** Offset 0x1F28 - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA + $EN_DIS +**/ + UINT8 EnableTcssCovTypeA[4]; + +/** Offset 0x1F2C +**/ + UINT8 Rsvd450[16]; + +/** Offset 0x1F3C +**/ + UINT8 ReservedFspsUpd[12]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x1F48 +**/ + UINT8 Rsvd600[6]; + +/** Offset 0x1F4E +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FsptUpd.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FsptUpd.h new file mode 100644 index 00000000..228d9575 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/FsptUpd.h @@ -0,0 +1,420 @@ +/** @file + +Copyright (c) 2025, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0040 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0044 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0048 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x004C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0050 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0060 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0061 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0062 - PcdSerialIoUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIoUartMode; + +/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT + Select SerialIo Uart Controller Powergating mode + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 PcdSerialIoUartPowerGating; + +/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIoUartBaudRate; + +/** Offset 0x0068 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0070 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0074 - PcdSerialIoUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIoUartParity; + +/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIoUartDataBits; + +/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIoUartStopBits; + +/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIoUartAutoFlow; + +/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartRxPinMux; + +/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartTxPinMux; + +/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIoUartRtsPinMux; + +/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIoUartCtsPinMux; + +/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 PcdSerialIoUartDebugMmioBase; + +/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT + Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0 +**/ + UINT32 PcdSerialIoUartDebugPciCfgBase; + +/** Offset 0x0090 - PcdLpcUartDebugEnable + Enable to initialize LPC Uart device in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcdLpcUartDebugEnable; + +/** Offset 0x0091 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0092 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0093 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0094 - PcdSerialIo2ndUartEnable + Enable Additional SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIo2ndUartEnable; + +/** Offset 0x0095 - PcdSerialIo2ndUartNumber + Select SerialIo Uart Controller Number + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIo2ndUartNumber; + +/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIo2ndUartMode; + +/** Offset 0x0097 +**/ + UINT8 Rsvd020[1]; + +/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIo2ndUartBaudRate; + +/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIo2ndUartParity; + +/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIo2ndUartDataBits; + +/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIo2ndUartStopBits; + +/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIo2ndUartAutoFlow; + +/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART +**/ + UINT32 PcdSerialIo2ndUartRxPinMux; + +/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART +**/ + UINT32 PcdSerialIo2ndUartTxPinMux; + +/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIo2ndUartRtsPinMux; + +/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIo2ndUartCtsPinMux; + +/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode + = SerialIoUartPci. +**/ + UINT32 PcdSerialIo2ndUartMmioBase; + +/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT + Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0 +**/ + UINT32 PcdSerialIo2ndUartPciCfgBase; + +/** Offset 0x00B8 +**/ + UINT32 TopMemoryCacheSize; + +/** Offset 0x00BC - FspDebugHandler + Optional pointer to the boot loader's implementation of FSP_DEBUG_HANDLER. +**/ + UINT32 FspDebugHandler; + +/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 PcdSerialIoSpiCsPolarity[2]; + +/** Offset 0x00C2 - Serial Io SPI Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 PcdSerialIoSpiCsEnable[2]; + +/** Offset 0x00C4 - Serial Io SPI Device Mode + When mode is set to Pci, controller is initalized in early stage. Available modes: + 0:SerialIoSpiDisabled, 1:SerialIoSpiPci. +**/ + UINT8 PcdSerialIoSpiMode; + +/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output + Sets Default CS as Output. Available options: 0:CS0, 1:CS1 +**/ + UINT8 PcdSerialIoSpiDefaultCsOutput; + +/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW +**/ + UINT8 PcdSerialIoSpiCsMode; + +/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High + Sets Default CS State Low or High. Available options: 0:Low, 1:High +**/ + UINT8 PcdSerialIoSpiCsState; + +/** Offset 0x00C8 - Serial Io SPI Device Number + Select which Serial Io SPI controller is initalized in early stage. +**/ + UINT8 PcdSerialIoSpiNumber; + +/** Offset 0x00C9 +**/ + UINT8 Rsvd030[3]; + +/** Offset 0x00CC - Serial Io SPI Device MMIO Base + Assigns MMIO for Serial Io SPI controller usage in early stage. +**/ + UINT32 PcdSerialIoSpiMmioBase; + +/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing + Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for + possible values. +**/ + UINT32 PcdSerialIoSpiCsPinMux[2]; + +/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing + Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for + possible values. +**/ + UINT32 PcdSerialIoSpiClkPinMux; + +/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing + Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO* + for possible values. +**/ + UINT32 PcdSerialIoSpiMisoPinMux; + +/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing + Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI* + for possible values. +**/ + UINT32 PcdSerialIoSpiMosiPinMux; + +/** Offset 0x00E4 - Serial Io I2C Device MMIO Base + Assigns MMIO for Serial Io I2C controller usage in early stage. +**/ + UINT32 PcdSerialIoI2cMmioBase; + +/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin + Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values. +**/ + UINT32 PcdSerialIoI2cSdaPin; + +/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin + Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values. +**/ + UINT32 PcdSerialIoI2cSclPin; + +/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PcdSerialIoI2cPadsTerm; + +/** Offset 0x00F1 - Serial Io I2c Controller Number + Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF + 0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable +**/ + UINT8 PcdSerialIoI2cNumber; + +/** Offset 0x00F2 +**/ + UINT8 ReservedFsptUpd1[6]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_ARCH_UPD FsptArchUpd; + +/** Offset 0x0040 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0060 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x00F8 +**/ + UINT8 Rsvd3[6]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioConfig.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioConfig.h new file mode 100644 index 00000000..20ce6759 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioConfig.h @@ -0,0 +1,349 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + @copyright + INTEL CONFIDENTIAL + Copyright 2014 - 2017 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enabled. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 17; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault = 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pad. + If GPIO is set to one of NativeX modes then following settings are not applicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chosen ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi = 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver. + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) + **/ + GpioHostOwnGpio = 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input enabled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). + This type of GPIO Driver interrupt doesn't have any additional routing setting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + + + GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified + + /// + /// New GPIO reset configuration options + /// + /** + Resume Reset (RSMRST) + GPP: PadRstCfg = 00b = "Powergood" + GPD: PadRstCfg = 11b = "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset = 0x01, + /** + Host Deep Reset + PadRstCfg = 01b = "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset = 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg = 10b = "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset = 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg = 00b = "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset = 0x07 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Set GPIO termination and Pad Tolerance (applicable only for some pads) + Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. +**/ +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative = 0x1F, + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value +#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioLockPadConfig and GpioLockOutputState can be OR'ed. + Lock settings reset is in Powergood domain. Care must be taken when using this setting + as fields it locks may be reset by a different signal and can be controllable + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides + functions which allow to unlock a GPIO pad. +**/ +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensions + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and native usage). + The override takes place at the internal pad state directly from buffer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioSampleDef.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioSampleDef.h new file mode 100644 index 00000000..b8b4f559 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/GpioSampleDef.h @@ -0,0 +1,382 @@ +/** @file + +Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __GPIOCONFIG_H__ +#define __GPIOCONFIG_H__ +#include +#include +#include + +/* + SKL LP GPIO pins + Use below for functions from PCH GPIO Lib which + require GpioPad as argument. Encoding used here + has all information required by library functions +*/ +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +//Sample GPIO Table + +static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] = +{ +//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 +//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 +//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 +//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 +//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ +//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N + {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N +//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK + {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N + {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R +//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N + {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N + {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL + {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N + {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR + {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR + {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0 + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1 + {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N + // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N + // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N + // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N + // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N + // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB + {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N + {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN + {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N + {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N + {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N + {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 + {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N + {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK + {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD + {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N + {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA + {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL + {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA + {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N + {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N + {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK + {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO + {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI + {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA + {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH + {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA + {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1 + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1 + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0 + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0 + {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2 + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3 + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R + {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N + {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N + {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N + {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N + {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0 + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1 + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2 + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3 + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4 + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5 + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6 + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7 + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD + {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0 + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1 + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2 + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3 + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N + {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table +}; + +#endif //_GPIO_CONFIG_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h new file mode 100644 index 00000000..8813e3db --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h @@ -0,0 +1,59 @@ +/** @file + Definitions for Hob Usage data HOB + +@copyright + INTEL CONFIDENTIAL + Copyright 2017 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ + +#ifndef _HOB_USAGE_DATA_HOB_H_ +#define _HOB_USAGE_DATA_HOB_H_ + +extern EFI_GUID gHobUsageDataGuid; + +#pragma pack (push, 1) + +/** + Hob Usage Data Hob + + Revision 1: + - Initial version. +**/ +typedef struct { + EFI_PHYSICAL_ADDRESS EfiMemoryTop; + EFI_PHYSICAL_ADDRESS EfiMemoryBottom; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; + UINTN FreeMemory; +} HOB_USAGE_DATA_HOB; + +#pragma pack (pop) + +#endif // _HOB_USAGE_DATA_HOB_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/MemInfoHob.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/MemInfoHob.h new file mode 100644 index 00000000..61593808 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/MemInfoHob.h @@ -0,0 +1,347 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + +@copyright + INTEL CONFIDENTIAL + Copyright 1999 - 2022 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. + UINT8 Resv[2]; ///< Resv +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status + BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population + BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosCacheInfoHob.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosCacheInfoHob.h new file mode 100644 index 00000000..1fc6fdd3 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosCacheInfoHob.h @@ -0,0 +1,56 @@ +/** @file + Header file for SMBIOS Cache Info HOB + + @copyright + INTEL CONFIDENTIAL + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + System Management BIOS (SMBIOS) Reference Specification v3.1.0 + dated 2016-Nov-16 (DSP0134) + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf +**/ + +#ifndef _SMBIOS_CACHE_INFO_HOB_H_ +#define _SMBIOS_CACHE_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Cache Info HOB Structure +/// +typedef struct { + UINT16 ProcessorSocketNumber; + UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3 + UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE" + UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36 + UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2 + UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown. + UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3 + UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4 + UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5 + // + // Add for smbios 3.1.0 + // + UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_CACHE_INFO; +#pragma pack() + +#endif // _SMBIOS_CACHE_INFO_HOB_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h new file mode 100644 index 00000000..a7e9a7f1 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Include/SmbiosProcessorInfoHob.h @@ -0,0 +1,67 @@ +/** @file + Header file for SMBIOS Processor Info HOB + + @copyright + INTEL CONFIDENTIAL + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + System Management BIOS (SMBIOS) Reference Specification v3.1.0 + dated 2016-Nov-16 (DSP0134) + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf +**/ + +#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_ +#define _SMBIOS_PROCESSOR_INFO_HOB_H_ + +#include +#include + +#pragma pack(1) +/// +/// SMBIOS Processor Info HOB Structure +/// +typedef struct { + UINT16 TotalNumberOfSockets; + UINT16 CurrentSocketNumber; + UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1 + /** This info is used for both ProcessorFamily and ProcessorFamily2 fields + See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2 + **/ + UINT16 ProcessorFamily; + UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer + UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3 + UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer + UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4 + UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown. + UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot + UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot + UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21 + UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5 + /** This info is used for both CoreCount & CoreCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.6 + **/ + UINT16 CoreCount; + /** This info is used for both CoreEnabled & CoreEnabled2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.7 + **/ + UINT16 EnabledCoreCount; + /** This info is used for both ThreadCount & ThreadCount2 fields + See detailed description in SMBIOS Spec v3.1 Section 7.5.8 + **/ + UINT16 ThreadCount; + UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9 + /** + String Buffer - each string terminated by NULL "0x00" + String buffer terminated by double NULL "0x0000" + **/ +} SMBIOS_PROCESSOR_INFO; +#pragma pack() + +#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_ diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c new file mode 100644 index 00000000..7ae4850b --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.c @@ -0,0 +1,49 @@ +/** @file + Library instance to list all DynamicEx PCD FSP consumes. + No real functionality. + +@copyright + INTEL CONFIDENTIAL + Copyright 2019 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ + +#include + +/** + Do nothing function. + +**/ +VOID +FspPcdListLibNull ( + VOID + ) +{ + return; +} diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf new file mode 100644 index 00000000..b87669a2 --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf @@ -0,0 +1,86 @@ +## @file +# Library instance to list all DynamicEx PCD FSP consumes. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright 2019 - 2021 Intel Corporation. +# +# The source code contained or described herein and all documents related to the +# source code ("Material") are owned by Intel Corporation or its suppliers or +# licensors. Title to the Material remains with Intel Corporation or its suppliers +# and licensors. The Material may contain trade secrets and proprietary and +# confidential information of Intel Corporation and its suppliers and licensors, +# and is protected by worldwide copyright and trade secret laws and treaty +# provisions. No part of the Material may be used, copied, reproduced, modified, +# published, uploaded, posted, transmitted, distributed, or disclosed in any way +# without Intel's prior express written permission. +# +# No license under any patent, copyright, trade secret or other intellectual +# property right is granted to or conferred upon you by disclosure or delivery +# of the Materials, either expressly, by implication, inducement, estoppel or +# otherwise. Any license under such intellectual property rights must be +# express and approved by Intel in writing. +# +# Unless otherwise agreed by Intel in writing, you may not remove or alter +# this notice or any other notice embedded in Materials by Intel or +# Intel's suppliers or licensors in any way. +# +# This file contains an 'Intel Peripheral Driver' and is uniquely identified as +# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under +# the terms of your license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the license agreement. +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = FspPcdListLibNull + FILE_GUID = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = NULL +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + ClientOneSiliconPkg/SiPkg.dec + +[Sources] + FspPcdListLibNull.c + +[Pcd] + # + # List all the DynamicEx PCDs that FSP will consume. + # FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are + # built into PCD database. + # + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONSUMES + diff --git a/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec new file mode 100644 index 00000000..902ab63c --- /dev/null +++ b/fsp/arl-s/5083.81/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec @@ -0,0 +1,43 @@ +## @file +# Component description file for MeteorLake Fsp Bin package. +# +# @copyright +# INTEL CONFIDENTIAL +# Copyright 2016 - 2019 Intel Corporation. +# +# The source code contained or described herein and all documents related to the +# source code ("Material") are owned by Intel Corporation or its suppliers or +# licensors. Title to the Material remains with Intel Corporation or its suppliers +# and licensors. The Material may contain trade secrets and proprietary and +# confidential information of Intel Corporation and its suppliers and licensors, +# and is protected by worldwide copyright and trade secret laws and treaty +# provisions. No part of the Material may be used, copied, reproduced, modified, +# published, uploaded, posted, transmitted, distributed, or disclosed in any way +# without Intel's prior express written permission. +# +# No license under any patent, copyright, trade secret or other intellectual +# property right is granted to or conferred upon you by disclosure or delivery +# of the Materials, either expressly, by implication, inducement, estoppel or +# otherwise. Any license under such intellectual property rights must be +# express and approved by Intel in writing. +# +# Unless otherwise agreed by Intel in writing, you may not remove or alter +# this notice or any other notice embedded in Materials by Intel or +# Intel's suppliers or licensors in any way. +# +# This file contains an 'Intel Peripheral Driver' and is uniquely identified as +# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under +# the terms of your license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the license agreement. +# +# @par Specification +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = MeteorLakeFspBinPkg + PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06 + PACKAGE_VERSION = 1.02 + +[Includes] + Include diff --git a/models/bonw16/IntelGopDriver.inf b/models/bonw16/IntelGopDriver.inf new file mode 100644 index 00000000..39b2eb91 --- /dev/null +++ b/models/bonw16/IntelGopDriver.inf @@ -0,0 +1,9 @@ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IntelGopDriver + FILE_GUID = 767222f4-a9f4-41ba-9faa-edaa1405a486 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + +[Binaries.X64] + PE32|IntelGopDriver.efi|* diff --git a/models/bonw16/MeteorLakeFspBinPkg b/models/bonw16/MeteorLakeFspBinPkg new file mode 120000 index 00000000..07b7d10c --- /dev/null +++ b/models/bonw16/MeteorLakeFspBinPkg @@ -0,0 +1 @@ +../../fsp/arl-s/5083.81/MeteorLakeFspBinPkg \ No newline at end of file diff --git a/models/bonw16/chip.txt b/models/bonw16/chip.txt new file mode 100644 index 00000000..ef167119 --- /dev/null +++ b/models/bonw16/chip.txt @@ -0,0 +1 @@ +GD25Q256D diff --git a/models/bonw16/coreboot.config b/models/bonw16/coreboot.config new file mode 100644 index 00000000..45052f93 --- /dev/null +++ b/models/bonw16/coreboot.config @@ -0,0 +1,27 @@ +CONFIG_VENDOR_SYSTEM76=y +CONFIG_BOARD_SYSTEM76_BONW16=y +CONFIG_CCACHE=y +CONFIG_CONSOLE_SERIAL=n +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom" +CONFIG_HAVE_IFD_BIN=y +CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom" +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)" +CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000 +CONFIG_POST_IO=n +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_V2=y +CONFIG_TPM_PPI=y +CONFIG_USE_OPTION_TABLE=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +#CONFIG_CONSOLE_SYSTEM76_EC=y + +# Custom FSP +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/MeteorLakeFspBinPkg/Include" diff --git a/models/bonw16/ec.config b/models/bonw16/ec.config new file mode 100644 index 00000000..b7d1d563 --- /dev/null +++ b/models/bonw16/ec.config @@ -0,0 +1 @@ +BOARD=system76/bonw16 diff --git a/models/bonw16/edk2.config b/models/bonw16/edk2.config new file mode 100644 index 00000000..b2378083 --- /dev/null +++ b/models/bonw16/edk2.config @@ -0,0 +1,9 @@ +BOOTLOADER=COREBOOT +DISABLE_SERIAL_TERMINAL=TRUE +PLATFORM_BOOT_TIMEOUT=2 +PS2_KEYBOARD_ENABLE=TRUE +SECURE_BOOT_ENABLE=TRUE +SERIAL_DRIVER_ENABLE=FALSE +SHELL_TYPE=NONE +TPM_ENABLE=TRUE +#SYSTEM76_EC_LOGGING=TRUE From dd930cd9d34959383acf8cd5c27d0f13d8ac4401 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 24 Mar 2025 14:04:40 -0600 Subject: [PATCH 3/7] Add bonw16 microcode --- models/bonw16/microcode.rom | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 models/bonw16/microcode.rom diff --git a/models/bonw16/microcode.rom b/models/bonw16/microcode.rom new file mode 100644 index 00000000..6e0572f5 --- /dev/null +++ b/models/bonw16/microcode.rom @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ef6739dfa35109ab841cf9511305340d23ad49073d7078a74fa56afb707bb02c +size 179200 From 6f0b1206dba520b035440a3fbb0e4e73c4caa224 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 24 Mar 2025 14:09:10 -0600 Subject: [PATCH 4/7] Update coreboot --- coreboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/coreboot b/coreboot index de349801..1fda16f8 160000 --- a/coreboot +++ b/coreboot @@ -1 +1 @@ -Subproject commit de349801ce63a7256185ce726043861e033d9204 +Subproject commit 1fda16f8d00aef2f039dd613db223515f144685e From a65def0eacaf5a61b5d7921eccc541ec01c3ae3f Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 24 Mar 2025 15:54:27 -0600 Subject: [PATCH 5/7] Update EC --- ec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ec b/ec index fdefd165..8a4753ca 160000 --- a/ec +++ b/ec @@ -1 +1 @@ -Subproject commit fdefd165e12669fbab54739f789a5d154a42868f +Subproject commit 8a4753ca3737d00e1fb7391731b7d90668f0aeb5 From 240a8efb9a95435a3287ce25a2419843a57e9e09 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 25 Mar 2025 17:45:03 +0000 Subject: [PATCH 6/7] Fix bonw16 coreboot-collector output --- models/bonw16/coreboot-collector.txt | 554 ++++++++++++++++----------- tools/coreboot-collector | 2 +- 2 files changed, 326 insertions(+), 230 deletions(-) diff --git a/models/bonw16/coreboot-collector.txt b/models/bonw16/coreboot-collector.txt index 9da15778..310f4a81 100644 --- a/models/bonw16/coreboot-collector.txt +++ b/models/bonw16/coreboot-collector.txt @@ -42,236 +42,332 @@ PCI Device: 0000:86:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x5781, Revisi PCI Device: 0000:ad:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x5782, Revision 0x00 PCI Device: 0000:d5:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3102, Revision 0x04 ## GPIO ## +ARL-S SOC 800 series PCH -GPP_D0 (0x6E,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff -GPP_D1 (0x6E,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D2 (0x6E,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D3 (0x6E,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D4 (0x6E,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D5 (0x6E,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D6 (0x6E,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D7 (0x6E,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D8 (0x6E,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D9 (0x6E,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D10 (0x6E,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D11 (0x6E,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D12 (0x6E,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D13 (0x6E,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D14 (0x6E,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D15 (0x6E,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D16 (0x6E,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D17 (0x6E,0x22) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D18 (0x6E,0x24) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D19 (0x6E,0x26) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D20 (0x6E,0x28) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D21 (0x6E,0x2A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D22 (0x6E,0x2C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_D23 (0x6E,0x2E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R0 (0x6E,0x32) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R1 (0x6E,0x34) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R2 (0x6E,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R3 (0x6E,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R4 (0x6E,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R5 (0x6E,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R6 (0x6E,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R7 (0x6E,0x40) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R8 (0x6E,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R9 (0x6E,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R10 (0x6E,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R11 (0x6E,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_R12 (0x6E,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J0 (0x6E,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J1 (0x6E,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J2 (0x6E,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J3 (0x6E,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J4 (0x6E,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J5 (0x6E,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J6 (0x6E,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J7 (0x6E,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J8 (0x6E,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J9 (0x6E,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J10 (0x6E,0x62) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J11 (0x6E,0x64) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J12 (0x6E,0x66) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J13 (0x6E,0x68) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J14 (0x6E,0x6A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J15 (0x6E,0x6C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_J16 (0x6E,0x6E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A0 (0x6D,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff -GPP_A1 (0x6D,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A2 (0x6D,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A3 (0x6D,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A4 (0x6D,0x08) 0x21000000 0xffffffff 0xffffffff 0xffffffff -GPP_A5 (0x6D,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A6 (0x6D,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A7 (0x6D,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A8 (0x6D,0x10) 0x21001f00 0xffffffff 0xffffffff 0xffffffff -GPP_A9 (0x6D,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A10 (0x6D,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A11 (0x6D,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_A12 (0x6D,0x18) 0x00000000 0xffffffff 0xffffffff 0xffffffff -GPP_A13 (0x6D,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B0 (0x6D,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B1 (0x6D,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B2 (0x6D,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B3 (0x6D,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B4 (0x6D,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B5 (0x6D,0x40) 0x210000ff 0xffffffff 0xffffffff 0xffffffff -GPP_B6 (0x6D,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B7 (0x6D,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B8 (0x6D,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B9 (0x6D,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B10 (0x6D,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B11 (0x6D,0x4C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B12 (0x6D,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B13 (0x6D,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B14 (0x6D,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B15 (0x6D,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B16 (0x6D,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B17 (0x6D,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B18 (0x6D,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B19 (0x6D,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B20 (0x6D,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_B21 (0x6D,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD0 (0x6C,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff -GPD1 (0x6C,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD2 (0x6C,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD3 (0x6C,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD4 (0x6C,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD5 (0x6C,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD6 (0x6C,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD7 (0x6C,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD8 (0x6C,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD9 (0x6C,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD10 (0x6C,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD11 (0x6C,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPD12 (0x6C,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C0 (0x6B,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C1 (0x6B,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C2 (0x6B,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C3 (0x6B,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C4 (0x6B,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C5 (0x6B,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C6 (0x6B,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C7 (0x6B,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C8 (0x6B,0x22) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C9 (0x6B,0x24) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C10 (0x6B,0x26) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C11 (0x6B,0x28) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C12 (0x6B,0x2A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C13 (0x6B,0x2C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C14 (0x6B,0x2E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C15 (0x6B,0x30) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C16 (0x6B,0x32) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C17 (0x6B,0x34) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C18 (0x6B,0x36) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C19 (0x6B,0x38) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C20 (0x6B,0x3A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C21 (0x6B,0x3C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C22 (0x6B,0x3E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_C23 (0x6B,0x40) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H0 (0x6B,0x42) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H1 (0x6B,0x44) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H2 (0x6B,0x46) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H3 (0x6B,0x48) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H4 (0x6B,0x4A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H5 (0x6B,0x4C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H6 (0x6B,0x4E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H7 (0x6B,0x50) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H8 (0x6B,0x52) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H9 (0x6B,0x54) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H10 (0x6B,0x56) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H11 (0x6B,0x58) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H12 (0x6B,0x5A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H13 (0x6B,0x5C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H14 (0x6B,0x5E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H15 (0x6B,0x60) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H16 (0x6B,0x62) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H17 (0x6B,0x64) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H18 (0x6B,0x66) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_H19 (0x6B,0x68) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_S0 (0x6A,0x00) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S1 (0x6A,0x02) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S2 (0x6A,0x04) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S3 (0x6A,0x06) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S4 (0x6A,0x08) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S5 (0x6A,0x0A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S6 (0x6A,0x0C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_S7 (0x6A,0x0E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E0 (0x6A,0x10) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E1 (0x6A,0x12) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E2 (0x6A,0x14) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E3 (0x6A,0x16) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E4 (0x6A,0x18) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E5 (0x6A,0x1A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E6 (0x6A,0x1C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E7 (0x6A,0x1E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E8 (0x6A,0x20) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E9 (0x6A,0x22) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E10 (0x6A,0x24) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E11 (0x6A,0x26) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E12 (0x6A,0x28) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E13 (0x6A,0x2A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E14 (0x6A,0x2C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E15 (0x6A,0x2E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E16 (0x6A,0x30) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E17 (0x6A,0x32) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E18 (0x6A,0x34) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E19 (0x6A,0x36) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E20 (0x6A,0x38) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_E21 (0x6A,0x3A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K0 (0x6A,0x3E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K1 (0x6A,0x40) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K2 (0x6A,0x42) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K3 (0x6A,0x44) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K4 (0x6A,0x46) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K5 (0x6A,0x48) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K6 (0x6A,0x4A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K7 (0x6A,0x4C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K8 (0x6A,0x4E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K9 (0x6A,0x50) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_K10 (0x6A,0x52) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F0 (0x6A,0x5A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F1 (0x6A,0x5C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F2 (0x6A,0x5E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F3 (0x6A,0x60) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F4 (0x6A,0x62) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F5 (0x6A,0x64) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F6 (0x6A,0x66) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F7 (0x6A,0x68) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F8 (0x6A,0x6A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F9 (0x6A,0x6C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F10 (0x6A,0x6E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F11 (0x6A,0x70) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F12 (0x6A,0x72) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F13 (0x6A,0x74) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F14 (0x6A,0x76) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F15 (0x6A,0x78) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F16 (0x6A,0x7A) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F17 (0x6A,0x7C) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F18 (0x6A,0x7E) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F19 (0x6A,0x80) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F20 (0x6A,0x82) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F21 (0x6A,0x84) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F22 (0x6A,0x86) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_F23 (0x6A,0x88) 0x00000000 0x00000000 0x00000000 0x00000000 -GPP_I0 (0x69,0x00) 0x00000000 0x00000000 0xffffffff 0xffffffff -GPP_I1 (0x69,0x02) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I2 (0x69,0x04) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I3 (0x69,0x06) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I4 (0x69,0x08) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I5 (0x69,0x0A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I6 (0x69,0x0C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I7 (0x69,0x0E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I8 (0x69,0x10) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I9 (0x69,0x12) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I10 (0x69,0x14) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I11 (0x69,0x16) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I12 (0x69,0x18) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I13 (0x69,0x1A) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I14 (0x69,0x1C) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I15 (0x69,0x1E) 0xffffffff 0xffffffff 0xffffffff 0xffffffff -GPP_I16 (0x69,0x20) 0xffffffff 0xffffffff 0xffffffff 0xffffffff +GPP_SA0 (0xD1,0x00) 0x04000700 0x0003f048 0x00000000 0x00000000 +GPP_SA1 (0xD1,0x02) 0x04000702 0x0003f049 0x00000000 0x00000000 +GPP_SA2 (0xD1,0x04) 0x04000700 0x0003f04a 0x00000000 0x00000000 +GPP_SA3 (0xD1,0x06) 0x04000700 0x0003f04b 0x00000000 0x00000000 +GPP_SA4 (0xD1,0x08) 0x04000700 0x0003f04c 0x00000000 0x00000000 +GPP_SA5 (0xD1,0x0A) 0x04000700 0x0003f04d 0x00000000 0x00000000 +GPP_SA6 (0xD1,0x0C) 0x04000700 0x0003f04e 0x00000000 0x00000000 +GPP_SA7 (0xD1,0x0E) 0x04000700 0x0003c04f 0x00000000 0x00000000 +GPP_SA8 (0xD1,0x10) 0x44000700 0x0003c050 0x00000000 0x00000000 +GPP_SA9 (0xD1,0x12) 0x44000700 0x0003c051 0x00000000 0x00000000 +GPP_SA10 (0xD1,0x14) 0x44000700 0x0003c052 0x00000000 0x00000000 +GPP_SA11 (0xD1,0x16) 0x44000700 0x0003c053 0x00000000 0x00000000 +GPP_SA12 (0xD1,0x18) 0x44000700 0x0003c054 0x00000000 0x00000000 +GPP_SA13 (0xD1,0x1A) 0x44000700 0x0003c055 0x00000000 0x00000000 +GPP_SA14 (0xD1,0x1C) 0x44000e00 0x00000056 0x00000000 0x00000000 +GPP_SA15 (0xD1,0x1E) 0x84000201 0x00000057 0x00000000 0x00000000 +GPP_SA16 (0xD1,0x20) 0x84000201 0x00000058 0x00000000 0x00000000 +GPP_SA17 (0xD1,0x22) 0x84000201 0x00000059 0x00000000 0x00000000 +GPP_SA18 (0xD1,0x24) 0x84000201 0x0000005a 0x00000000 0x00000000 +GPP_SA19 (0xD1,0x26) 0x44000300 0x0000005b 0x00000000 0x00000000 +GPP_SA20 (0xD1,0x28) 0x44000300 0x0000005c 0x00000000 0x00000000 +GPP_SA21 (0xD1,0x2A) 0x44000b00 0x0000005d 0x00000000 0x00000000 +GPP_SA22 (0xD1,0x2C) 0x44000b00 0x0003d05e 0x00000000 0x00000000 +GPP_SA23 (0xD1,0x2E) 0x44000b00 0x0003d05f 0x00000000 0x00000000 +GPP_SC0 (0xD1,0x5C) 0x44000100 0x00000033 0x00000000 0x00000000 +GPP_SC1 (0xD1,0x5E) 0x44000300 0x00000065 0x00000000 0x00000000 +GPP_SC2 (0xD1,0x60) 0x44000300 0x00000066 0x00000000 0x00000000 +GPP_SC3 (0xD1,0x62) 0x44000300 0x00000067 0x00000000 0x00000000 +GPP_SC4 (0xD1,0x64) 0x44000300 0x00000068 0x00000000 0x00000000 +GPP_SC5 (0xD1,0x66) 0x44000300 0x00000069 0x00000000 0x00000000 +GPP_SC6 (0xD1,0x68) 0x44000300 0x0000006a 0x00000000 0x00000000 +GPP_SC7 (0xD1,0x6A) 0x44000300 0x0000006b 0x00000000 0x00000000 +GPP_SC8 (0xD1,0x6C) 0x44000300 0x0000006c 0x00000000 0x00000000 +GPP_SC9 (0xD1,0x6E) 0x44000300 0x0000006d 0x00000000 0x00000000 +GPP_SC10 (0xD1,0x70) 0x44000300 0x0000006e 0x00000000 0x00000000 +GPP_SC11 (0xD1,0x72) 0x44000300 0x0000006f 0x00000000 0x00000000 +GPP_SC12 (0xD1,0x74) 0x44000300 0x00000070 0x00000000 0x00000000 +GPP_SC13 (0xD1,0x76) 0x44000300 0x00000071 0x00000000 0x00000000 +GPP_SC14 (0xD1,0x78) 0x44000300 0x00000072 0x00000000 0x00000000 +GPP_SC15 (0xD1,0x7A) 0x44000300 0x00000073 0x00000000 0x00000000 +GPP_SC16 (0xD1,0x7C) 0x44000300 0x00000074 0x00000000 0x00000000 +GPP_SC17 (0xD1,0x7E) 0x44000300 0x00000075 0x00000000 0x00000000 +GPP_SC18 (0xD1,0x80) 0x44000300 0x00000076 0x00000000 0x00000000 +GPP_SC19 (0xD1,0x82) 0x44000300 0x00000077 0x00000000 0x00000000 +GPP_SC20 (0xD1,0x84) 0x44000300 0x00000040 0x00000000 0x00000000 +GPP_SC21 (0xD1,0x86) 0x44000300 0x00000041 0x00000000 0x00000000 +GPP_SC22 (0xD1,0x88) 0x44000300 0x00000042 0x00000000 0x00000000 +GPP_SC23 (0xD1,0x8A) 0x44000300 0x00000043 0x00000000 0x00000000 +GPP_SC24 (0xD1,0x8C) 0x44000300 0x00000044 0x00000000 0x00000000 +GPP_SC25 (0xD1,0x8E) 0x44000300 0x00000045 0x00000000 0x00000000 +GPP_SC26 (0xD1,0x90) 0x44000300 0x00000046 0x00000000 0x00000000 +GPP_SB0 (0xD2,0x00) 0x84000201 0x00000058 0x00000000 0x00000000 +GPP_SB1 (0xD2,0x02) 0x84000201 0x00000059 0x00000000 0x00000000 +GPP_SB2 (0xD2,0x04) 0x84000201 0x0000005a 0x00000000 0x00000000 +GPP_SB3 (0xD2,0x06) 0x84000201 0x0000005b 0x00000000 0x00000000 +GPP_SB4 (0xD2,0x08) 0x84000201 0x0000005c 0x00000000 0x00000000 +GPP_SB5 (0xD2,0x0A) 0x84000201 0x0000005d 0x00000000 0x00000000 +GPP_SB6 (0xD2,0x0C) 0x84000201 0x0000005e 0x00000000 0x00000000 +GPP_SB7 (0xD2,0x0E) 0x44000700 0x0000005f 0x00000000 0x00000000 +GPP_SB8 (0xD2,0x10) 0x84000702 0x00000060 0x00000000 0x00000000 +GPP_SB9 (0xD2,0x12) 0x84000702 0x00000061 0x00000000 0x00000000 +GPP_SB10 (0xD2,0x14) 0x84000201 0x00000062 0x00000000 0x00000000 +GPP_SB11 (0xD2,0x16) 0x84000201 0x00000063 0x00000000 0x00000000 +GPP_SB12 (0xD2,0x18) 0x84000201 0x00000064 0x00000000 0x00000000 +GPP_SB13 (0xD2,0x1A) 0x84000201 0x00000065 0x00000000 0x00000000 +GPP_SB14 (0xD2,0x1C) 0x84000700 0x00000066 0x00000000 0x00000000 +GPP_SB15 (0xD2,0x1E) 0x84000201 0x00000067 0x00000000 0x00000000 +GPP_SB16 (0xD2,0x20) 0x84000201 0x00000068 0x00000000 0x00000000 +GPP_SB17 (0xD2,0x22) 0x44000702 0x0003c069 0x00000000 0x00000000 +GPP_SB18 (0xD2,0x24) 0x84000201 0x00003c6a 0x00000000 0x00000000 +GPP_SB19 (0xD2,0x26) 0x84000201 0x00003c6b 0x00000000 0x00000000 +GPP_SD0 (0xD2,0x2C) 0x84000201 0x00000070 0x00000000 0x00000000 +GPP_SD1 (0xD2,0x2E) 0x84000201 0x00000071 0x00000000 0x00000000 +GPP_SD2 (0xD2,0x30) 0x84000201 0x00000072 0x00000000 0x00000000 +GPP_SD3 (0xD2,0x32) 0x84000201 0x00000073 0x00000000 0x00000000 +GPP_SD4 (0xD2,0x34) 0x84000201 0x00000074 0x00000800 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0x04000201 0x00000043 0x00000800 0x00000000 +GPP_E12 (0x6A,0x28) 0x82800102 0x00000044 0x00000000 0x00000000 +GPP_E13 (0x6A,0x2A) 0x82800102 0x00000045 0x00000000 0x00000000 +GPP_E14 (0x6A,0x2C) 0x04000201 0x00000046 0x00000000 0x00000000 +GPP_E15 (0x6A,0x2E) 0x04000201 0x00000047 0x00000000 0x00000000 +GPP_E16 (0x6A,0x30) 0x04000201 0x00000048 0x00000000 0x00000000 +GPP_E17 (0x6A,0x32) 0x04000201 0x00000049 0x00000000 0x00000000 +GPP_E18 (0x6A,0x34) 0x44000200 0x0000004a 0x00000000 0x00000000 +GPP_E19 (0x6A,0x36) 0x04000201 0x0000004b 0x00000000 0x00000000 +GPP_E20 (0x6A,0x38) 0x04000201 0x0000004c 0x00000000 0x00000000 +GPP_E21 (0x6A,0x3A) 0x04000201 0x0000004d 0x00000000 0x00000000 +GPP_K0 (0x6A,0x3E) 0x04000201 0x0000004e 0x00000000 0x00000000 +GPP_K1 (0x6A,0x40) 0x04000201 0x0000004f 0x00000000 0x00000000 +GPP_K2 (0x6A,0x42) 0x04000201 0x00000050 0x00000000 0x00000000 +GPP_K3 (0x6A,0x44) 0x04000201 0x00000051 0x00000000 0x00000000 +GPP_K4 (0x6A,0x46) 0x04000201 0x00000052 0x00000000 0x00000000 +GPP_K5 (0x6A,0x48) 0x04000201 0x00000053 0x00000000 0x00000000 +GPP_K6 (0x6A,0x4A) 0x04000a01 0x00000054 0x00000000 0x00000000 +GPP_K7 (0x6A,0x4C) 0x04000a01 0x00000055 0x00000000 0x00000000 +GPP_K8 (0x6A,0x4E) 0x04000201 0x00000056 0x00000000 0x00000000 +GPP_K9 (0x6A,0x50) 0x04000201 0x00000057 0x00000000 0x00000000 +GPP_K10 (0x6A,0x52) 0x44000b02 0x00003058 0x00000000 0x00000000 +GPP_F0 (0x6A,0x5A) 0x04000201 0x00000059 0x00000000 0x00000000 +GPP_F1 (0x6A,0x5C) 0x84000100 0x0000005a 0x00000000 0x00000000 +GPP_F2 (0x6A,0x5E) 0x04000201 0x0000005b 0x00000000 0x00000000 +GPP_F3 (0x6A,0x60) 0x04000201 0x0000005c 0x00000000 0x00000000 +GPP_F4 (0x6A,0x62) 0x84000100 0x0000005d 0x00000000 0x00000000 +GPP_F5 (0x6A,0x64) 0x04000201 0x0000005e 0x00000000 0x00000000 +GPP_F6 (0x6A,0x66) 0x04000201 0x00000060 0x00000000 0x00000000 +GPP_F7 (0x6A,0x68) 0x04000201 0x00000061 0x00000000 0x00000000 +GPP_F8 (0x6A,0x6A) 0x04000201 0x00000062 0x00000000 0x00000000 +GPP_F9 (0x6A,0x6C) 0x84000102 0x00000063 0x00000000 0x00000000 +GPP_F10 (0x6A,0x6E) 0x80000102 0x00000064 0x00000000 0x00000000 +GPP_F11 (0x6A,0x70) 0x04000201 0x00000065 0x00000000 0x00000000 +GPP_F12 (0x6A,0x72) 0x04000201 0x00000066 0x00000000 0x00000000 +GPP_F13 (0x6A,0x74) 0x04000201 0x00000067 0x00000000 0x00000000 +GPP_F14 (0x6A,0x76) 0x04000201 0x00000068 0x00000000 0x00000000 +GPP_F15 (0x6A,0x78) 0x44000300 0x00000069 0x00000000 0x00000000 +GPP_F16 (0x6A,0x7A) 0x44000200 0x0000006a 0x00000000 0x00000000 +GPP_F17 (0x6A,0x7C) 0x04000201 0x0000006b 0x00000000 0x00000000 +GPP_F18 (0x6A,0x7E) 0x04000201 0x0000006c 0x00000000 0x00000000 +GPP_F19 (0x6A,0x80) 0x04000201 0x0000006d 0x00000000 0x00000000 +GPP_F20 (0x6A,0x82) 0x04000201 0x0000006e 0x00000000 0x00000000 +GPP_F21 (0x6A,0x84) 0x04000201 0x0000006f 0x00000000 0x00000000 +GPP_F22 (0x6A,0x86) 0x04000201 0x00000070 0x00000000 0x00000000 +GPP_F23 (0x6A,0x88) 0x04000201 0x00000071 0x00000000 0x00000000 +GPP_I0 (0x69,0x00) 0x04000201 0x00000018 0x00000000 0x00000000 +GPP_I1 (0x69,0x02) 0x04000201 0x00000019 0x00000000 0x00000000 +GPP_I2 (0x69,0x04) 0x04000601 0x0000001a 0x00000000 0x00000000 +GPP_I3 (0x69,0x06) 0x04000601 0x0000001b 0x00000000 0x00000000 +GPP_I4 (0x69,0x08) 0x04000201 0x0000001c 0x00000000 0x00000000 +GPP_I5 (0x69,0x0A) 0x04000201 0x0000001d 0x00000000 0x00000000 +GPP_I6 (0x69,0x0C) 0x04000201 0x0000001e 0x00000000 0x00000000 +GPP_I7 (0x69,0x0E) 0x04000201 0x0000001f 0x00000000 0x00000000 +GPP_I8 (0x69,0x10) 0x04000201 0x00000020 0x00000000 0x00000000 +GPP_I9 (0x69,0x12) 0x04000201 0x00000021 0x00000000 0x00000000 +GPP_I10 (0x69,0x14) 0x04000201 0x00000022 0x00000000 0x00000000 +GPP_I11 (0x69,0x16) 0x04000201 0x00000023 0x00000000 0x00000000 +GPP_I12 (0x69,0x18) 0x04000201 0x00000024 0x00000000 0x00000000 +GPP_I13 (0x69,0x1A) 0x04000201 0x00000025 0x00000000 0x00000000 +GPP_I14 (0x69,0x1C) 0x04000201 0x00000026 0x00000000 0x00000000 +GPP_I15 (0x69,0x1E) 0x04000201 0x00000027 0x00000000 0x00000000 +GPP_I16 (0x69,0x20) 0x40000201 0x00000000 0x00000000 0x00000000 ## HDAUDIO ## hdaudioC0D0 vendor_name: Nvidia diff --git a/tools/coreboot-collector b/tools/coreboot-collector index ff7f10b7..76a10b20 160000 --- a/tools/coreboot-collector +++ b/tools/coreboot-collector @@ -1 +1 @@ -Subproject commit ff7f10b7460c1e6063b5fe1b4c7bf0db9a392d03 +Subproject commit 76a10b20f20e9f900c55a0c0ca6c02198b702749 From 7a14a4ad9285942fb1336fe898a8be3bc2b70a6a Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 25 Mar 2025 17:46:02 +0000 Subject: [PATCH 7/7] Update bonw16 generated GPIO output --- models/bonw16/gpio.c | 553 +++++++++++++++++++++++++------------------ 1 file changed, 324 insertions(+), 229 deletions(-) diff --git a/models/bonw16/gpio.c b/models/bonw16/gpio.c index c16318e8..f7ca21c4 100644 --- a/models/bonw16/gpio.c +++ b/models/bonw16/gpio.c @@ -4,235 +4,330 @@ #include static const struct pad_config gpio_table[] = { - PAD_CFG_GPO(GPD0, 0, PWROK), - _PAD_CFG_STRUCT(GPD1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPD12, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_A0, 0, PWROK), - _PAD_CFG_STRUCT(GPP_A1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A3, 0xfffffffd, 0x3c00), - PAD_CFG_TERM_GPO(GPP_A4, 0, NATIVE, TODO_0x21000000), - _PAD_CFG_STRUCT(GPP_A5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A8, 0x21001f00, 0x3c00), - _PAD_CFG_STRUCT(GPP_A9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_A11, 0xfffffffd, 0x3c00), - PAD_CFG_TERM_GPO(GPP_A12, 0, NATIVE, PWROK), - _PAD_CFG_STRUCT(GPP_A13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B0, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B5, 0x210000fd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B16, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B17, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B18, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B19, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B20, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_B21, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C0, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C16, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C17, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C18, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C19, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C20, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C21, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C22, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_C23, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_D0, 0, PWROK), - _PAD_CFG_STRUCT(GPP_D1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D16, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D17, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D18, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D19, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D20, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D21, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D22, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_D23, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_E0, 0, PWROK), - PAD_CFG_GPO(GPP_E1, 0, PWROK), - PAD_CFG_GPO(GPP_E2, 0, PWROK), - PAD_CFG_GPO(GPP_E3, 0, PWROK), - PAD_CFG_GPO(GPP_E4, 0, PWROK), - PAD_CFG_GPO(GPP_E5, 0, PWROK), - PAD_CFG_GPO(GPP_E6, 0, PWROK), - PAD_CFG_GPO(GPP_E7, 0, PWROK), - PAD_CFG_GPO(GPP_E8, 0, PWROK), - PAD_CFG_GPO(GPP_E9, 0, PWROK), - PAD_CFG_GPO(GPP_E10, 0, PWROK), - PAD_CFG_GPO(GPP_E11, 0, PWROK), - PAD_CFG_GPO(GPP_E12, 0, PWROK), - PAD_CFG_GPO(GPP_E13, 0, PWROK), - PAD_CFG_GPO(GPP_E14, 0, PWROK), - PAD_CFG_GPO(GPP_E15, 0, PWROK), - PAD_CFG_GPO(GPP_E16, 0, PWROK), - PAD_CFG_GPO(GPP_E17, 0, PWROK), - PAD_CFG_GPO(GPP_E18, 0, PWROK), - PAD_CFG_GPO(GPP_E19, 0, PWROK), - PAD_CFG_GPO(GPP_E20, 0, PWROK), - PAD_CFG_GPO(GPP_E21, 0, PWROK), - PAD_CFG_GPO(GPP_F0, 0, PWROK), - PAD_CFG_GPO(GPP_F1, 0, PWROK), - PAD_CFG_GPO(GPP_F2, 0, PWROK), - PAD_CFG_GPO(GPP_F3, 0, PWROK), - PAD_CFG_GPO(GPP_F4, 0, PWROK), - PAD_CFG_GPO(GPP_F5, 0, PWROK), - PAD_CFG_GPO(GPP_F6, 0, PWROK), - PAD_CFG_GPO(GPP_F7, 0, PWROK), - PAD_CFG_GPO(GPP_F8, 0, PWROK), - PAD_CFG_GPO(GPP_F9, 0, PWROK), - PAD_CFG_GPO(GPP_F10, 0, PWROK), - PAD_CFG_GPO(GPP_F11, 0, PWROK), - PAD_CFG_GPO(GPP_F12, 0, PWROK), - PAD_CFG_GPO(GPP_F13, 0, PWROK), - PAD_CFG_GPO(GPP_F14, 0, PWROK), - PAD_CFG_GPO(GPP_F15, 0, PWROK), - PAD_CFG_GPO(GPP_F16, 0, PWROK), - PAD_CFG_GPO(GPP_F17, 0, PWROK), - PAD_CFG_GPO(GPP_F18, 0, PWROK), - PAD_CFG_GPO(GPP_F19, 0, PWROK), - PAD_CFG_GPO(GPP_F20, 0, PWROK), - PAD_CFG_GPO(GPP_F21, 0, PWROK), - PAD_CFG_GPO(GPP_F22, 0, PWROK), - PAD_CFG_GPO(GPP_F23, 0, PWROK), - _PAD_CFG_STRUCT(GPP_H0, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H16, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H17, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H18, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_H19, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_I0, 0, PWROK), - _PAD_CFG_STRUCT(GPP_I1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_I16, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J0, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J12, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J13, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J14, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J15, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_J16, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_K0, 0, PWROK), - PAD_CFG_GPO(GPP_K1, 0, PWROK), - PAD_CFG_GPO(GPP_K2, 0, PWROK), - PAD_CFG_GPO(GPP_K3, 0, PWROK), - PAD_CFG_GPO(GPP_K4, 0, PWROK), - PAD_CFG_GPO(GPP_K5, 0, PWROK), - PAD_CFG_GPO(GPP_K6, 0, PWROK), - PAD_CFG_GPO(GPP_K7, 0, PWROK), - PAD_CFG_GPO(GPP_K8, 0, PWROK), - PAD_CFG_GPO(GPP_K9, 0, PWROK), - PAD_CFG_GPO(GPP_K10, 0, PWROK), - _PAD_CFG_STRUCT(GPP_R0, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R1, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R2, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R3, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R4, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R5, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R6, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R7, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R8, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R9, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R10, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R11, 0xfffffffd, 0x3c00), - _PAD_CFG_STRUCT(GPP_R12, 0xfffffffd, 0x3c00), - PAD_CFG_GPO(GPP_S0, 0, PWROK), - PAD_CFG_GPO(GPP_S1, 0, PWROK), - PAD_CFG_GPO(GPP_S2, 0, PWROK), - PAD_CFG_GPO(GPP_S3, 0, PWROK), - PAD_CFG_GPO(GPP_S4, 0, PWROK), - PAD_CFG_GPO(GPP_S5, 0, PWROK), - PAD_CFG_GPO(GPP_S6, 0, PWROK), - PAD_CFG_GPO(GPP_S7, 0, PWROK), + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD2, 0x42800100, 0x0000), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, TODO_0xc4000201), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD11, 0, PWROK), + PAD_CFG_GPO(GPD12, 1, TODO_0xc4000201), + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A7, 1, PWROK), + PAD_CFG_GPO(GPP_A8, 1, PWROK), + PAD_CFG_GPO(GPP_A9, 1, PWROK), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 1, PWROK), + _PAD_CFG_STRUCT(GPP_A12, 0x82900100, 0x0000), + PAD_CFG_GPI(GPP_A13, NONE, PLTRST), + _PAD_CFG_STRUCT(GPP_B0, 0x04000601, 0x0000), + PAD_CFG_GPO(GPP_B1, 1, PWROK), + PAD_CFG_GPO(GPP_B2, 1, PWROK), + _PAD_CFG_STRUCT(GPP_B3, 0x42880100, 0x0000), + PAD_CFG_GPO(GPP_B4, 0, PWROK), + PAD_CFG_GPO(GPP_B5, 1, PWROK), + PAD_CFG_GPO(GPP_B6, 1, PWROK), + PAD_CFG_GPI(GPP_B7, NONE, PLTRST), + PAD_CFG_GPI(GPP_B8, NONE, PLTRST), + PAD_CFG_GPI(GPP_B9, NONE, PLTRST), + PAD_CFG_GPI(GPP_B10, NONE, PLTRST), + PAD_CFG_GPI(GPP_B11, NONE, PLTRST), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B14, 1, PWROK), + PAD_CFG_GPO(GPP_B15, 1, PWROK), + PAD_CFG_GPO(GPP_B16, 1, PWROK), + PAD_CFG_GPO(GPP_B17, 0, PWROK), + _PAD_CFG_STRUCT(GPP_B18, 0x04000601, 0x0000), + PAD_CFG_GPO(GPP_B19, 1, PWROK), + PAD_CFG_GPO(GPP_B20, 1, PWROK), + _PAD_CFG_STRUCT(GPP_B21, 0x02880100, 0x0000), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C2, 1, PWROK), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), + PAD_CFG_GPO(GPP_C5, 1, PWROK), + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), + _PAD_CFG_STRUCT(GPP_C8, 0x86880100, 0x0000), + PAD_CFG_GPO(GPP_C9, 1, PWROK), + _PAD_CFG_STRUCT(GPP_C10, 0x86880100, 0x0000), + _PAD_CFG_STRUCT(GPP_C11, 0x86880100, 0x0000), + PAD_CFG_GPO(GPP_C12, 1, PWROK), + PAD_CFG_GPO(GPP_C13, 1, PWROK), + PAD_CFG_GPO(GPP_C14, 1, PWROK), + _PAD_CFG_STRUCT(GPP_C15, 0x80100100, 0x0000), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF2), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPO(GPP_C22, 1, PWROK), + PAD_CFG_GPO(GPP_C23, 1, PWROK), + PAD_CFG_GPO(GPP_D0, 1, PWROK), + PAD_CFG_GPO(GPP_D1, 1, PWROK), + PAD_CFG_GPO(GPP_D2, 1, PWROK), + PAD_CFG_GPO(GPP_D3, 1, PWROK), + _PAD_CFG_STRUCT(GPP_D4, 0x04000300, 0x0000), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + _PAD_CFG_STRUCT(GPP_D9, 0x04000300, 0x0000), + _PAD_CFG_STRUCT(GPP_D10, 0x04000300, 0x0000), + PAD_CFG_NF(GPP_D11, NATIVE, PLTRST, NF1), + PAD_CFG_NF(GPP_D12, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D13, 1, PWROK), + PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + _PAD_CFG_STRUCT(GPP_D15, 0x04000300, 0x0000), + PAD_CFG_GPO(GPP_D16, 1, PWROK), + PAD_CFG_GPO(GPP_D17, 1, PWROK), + PAD_CFG_GPO(GPP_D18, 1, PWROK), + PAD_CFG_GPO(GPP_D19, 1, PWROK), + PAD_CFG_GPO(GPP_D20, 1, PWROK), + PAD_CFG_GPO(GPP_D21, 1, PWROK), + PAD_CFG_GPO(GPP_D22, 1, PWROK), + PAD_CFG_GPO(GPP_D23, 1, PWROK), + PAD_CFG_GPO(GPP_E0, 1, PWROK), + PAD_CFG_GPO(GPP_E1, 1, PWROK), + PAD_CFG_GPO(GPP_E2, 1, PWROK), + _PAD_CFG_STRUCT(GPP_E3, 0x82800100, 0x0000), + PAD_CFG_GPO(GPP_E4, 1, PWROK), + PAD_CFG_GPO(GPP_E5, 1, PWROK), + PAD_CFG_GPO(GPP_E6, 1, PWROK), + PAD_CFG_GPO(GPP_E7, 1, PWROK), + PAD_CFG_GPO(GPP_E8, 1, PWROK), + PAD_CFG_GPO(GPP_E9, 1, PWROK), + PAD_CFG_GPO(GPP_E10, 1, PWROK), + PAD_CFG_GPO(GPP_E11, 1, PWROK), + _PAD_CFG_STRUCT(GPP_E12, 0x82800100, 0x0000), + _PAD_CFG_STRUCT(GPP_E13, 0x82800100, 0x0000), + PAD_CFG_GPO(GPP_E14, 1, PWROK), + PAD_CFG_GPO(GPP_E15, 1, PWROK), + PAD_CFG_GPO(GPP_E16, 1, PWROK), + PAD_CFG_GPO(GPP_E17, 1, PWROK), + PAD_CFG_GPO(GPP_E18, 0, DEEP), + PAD_CFG_GPO(GPP_E19, 1, PWROK), + PAD_CFG_GPO(GPP_E20, 1, PWROK), + PAD_CFG_GPO(GPP_E21, 1, PWROK), + PAD_CFG_GPO(GPP_F0, 1, PWROK), + PAD_CFG_GPI(GPP_F1, NONE, PLTRST), + PAD_CFG_GPO(GPP_F2, 1, PWROK), + PAD_CFG_GPO(GPP_F3, 1, PWROK), + PAD_CFG_GPI(GPP_F4, NONE, PLTRST), + PAD_CFG_GPO(GPP_F5, 1, PWROK), + PAD_CFG_GPO(GPP_F6, 1, PWROK), + PAD_CFG_GPO(GPP_F7, 1, PWROK), + PAD_CFG_GPO(GPP_F8, 1, PWROK), + PAD_CFG_GPI(GPP_F9, NONE, PLTRST), + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + PAD_CFG_GPO(GPP_F11, 1, PWROK), + PAD_CFG_GPO(GPP_F12, 1, PWROK), + PAD_CFG_GPO(GPP_F13, 1, PWROK), + PAD_CFG_GPO(GPP_F14, 1, PWROK), + PAD_NC(GPP_F15, NONE), + PAD_CFG_GPO(GPP_F16, 0, DEEP), + PAD_CFG_GPO(GPP_F17, 1, PWROK), + PAD_CFG_GPO(GPP_F18, 1, PWROK), + PAD_CFG_GPO(GPP_F19, 1, PWROK), + PAD_CFG_GPO(GPP_F20, 1, PWROK), + PAD_CFG_GPO(GPP_F21, 1, PWROK), + PAD_CFG_GPO(GPP_F22, 1, PWROK), + PAD_CFG_GPO(GPP_F23, 1, PWROK), + PAD_CFG_GPO(GPP_H0, 1, PWROK), + PAD_CFG_NF(GPP_H1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H4, NONE, PLTRST, NF1), + PAD_CFG_GPI(GPP_H5, NONE, PLTRST), + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), + PAD_CFG_GPI(GPP_H8, NONE, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PWROK), + PAD_CFG_GPO(GPP_H10, 1, PWROK), + PAD_CFG_GPO(GPP_H11, 1, PWROK), + PAD_CFG_GPO(GPP_H12, 1, PWROK), + PAD_CFG_GPO(GPP_H13, 1, PWROK), + PAD_CFG_GPO(GPP_H14, 1, PWROK), + PAD_CFG_GPO(GPP_H15, 1, PWROK), + PAD_CFG_GPO(GPP_H16, 1, PWROK), + PAD_CFG_GPO(GPP_H17, 1, PWROK), + PAD_CFG_GPO(GPP_H18, 1, PWROK), + PAD_CFG_GPO(GPP_H19, 1, PWROK), + PAD_CFG_GPO(GPP_I0, 1, PWROK), + PAD_CFG_GPO(GPP_I1, 1, PWROK), + _PAD_CFG_STRUCT(GPP_I2, 0x04000601, 0x0000), + _PAD_CFG_STRUCT(GPP_I3, 0x04000601, 0x0000), + PAD_CFG_GPO(GPP_I4, 1, PWROK), + PAD_CFG_GPO(GPP_I5, 1, PWROK), + PAD_CFG_GPO(GPP_I6, 1, PWROK), + PAD_CFG_GPO(GPP_I7, 1, PWROK), + PAD_CFG_GPO(GPP_I8, 1, PWROK), + PAD_CFG_GPO(GPP_I9, 1, PWROK), + PAD_CFG_GPO(GPP_I10, 1, PWROK), + PAD_CFG_GPO(GPP_I11, 1, PWROK), + PAD_CFG_GPO(GPP_I12, 1, PWROK), + PAD_CFG_GPO(GPP_I13, 1, PWROK), + PAD_CFG_GPO(GPP_I14, 1, PWROK), + PAD_CFG_GPO(GPP_I15, 1, PWROK), + PAD_CFG_GPO(GPP_I16, 1, DEEP), + PAD_NC(GPP_J0, NONE), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_J2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_J4, UP_20K, DEEP, NF1), + PAD_NC(GPP_J5, NONE), + PAD_CFG_GPO(GPP_J6, 0, DEEP), + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_J9, 1, PWROK), + PAD_CFG_GPO(GPP_J10, 1, PWROK), + PAD_CFG_GPO(GPP_J11, 1, PWROK), + PAD_CFG_NF(GPP_J12, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_J13, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_J15, 1, PWROK), + PAD_CFG_GPO(GPP_J16, 1, PWROK), + PAD_CFG_GPO(GPP_K0, 1, PWROK), + PAD_CFG_GPO(GPP_K1, 1, PWROK), + PAD_CFG_GPO(GPP_K2, 1, PWROK), + PAD_CFG_GPO(GPP_K3, 1, PWROK), + PAD_CFG_GPO(GPP_K4, 1, PWROK), + PAD_CFG_GPO(GPP_K5, 1, PWROK), + _PAD_CFG_STRUCT(GPP_K6, 0x04000a01, 0x0000), + _PAD_CFG_STRUCT(GPP_K7, 0x04000a01, 0x0000), + PAD_CFG_GPO(GPP_K8, 1, PWROK), + PAD_CFG_GPO(GPP_K9, 1, PWROK), + PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2), + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_R5, 1, PWROK), + PAD_CFG_GPO(GPP_R6, 1, PWROK), + PAD_CFG_GPO(GPP_R7, 1, PWROK), + PAD_CFG_GPO(GPP_R8, 1, PWROK), + PAD_CFG_GPO(GPP_R9, 1, PWROK), + PAD_CFG_GPO(GPP_R10, 1, PWROK), + PAD_CFG_GPO(GPP_R11, 1, PWROK), + PAD_CFG_GPO(GPP_R12, 1, PWROK), + PAD_CFG_GPO(GPP_S0, 1, PWROK), + PAD_CFG_GPO(GPP_S1, 1, PWROK), + PAD_CFG_GPO(GPP_S2, 1, PWROK), + PAD_CFG_GPO(GPP_S3, 1, PWROK), + PAD_CFG_GPO(GPP_S4, 1, PWROK), + PAD_CFG_GPO(GPP_S5, 1, PWROK), + PAD_CFG_GPO(GPP_S6, 1, PWROK), + PAD_CFG_GPO(GPP_S7, 1, PWROK), + PAD_CFG_NF(GPP_SA0, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA1, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA2, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA4, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA5, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA6, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPP_SA7, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_SA8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SA14, NONE, DEEP, NF3), + PAD_CFG_GPO(GPP_SA15, 1, PLTRST), + PAD_CFG_GPO(GPP_SA16, 1, PLTRST), + PAD_CFG_GPO(GPP_SA17, 1, PLTRST), + PAD_CFG_GPO(GPP_SA18, 1, PLTRST), + PAD_NC(GPP_SA19, NONE), + PAD_NC(GPP_SA20, NONE), + PAD_CFG_NF(GPP_SA21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_SA22, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPP_SA23, DN_20K, DEEP, NF2), + PAD_CFG_GPO(GPP_SB0, 1, PLTRST), + PAD_CFG_GPO(GPP_SB1, 1, PLTRST), + PAD_CFG_GPO(GPP_SB2, 1, PLTRST), + PAD_CFG_GPO(GPP_SB3, 1, PLTRST), + PAD_CFG_GPO(GPP_SB4, 1, PLTRST), + PAD_CFG_GPO(GPP_SB5, 1, PLTRST), + PAD_CFG_GPO(GPP_SB6, 1, PLTRST), + PAD_CFG_NF(GPP_SB7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_SB8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_SB9, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_SB10, 1, PLTRST), + PAD_CFG_GPO(GPP_SB11, 1, PLTRST), + PAD_CFG_GPO(GPP_SB12, 1, PLTRST), + PAD_CFG_GPO(GPP_SB13, 1, PLTRST), + PAD_CFG_NF(GPP_SB14, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_SB15, 1, PLTRST), + PAD_CFG_GPO(GPP_SB16, 1, PLTRST), + PAD_CFG_NF(GPP_SB17, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_SB18, 1, NATIVE, PLTRST), + PAD_CFG_TERM_GPO(GPP_SB19, 1, NATIVE, PLTRST), + PAD_CFG_GPI(GPP_SC0, NONE, DEEP), + PAD_NC(GPP_SC1, NONE), + PAD_NC(GPP_SC2, NONE), + PAD_NC(GPP_SC3, NONE), + PAD_NC(GPP_SC4, NONE), + PAD_NC(GPP_SC5, NONE), + PAD_NC(GPP_SC6, NONE), + PAD_NC(GPP_SC7, NONE), + PAD_NC(GPP_SC8, NONE), + PAD_NC(GPP_SC9, NONE), + PAD_NC(GPP_SC10, NONE), + PAD_NC(GPP_SC11, NONE), + PAD_NC(GPP_SC12, NONE), + PAD_NC(GPP_SC13, NONE), + PAD_NC(GPP_SC14, NONE), + PAD_NC(GPP_SC15, NONE), + PAD_NC(GPP_SC16, NONE), + PAD_NC(GPP_SC17, NONE), + PAD_NC(GPP_SC18, NONE), + PAD_NC(GPP_SC19, NONE), + PAD_NC(GPP_SC20, NONE), + PAD_NC(GPP_SC21, NONE), + PAD_NC(GPP_SC22, NONE), + PAD_NC(GPP_SC23, NONE), + PAD_NC(GPP_SC24, NONE), + PAD_NC(GPP_SC25, NONE), + PAD_NC(GPP_SC26, NONE), + PAD_CFG_GPO(GPP_SD0, 1, PLTRST), + PAD_CFG_GPO(GPP_SD1, 1, PLTRST), + PAD_CFG_GPO(GPP_SD2, 1, PLTRST), + PAD_CFG_GPO(GPP_SD3, 1, PLTRST), + PAD_CFG_GPO(GPP_SD4, 1, PLTRST), + PAD_CFG_GPO(GPP_SD5, 1, PLTRST), + PAD_CFG_GPO(GPP_SD6, 1, PLTRST), + PAD_CFG_GPO(GPP_SD7, 1, PLTRST), + PAD_CFG_GPO(GPP_SD8, 1, PLTRST), + PAD_CFG_GPO(GPP_SD9, 1, PLTRST), + PAD_CFG_GPO(GPP_SD10, 1, PLTRST), + PAD_CFG_GPO(GPP_SD11, 1, PLTRST), + PAD_CFG_GPO(GPP_SD12, 1, PLTRST), + PAD_CFG_GPO(GPP_SD13, 1, PLTRST), + PAD_CFG_GPO(GPP_SD14, 1, PLTRST), + PAD_CFG_GPO(GPP_SD15, 1, PLTRST), + PAD_CFG_GPO(GPP_SD16, 1, PLTRST), + PAD_CFG_GPO(GPP_SD17, 0, DEEP), + PAD_CFG_NF(GPP_SD18, UP_20K, DEEP, NF1), + PAD_NC(GPP_SD19, NONE), + PAD_NC(GPP_SD20, NONE), + PAD_CFG_NF(GPP_SD21, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_SD22, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_SD23, NONE, DEEP, NF1), }; void mainboard_configure_gpios(void)