Update intel-spi and add gaze17

Author: jackpot51

Cargo.lock

@@ -9,7 +9,7 @@ lto = true
 
 [dependencies]
 coreboot-fs = "0.1.0"
-intel-spi = "0.1.3"
+intel-spi = "0.1.4"
 plain = "0.2.3"
 redox_dmi = "0.1.5"
 redox_hwio = "0.1.4"

Cargo.toml

@@ -5,15 +5,15 @@ use alloc::string::String;
 use core::char;
 use coreboot_fs::Rom;
 use ecflash::EcFlash;
-use intel_spi::{HsfStsCtl, Spi, SpiKbl, SpiCnl};
+use intel_spi::{HsfStsCtl, Spi, SpiDev};
 use plain::Plain;
 use std::fs::{find, load};
 use std::ptr;
 use std::vars::{get_boot_item, get_boot_order, set_boot_item, set_boot_order};
 use std::uefi::reset::ResetType;
 use std::uefi::status::{Error, Result, Status};
 
-use super::{FIRMWARECAP, FIRMWAREDIR, FIRMWARENSH, FIRMWAREROM, H2OFFT, IFLASHV, UEFIFLASH, shell, Component};
+use super::{FIRMWARECAP, FIRMWAREDIR, FIRMWARENSH, FIRMWAREROM, H2OFFT, IFLASHV, UEFIFLASH, shell, Component, pci_mcfg, UefiMapper};
 
 fn copy_region(region: intelflash::RegionKind, old_data: &[u8], new_data: &mut [u8]) -> core::result::Result<bool, String> {
     let old_opt = intelflash::Rom::new(old_data)?.get_region_base_limit(region)?;
@@ -102,44 +102,54 @@ impl BiosComponent {
         }
     }
 
-    pub fn spi(&self) -> Option<(&'static mut dyn Spi, HsfStsCtl)> {
+    pub fn spi(&self) -> Option<(SpiDev<'static, UefiMapper>, HsfStsCtl)> {
+        static mut UEFI_MAPPER: UefiMapper = UefiMapper;
+
         match self.bios_vendor.as_str() {
             "coreboot" => match self.system_version.as_str() {
-                "galp2" |
-                "galp3" |
-                "galp3-b" => {
-                    let spi_kbl = unsafe {
-                        &mut *(SpiKbl::address() as *mut SpiKbl)
-                    };
-                    let hsfsts_ctl = spi_kbl.hsfsts_ctl();
-                    Some((spi_kbl as &mut dyn Spi, hsfsts_ctl))
-                },
                 "addw1" |
                 "addw2" |
                 "bonw14" |
                 "darp5" |
                 "darp6" |
-                "darp7" | // Technically TGL-U but protocol is the same
+                "darp7" |
+                "galp2" |
+                "galp3" |
+                "galp3-b" |
                 "galp3-c" |
                 "galp4" |
-                "galp5" | // Technically TGL-U but protocol is the same
+                "galp5" |
                 "gaze14" |
                 "gaze15" |
-                "gaze16-3050" | // Technically TGL-H but protocol is the same
-                "gaze16-3060" | // Technically TGL-H but protocol is the same
-                "gaze16-3060-b" | // Technically TGL-H but protocol is the same
+                "gaze16-3050" |
+                "gaze16-3060" |
+                "gaze16-3060-b" |
+                "gaze17-3050" |
+                "gaze17-3060" |
+                "gaze17-3060-b" |
                 "lemp9" |
-                "lemp10" | // Technically TGL-U but protocol is the same
+                "lemp10" |
                 "oryp5" |
                 "oryp6" |
                 "oryp7" |
-                "oryp8" // Technically TGL-H but protocol is the same
+                "oryp8"
                 => {
-                    let spi_cnl = unsafe {
-                        &mut *(SpiCnl::address() as *mut SpiCnl)
+                    let mcfg = match pci_mcfg() {
+                        Some(some) => some,
+                        None => {
+                            println!("failed to get MCFG table");
+                            return None;
+                        }
+                    };
+                    let spi = match unsafe { SpiDev::new(mcfg, &mut UEFI_MAPPER) } {
+                        Ok(ok) => ok,
+                        Err(err) => {
+                            println!("failed to get SPI device: {}", err);
+                            return None;
+                        }
                     };
-                    let hsfsts_ctl = spi_cnl.hsfsts_ctl();
-                    Some((spi_cnl as &mut dyn Spi, hsfsts_ctl))
+                    let hsfsts_ctl = spi.regs.hsfsts_ctl();
+                    Some((spi, hsfsts_ctl))
                 },
                 _ => None,
             },
@@ -200,7 +210,7 @@ impl Component for BiosComponent {
 
     fn validate(&self) -> Result<bool> {
         let data = load(self.path())?;
-        if let Some((spi, _hsfsts_ctl)) = self.spi() {
+        if let Some((mut spi, _hsfsts_ctl)) = self.spi() {
             // if hsfsts_ctl.contains(HsfStsCtl::FDOPSS) {
             //     println!("SPI currently locked, attempting to unlock");
             //     Self::spi_unlock();
@@ -224,7 +234,7 @@ impl Component for BiosComponent {
     }
 
     fn flash(&self) -> Result<()> {
-        if let Some((spi, _hsfsts_ctl)) = self.spi() {
+        if let Some((mut spi, _hsfsts_ctl)) = self.spi() {
             // Read new data
             let mut new;
             {

src/app/bios.rs

@@ -163,6 +163,15 @@ impl EcComponent {
                         "system76/gaze16-3060".to_string()
                     }
                 },
+                "NPxxPNJ_K" => "system76/gaze17-3050".to_string(),
+                "NPxxPNP" => {
+                    // If the builtin ethernet at 00:1f.6 is present, this is a -b variant
+                    if pci_read(0x00, 0x1f, 0x6, 0x00).unwrap() == 0x1a1e8086 {
+                        "system76/gaze17-3060-b".to_string()
+                    } else {
+                        "system76/gaze17-3060".to_string()
+                    }
+                },
                 "NS50MU" => "system76/darp7".to_string(),
                 "NV40Mx" | "NV40Mx-DV" | "NV40MJ" => "system76/galp5".to_string(),
                 "PB50Ex" => "system76/addw1".to_string(),

src/app/ec.rs

@@ -0,0 +1,18 @@
+use intel_spi::{Mapper, PhysicalAddress, VirtualAddress};
+
+pub struct UefiMapper;
+
+impl Mapper for UefiMapper {
+    unsafe fn map_aligned(&mut self, address: PhysicalAddress, _size: usize) -> Result<VirtualAddress, &'static str> {
+        Ok(VirtualAddress(address.0 as usize))
+    }
+
+    unsafe fn unmap_aligned(&mut self, _address: VirtualAddress, _size: usize) -> Result<(), &'static str> {
+        Ok(())
+    }
+
+    fn page_size(&self) -> usize {
+        //TODO: get dynamically
+        4096
+    }
+}

src/app/mapper.rs

@@ -29,11 +29,13 @@ use crate::text::TextDisplay;
 pub use self::bios::BiosComponent;
 pub use self::component::Component;
 pub use self::ec::EcComponent;
-pub use self::pci::pci_read;
+pub use self::mapper::UefiMapper;
+pub use self::pci::{pci_mcfg, pci_read};
 
 mod bios;
 mod component;
 mod ec;
+mod mapper;
 mod pci;
 
 static ECROM: &str = concat!("\\", env!("BASEDIR"), "\\firmware\\ec.rom");

src/app/mod.rs

@@ -1,4 +1,98 @@
+use core::{mem, slice};
 use hwio::{Io, Pio};
+use std::uefi::guid::GuidKind;
+
+#[allow(dead_code)]
+#[repr(packed)]
+struct Rsdp {
+    signature: [u8; 8], // b"RSD PTR "
+    chksum: u8,
+    oem_id: [u8; 6],
+    revision: u8,
+    rsdt_addr: u32,
+    // the following fields are only available for ACPI 2.0, and are reserved otherwise
+    length: u32,
+    xsdt_addr: u64,
+    extended_chksum: u8,
+    _rsvd: [u8; 3],
+}
+
+#[allow(dead_code)]
+#[repr(packed)]
+struct SdtHeader {
+    signature: [u8; 4],
+    length: u32,
+    revision: u8,
+    checksum: u8,
+    oem_id: [u8; 6],
+    oem_table_id: u64,
+    oem_revision: u32,
+    creator_id: u32,
+    creator_revision: u32,
+}
+
+unsafe fn rsdp_mcfg(rsdp: &Rsdp) -> Option<&'static [u8]> {
+    if rsdp.signature != *b"RSD PTR " {
+        return None;
+    }
+
+    if rsdp.rsdt_addr != 0 {
+        let rsdt = &*(rsdp.rsdt_addr as *const SdtHeader);
+        if let Some(rsdt_data_len) = (rsdt.length as usize).checked_sub(mem::size_of::<SdtHeader>()) {
+            let entries = slice::from_raw_parts(
+                (rsdt as *const SdtHeader).offset(1) as *const u32,
+                rsdt_data_len / mem::size_of::<u32>()
+            );
+            for &entry in entries {
+                let sdt = &*(entry as *const SdtHeader);
+                if sdt.signature == *b"MCFG" {
+                    return Some(slice::from_raw_parts(
+                        sdt as *const SdtHeader as *const u8,
+                        sdt.length as usize
+                    ));
+                }
+            }
+        }
+    }
+
+    if rsdp.revision >= 2 && rsdp.xsdt_addr != 0 {
+        let xsdt = &*(rsdp.xsdt_addr as *const SdtHeader);
+        if let Some(rsdt_data_len) = (xsdt.length as usize).checked_sub(mem::size_of::<SdtHeader>()) {
+            let entries = slice::from_raw_parts(
+                (xsdt as *const SdtHeader).offset(1) as *const u64,
+                rsdt_data_len / mem::size_of::<u64>()
+            );
+            for &entry in entries {
+                let sdt = &*(entry as *const SdtHeader);
+                if sdt.signature == *b"MCFG" {
+                    return Some(slice::from_raw_parts(
+                        sdt as *const SdtHeader as *const u8,
+                        sdt.length as usize
+                    ));
+                }
+            }
+        }
+    }
+
+    None
+}
+
+pub fn pci_mcfg() -> Option<&'static [u8]> {
+    for table in std::system_table().config_tables() {
+        match table.VendorGuid.kind() {
+            GuidKind::Acpi |
+            GuidKind::Acpi2 => unsafe {
+                let rsdp = &*(table.VendorTable as *const Rsdp);
+                match rsdp_mcfg(rsdp) {
+                    Some(some) => return Some(some),
+                    None => (),
+                }
+            },
+            _ => ()
+        };
+    }
+    None
+}
 
 pub fn pci_read(bus: u8, dev: u8, func: u8, offset: u8) -> Result<u32, String> {
     if dev > 0x1f {