re-write with Veryl

Author: taichi-ishitani

.gitignore

@@ -22,3 +22,9 @@ whisper_connect
 *.bin
 *.dump
 *.elf
+
+# Veryl
+.build
+dependencies
+target
+**/sim_binary/*.list.rb

csr/rice_csr_m_level.rb csr/rice_csr.rbcsr/rice_csr_m_level.rb renamed to csr/rice_csr.rb

@@ -1,12 +1,30 @@
 # frozen_string_literal: true
 
-require_relative 'rice_csr_common'
-setup(self)
+class << self
+  def xlen
+    configuration.bus_width
+  end
+
+  def word_size
+    @word_size ||= xlen / 8
+  end
+
+  def block_size
+    @block_size ||= word_size * 4096
+  end
+
+  def byte_address(address)
+    address * word_size
+  end
+end
 
 register_block {
-  name "rice_csr_m_level_xlen#{xlen}"
+  name "rice_csr_xlen#{xlen}"
   byte_size block_size
 
+#==============================================================
+# Machine level registrers
+#==============================================================
   #
   # Machine Information Registers
   #
@@ -54,7 +72,7 @@
     }
     bit_field {
       name 'mie'
-      bit_assignment lsb: 3, width: 1; type :rws; initial_value 0
+      bit_assignment lsb: 3, width: 1; type :rwhw; initial_value 0
     }
     bit_field {
       name 'spie'
@@ -66,7 +84,7 @@
     }
     bit_field {
       name 'mpie'
-      bit_assignment lsb: 7, width: 1; type :rws; initial_value 0
+      bit_assignment lsb: 7, width: 1; type :rwhw; initial_value 0
     }
     bit_field {
       name 'spp'
@@ -78,7 +96,7 @@
     }
     bit_field {
       name 'mpp'
-      bit_assignment lsb: 11, width: 2; type :rws; initial_value 0
+      bit_assignment lsb: 11, width: 2; type :rwhw; initial_value 0
     }
     bit_field {
       name 'fs'
@@ -235,7 +253,7 @@
     name 'mepc'
     offset_address byte_address(0x341)
     bit_field {
-      bit_assignment lsb: 0, width: xlen; type :rws; initial_value 0
+      bit_assignment lsb: 0, width: xlen; type :rwhw; initial_value 0
     }
   }
 
@@ -244,19 +262,19 @@
     offset_address byte_address(0x342)
     bit_field {
       name 'exception_code'
-      bit_assignment lsb: 0, width: xlen - 1; type :rws; initial_value 0
+      bit_assignment lsb: 0, width: xlen - 1; type :rwhw; initial_value 0
     }
     bit_field {
       name 'interrupt'
-      bit_assignment lsb: xlen - 1, width: 1; type :rws; initial_value 0
+      bit_assignment lsb: xlen - 1, width: 1; type :rwhw; initial_value 0
     }
   }
 
   register {
     name 'mtval'
     offset_address byte_address(0x343)
     bit_field {
-      bit_assignment lsb: 0, width: xlen; type :rws; initial_value 0
+      bit_assignment lsb: 0, width: xlen; type :rwhw; initial_value 0
     }
   }
 
@@ -345,4 +363,48 @@
       bit_assignment lsb: 2, width: 1; type :rw; initial_value 0
     }
   }
+
+#==============================================================
+# User level registrers
+#==============================================================
+  #
+  # Unprivileged Counter/Timers
+  #
+  register {
+    name 'cycle'
+    offset_address byte_address(0xC00)
+    type :variable_access
+    bit_field {
+      bit_assignment lsb: 0, width: xlen; type :ro
+    }
+  }
+
+  register {
+    name 'instret'
+    offset_address byte_address(0xC02)
+    type :variable_access
+    bit_field {
+      bit_assignment lsb: 0, width: xlen; type :ro
+    }
+  }
+
+  if xlen == 32
+    register {
+      name 'cycleh'
+      offset_address byte_address(0xC80)
+      type :variable_access
+      bit_field {
+        bit_assignment lsb: 0, width: xlen; type :ro
+      }
+    }
+
+    register {
+      name 'instreth'
+      offset_address byte_address(0xC82)
+      type :variable_access
+      bit_field {
+        bit_assignment lsb: 0, width: xlen; type :ro
+      }
+    }
+  end
 }

csr/rice_csr_common.rb

@@ -3,7 +3,7 @@ PATH_SCRIPT := $(RICE_ROOT)/script
 PATH_RTL    := $(RICE_ROOT)/rtl
 
 SOURCE := $(RICE_ROOT)/inst/riscv_inst.yaml
-RESULT := $(PATH_RTL)/common/rice_riscv_inst_matcher_pkg.sv
+RESULT := $(PATH_RTL)/common/rice_riscv_inst_matcher_pkg.veryl
 
 $(RESULT): $(SOURCE)
 	ruby $(PATH_SCRIPT)/rb/create_inst_matcher.rb $< $@

csr/rice_csr_u_level.rb

@@ -0,0 +1,15 @@
+# This file is automatically @generated by Veryl.
+# It is not intended for manual editing.
+version = 1
+
+[[projects]]
+name = "rggen"
+dependencies = []
+
+[projects.source]
+uuid = "14c7e46d-44a0-52cd-b9a3-70b31bd92d75"
+url = "https://github.com/rggen/rggen-veryl-rtl"
+path = ""
+project = "rggen"
+version = "0.5.0"
+revision = "1f628ca3183b4dbf7ced84b4139159d4f87ff491"

inst/makefile

@@ -0,0 +1,21 @@
+[project]
+name       = "rice"
+version    = "0.1.0"
+authors    = ["Taichi Ishitani <taichi730@gmail.com>"]
+license    = "Apache-2.0"
+repository = "https://github.com/taichi-ishitani/rice"
+
+[format]
+indent_width  = 2
+
+[build]
+target           = {type = "directory", path = "target"}
+filelist_type    = "flgen"
+reset_low_suffix = "_n"
+
+[publish]
+bump_commit    = true
+publish_commit = true
+
+[dependencies]
+"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" }

rtl/Veryl.lock

@@ -0,0 +1,79 @@
+interface rice_bus_if #(
+  param ADDRESS_WIDTH: u32 = 32            ,
+  param DATA_WIDTH   : u32 = 32            ,
+  param STROBE_WIDTH : u32 = DATA_WIDTH / 8,
+) {
+  var request_ready : logic               ;
+  var request_valid : logic               ;
+  var write         : logic               ;
+  var address       : logic<ADDRESS_WIDTH>;
+  var strobe        : logic<STROBE_WIDTH> ;
+  var write_data    : logic<DATA_WIDTH>   ;
+  var response_ready: logic               ;
+  var response_valid: logic               ;
+  var read_data     : logic<DATA_WIDTH>   ;
+  var error         : logic               ;
+
+  function request_ack() -> logic {
+    return request_ready && request_valid;
+  }
+
+  function read_request_valid() -> logic {
+    return request_valid && (!write);
+  }
+
+  function read_request_ack() -> logic {
+    return request_ready && request_valid && (!write);
+  }
+
+  function write_request_valid() -> logic {
+    return request_valid && write;
+  }
+
+  function write_request_ack() -> logic {
+    return request_ready && request_valid && write;
+  }
+
+  function response_ack() -> logic {
+    return response_ready && response_valid;
+  }
+
+  modport master {
+    request_ready      : input ,
+    request_valid      : output,
+    write              : output,
+    address            : output,
+    strobe             : output,
+    write_data         : output,
+    response_ready     : output,
+    response_valid     : input ,
+    read_data          : input ,
+    error              : input ,
+    request_ack        : import,
+    read_request_valid : import,
+    read_request_ack   : import,
+    write_request_valid: import,
+    write_request_ack  : import,
+    response_ack       : import,
+  }
+
+  modport slave {
+    request_ack        : import,
+    read_request_valid : import,
+    read_request_ack   : import,
+    write_request_valid: import,
+    write_request_ack  : import,
+    response_ack       : import,
+    ..converse(master)
+  }
+
+  modport monitor {
+    request_ack        : import,
+    read_request_valid : import,
+    read_request_ack   : import,
+    write_request_valid: import,
+    write_request_ack  : import,
+    response_ack       : import,
+    ..input
+  }
+}