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Improve support for AVR and MSP430 custom targets
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‎CHANGELOG.md‎

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@@ -10,6 +10,10 @@ Note: In this file, do not use the hard wrap in the middle of a sentence for com
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## [Unreleased]
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- Fix build error when not using `portable_atomic_unsafe_assume_single_core` cfg on AVR and MSP430 custom targets.
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Since 0.3.11, atomic CAS was supported without the cfg on AVR and MSP430 builtin targets, but that change was not applied to custom targets.
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## [0.3.17] - 2022-12-14
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- Optimize x86_64 128-bit atomic load/store on AMD CPU with AVX. ([#49](https://github.com/taiki-e/portable-atomic/pull/49))

‎src/imp/mod.rs‎

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@@ -2,15 +2,19 @@
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// Lock-free implementations
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// cfg(target_has_atomic_load_store = "ptr")
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#[cfg(not(portable_atomic_no_atomic_load_store))]
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#[cfg(not(any(
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portable_atomic_no_atomic_load_store,
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portable_atomic_unsafe_assume_single_core,
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target_arch = "avr",
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target_arch = "msp430",
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)))]
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#[cfg_attr(
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not(portable_atomic_no_cfg_target_has_atomic),
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cfg(not(all(
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any(target_arch = "riscv32", target_arch = "riscv64"),
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not(target_has_atomic = "ptr")
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)))
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)]
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#[cfg(any(test, not(portable_atomic_unsafe_assume_single_core)))]
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mod core_atomic;
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// Miri and Sanitizer do not support inline assembly.
@@ -137,38 +141,27 @@ pub(crate) mod float;
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// -----------------------------------------------------------------------------
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// Atomic{Isize,Usize,Bool,Ptr}, Atomic{I,U}{8,16}
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#[cfg_attr(
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portable_atomic_no_cfg_target_has_atomic,
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cfg(any(
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not(portable_atomic_no_atomic_cas),
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all(
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not(portable_atomic_no_atomic_load_store),
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not(portable_atomic_unsafe_assume_single_core)
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)
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))
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)]
144+
#[cfg(not(any(
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portable_atomic_no_atomic_load_store,
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portable_atomic_unsafe_assume_single_core,
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target_arch = "avr",
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target_arch = "msp430",
149+
)))]
150150
#[cfg_attr(
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not(portable_atomic_no_cfg_target_has_atomic),
152-
cfg(any(
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target_has_atomic = "ptr",
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all(
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not(portable_atomic_no_atomic_load_store),
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not(portable_atomic_unsafe_assume_single_core),
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not(all(
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any(target_arch = "riscv32", target_arch = "riscv64"),
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not(target_has_atomic = "ptr")
160-
))
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)
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))
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cfg(not(all(
153+
any(target_arch = "riscv32", target_arch = "riscv64"),
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not(target_has_atomic = "ptr")
155+
)))
163156
)]
164157
pub(crate) use self::core_atomic::{
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AtomicBool, AtomicI16, AtomicI8, AtomicIsize, AtomicPtr, AtomicU16, AtomicU8, AtomicUsize,
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};
167160
// RISC-V without A-extension
168161
#[cfg(not(portable_atomic_unsafe_assume_single_core))]
169-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(portable_atomic_no_atomic_cas))]
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#[cfg_attr(not(portable_atomic_no_cfg_target_has_atomic), cfg(not(target_has_atomic = "ptr")))]
164+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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pub(crate) use self::riscv::{
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AtomicBool, AtomicI16, AtomicI8, AtomicIsize, AtomicPtr, AtomicU16, AtomicU8, AtomicUsize,
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};
@@ -185,37 +178,25 @@ pub(crate) use self::interrupt::{
185178
};
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187180
// Atomic{I,U}32
188-
#[cfg(not(target_pointer_width = "16"))]
189-
#[cfg_attr(
190-
portable_atomic_no_cfg_target_has_atomic,
191-
cfg(any(
192-
not(portable_atomic_no_atomic_cas),
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all(
194-
not(portable_atomic_no_atomic_load_store),
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not(portable_atomic_unsafe_assume_single_core)
196-
)
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))
198-
)]
181+
#[cfg(not(any(
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portable_atomic_no_atomic_load_store,
183+
portable_atomic_unsafe_assume_single_core,
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target_arch = "avr",
185+
target_arch = "msp430",
186+
)))]
199187
#[cfg_attr(
200188
not(portable_atomic_no_cfg_target_has_atomic),
201-
cfg(any(
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target_has_atomic = "ptr",
203-
all(
204-
not(portable_atomic_no_atomic_load_store),
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not(portable_atomic_unsafe_assume_single_core),
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not(all(
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any(target_arch = "riscv32", target_arch = "riscv64"),
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not(target_has_atomic = "ptr")
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))
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)
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))
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cfg(not(all(
190+
any(target_arch = "riscv32", target_arch = "riscv64"),
191+
not(target_has_atomic = "ptr")
192+
)))
212193
)]
213194
pub(crate) use self::core_atomic::{AtomicI32, AtomicU32};
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// RISC-V without A-extension
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#[cfg(not(portable_atomic_unsafe_assume_single_core))]
216-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(portable_atomic_no_atomic_cas))]
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#[cfg_attr(not(portable_atomic_no_cfg_target_has_atomic), cfg(not(target_has_atomic = "ptr")))]
199+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
219200
pub(crate) use self::riscv::{AtomicI32, AtomicU32};
220201
// no core Atomic{I,U}32 & no CAS & assume single core => critical section based fallback
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#[cfg(any(not(target_pointer_width = "16"), feature = "fallback"))]
@@ -229,15 +210,17 @@ pub(crate) use self::riscv::{AtomicI32, AtomicU32};
229210
pub(crate) use self::interrupt::{AtomicI32, AtomicU32};
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// Atomic{I,U}64
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#[cfg(not(any(
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portable_atomic_no_atomic_load_store,
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portable_atomic_unsafe_assume_single_core,
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)))]
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#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(not(portable_atomic_no_atomic_64)))]
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#[cfg_attr(
234219
not(portable_atomic_no_cfg_target_has_atomic),
235220
cfg(any(
236221
target_has_atomic = "64",
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all(
238223
not(any(target_pointer_width = "16", target_pointer_width = "32")),
239-
not(portable_atomic_no_atomic_load_store),
240-
not(portable_atomic_unsafe_assume_single_core),
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not(all(
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any(target_arch = "riscv32", target_arch = "riscv64"),
243226
not(target_has_atomic = "ptr")
@@ -248,16 +231,20 @@ pub(crate) use self::interrupt::{AtomicI32, AtomicU32};
248231
pub(crate) use self::core_atomic::{AtomicI64, AtomicU64};
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// RISC-V without A-extension
250233
#[cfg(not(portable_atomic_unsafe_assume_single_core))]
251-
#[cfg(target_arch = "riscv64")]
252234
#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(portable_atomic_no_atomic_cas))]
253235
#[cfg_attr(not(portable_atomic_no_cfg_target_has_atomic), cfg(not(target_has_atomic = "ptr")))]
236+
#[cfg(target_arch = "riscv64")]
254237
pub(crate) use self::riscv::{AtomicI64, AtomicU64};
255238
// no core Atomic{I,U}64 & has CAS => use lock-base fallback
256239
#[cfg(feature = "fallback")]
257-
#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(portable_atomic_no_atomic_64))]
258-
#[cfg_attr(not(portable_atomic_no_cfg_target_has_atomic), cfg(not(target_has_atomic = "64")))]
259-
#[cfg_attr(portable_atomic_no_cfg_target_has_atomic, cfg(not(portable_atomic_no_atomic_cas)))]
260-
#[cfg_attr(not(portable_atomic_no_cfg_target_has_atomic), cfg(target_has_atomic = "ptr"))]
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#[cfg_attr(
241+
portable_atomic_no_cfg_target_has_atomic,
242+
cfg(all(portable_atomic_no_atomic_64, not(portable_atomic_no_atomic_cas)))
243+
)]
244+
#[cfg_attr(
245+
not(portable_atomic_no_cfg_target_has_atomic),
246+
cfg(all(not(target_has_atomic = "64"), target_has_atomic = "ptr"))
247+
)]
261248
pub(crate) use self::fallback::{AtomicI64, AtomicU64};
262249
// no core Atomic{I,U}64 & no CAS & assume single core => critical section based fallback
263250
#[cfg(any(

‎target-specs/avr-unknown-gnu-atmega168.json‎

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{
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"arch": "avr",
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"atomic-cas": false,
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"cpu": "atmega168",
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"data-layout": "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8",
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"eh-frame-header": false,
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"exe-suffix": ".elf",
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"late-link-args": {
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"gcc": [
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"-lgcc"
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]
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},
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"linker": "avr-gcc",
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"llvm-target": "avr-unknown-unknown",
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"max-atomic-width": 0,
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"pre-link-args": {
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"gcc": [
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"-mmcu=atmega168"
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]
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},
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"relocation-model": "static",
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"target-c-int-width": "16",
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"target-pointer-width": "16"
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}

‎target-specs/msp430-unknown-none-elf.json‎

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{
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"arch": "msp430",
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"asm-args": [
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"-mcpu=msp430"
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],
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"atomic-cas": false,
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"data-layout": "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16",
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"default-codegen-units": 1,
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"eh-frame-header": false,
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"emit-debug-gdb-scripts": false,
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"linker": "msp430-elf-gcc",
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"linker-is-gnu": false,
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"llvm-target": "msp430-none-elf",
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"max-atomic-width": 0,
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"panic-strategy": "abort",
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"relocation-model": "static",
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"target-c-int-width": "16",
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"target-pointer-width": "16",
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"trap-unreachable": false
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}

‎tools/build.sh‎

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@@ -9,14 +9,16 @@ trap -- 'exit 0' SIGINT
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default_targets=(
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# no atomic load/store (16-bit)
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avr-unknown-gnu-atmega168 # for checking custom target
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avr-unknown-gnu-atmega328
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msp430-none-elf
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msp430-unknown-none-elf # same as msp430-none-elf, but for checking custom target
1416
# no atomic load/store (32-bit)
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riscv32i-unknown-none-elf
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riscv32im-unknown-none-elf
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riscv32imc-unknown-none-elf
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# no atomic load/store (64-bit)
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riscv64i-unknown-none-elf
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riscv64i-unknown-none-elf # custom target
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# no atomic CAS (32-bit)
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thumbv4t-none-eabi

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