Skip to content

Commit 1ab5974

Browse files
authored
[AArch64] Support commuted operands in performFlagSettingCombine (llvm#162496)
Fixes llvm#122624. Assisted-by: gpt-5-codex
1 parent 739bfde commit 1ab5974

File tree

5 files changed

+31
-19
lines changed

5 files changed

+31
-19
lines changed

llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1850,9 +1850,11 @@ class SelectionDAG {
18501850
/// Get the specified node if it's already available, or else return NULL.
18511851
LLVM_ABI SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
18521852
ArrayRef<SDValue> Ops,
1853-
const SDNodeFlags Flags);
1853+
const SDNodeFlags Flags,
1854+
bool AllowCommute = false);
18541855
LLVM_ABI SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
1855-
ArrayRef<SDValue> Ops);
1856+
ArrayRef<SDValue> Ops,
1857+
bool AllowCommute = false);
18561858

18571859
/// Check if a node exists without modifying its flags.
18581860
LLVM_ABI bool doesNodeExist(unsigned Opcode, SDVTList VTList,

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11844,25 +11844,38 @@ SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
1184411844
/// getNodeIfExists - Get the specified node if it's already available, or
1184511845
/// else return NULL.
1184611846
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
11847-
ArrayRef<SDValue> Ops) {
11847+
ArrayRef<SDValue> Ops,
11848+
bool AllowCommute) {
1184811849
SDNodeFlags Flags;
1184911850
if (Inserter)
1185011851
Flags = Inserter->getFlags();
11851-
return getNodeIfExists(Opcode, VTList, Ops, Flags);
11852+
return getNodeIfExists(Opcode, VTList, Ops, Flags, AllowCommute);
1185211853
}
1185311854

1185411855
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
1185511856
ArrayRef<SDValue> Ops,
11856-
const SDNodeFlags Flags) {
11857-
if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
11857+
const SDNodeFlags Flags,
11858+
bool AllowCommute) {
11859+
if (VTList.VTs[VTList.NumVTs - 1] == MVT::Glue)
11860+
return nullptr;
11861+
11862+
auto Lookup = [&](ArrayRef<SDValue> LookupOps) -> SDNode * {
1185811863
FoldingSetNodeID ID;
11859-
AddNodeIDNode(ID, Opcode, VTList, Ops);
11864+
AddNodeIDNode(ID, Opcode, VTList, LookupOps);
1186011865
void *IP = nullptr;
11861-
if (SDNode *E = FindNodeOrInsertPos(ID, SDLoc(), IP)) {
11866+
if (SDNode *E = FindNodeOrInsertPos(ID, IP)) {
1186211867
E->intersectFlagsWith(Flags);
1186311868
return E;
1186411869
}
11865-
}
11870+
return nullptr;
11871+
};
11872+
11873+
if (SDNode *Existing = Lookup(Ops))
11874+
return Existing;
11875+
11876+
if (AllowCommute && TLI->isCommutativeBinOp(Opcode))
11877+
return Lookup({Ops[1], Ops[0]});
11878+
1186611879
return nullptr;
1186711880
}
1186811881

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26196,9 +26196,10 @@ static SDValue performFlagSettingCombine(SDNode *N,
2619626196
return DCI.CombineTo(N, Res, SDValue(N, 1));
2619726197
}
2619826198

26199-
// Combine identical generic nodes into this node, re-using the result.
26199+
// Combine equivalent generic nodes into this node, re-using the result.
2620026200
if (SDNode *Generic = DCI.DAG.getNodeIfExists(
26201-
GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS}))
26201+
GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS},
26202+
/*AllowCommute=*/true))
2620226203
DCI.CombineTo(Generic, SDValue(N, 0));
2620326204

2620426205
return SDValue();

llvm/test/CodeGen/AArch64/adds_cmn.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,8 @@ entry:
2222
define { i32, i32 } @adds_cmn_c(i32 noundef %x, i32 noundef %y) {
2323
; CHECK-LABEL: adds_cmn_c:
2424
; CHECK: // %bb.0: // %entry
25-
; CHECK-NEXT: cmn w0, w1
26-
; CHECK-NEXT: add w1, w1, w0
27-
; CHECK-NEXT: cset w8, lo
28-
; CHECK-NEXT: mov w0, w8
25+
; CHECK-NEXT: adds w1, w0, w1
26+
; CHECK-NEXT: cset w0, lo
2927
; CHECK-NEXT: ret
3028
entry:
3129
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %y)

llvm/test/CodeGen/AArch64/sat-add.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,7 @@ define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
290290
define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
291291
; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
292292
; CHECK: // %bb.0:
293-
; CHECK-NEXT: add w8, w0, w1
294-
; CHECK-NEXT: cmn w1, w0
293+
; CHECK-NEXT: adds w8, w1, w0
295294
; CHECK-NEXT: csinv w0, w8, wzr, lo
296295
; CHECK-NEXT: ret
297296
%noty = xor i32 %y, -1
@@ -331,8 +330,7 @@ define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {
331330
define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
332331
; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval:
333332
; CHECK: // %bb.0:
334-
; CHECK-NEXT: add x8, x0, x1
335-
; CHECK-NEXT: cmn x1, x0
333+
; CHECK-NEXT: adds x8, x1, x0
336334
; CHECK-NEXT: csinv x0, x8, xzr, lo
337335
; CHECK-NEXT: ret
338336
%noty = xor i64 %y, -1

0 commit comments

Comments
 (0)