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david-arm丹治秀樹
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[LV][NFC] Remove remaining uses of undef in tests (llvm#169357)
Split off from PR llvm#163525, this standalone patch replaces almost all the remaining cases where undef is used as value in loop vectoriser tests. This will reduce the likelihood of contributors hitting the `undef deprecator` warning in github. NOTE: The remaining use of undef in iv_outside_user.ll will be fixed in a separate PR. I've removed the test stride_undef from version-mem-access.ll, since there is already a stride_poison test.
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11 files changed

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‎llvm/test/Transforms/LoopVectorize/X86/pr39160.ll‎

Lines changed: 60 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,75 +1,71 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
12
; RUN: opt -passes=loop-vectorize -S < %s 2>&1 | FileCheck %s
23

34
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
45
target triple = "x86_64-unknown-linux-gnu"
56

67
; Make sure that we can compile the test without crash.
7-
define void @barney(ptr %dst, i1 %arg) {
8-
9-
; CHECK-LABEL: @barney(
10-
; CHECK: middle.block:
11-
12-
bb:
13-
br label %bb2
14-
15-
bb2: ; preds = %bb2, %bb
16-
%tmp4 = icmp slt i32 undef, 0
17-
br i1 %tmp4, label %bb2, label %bb5
18-
19-
bb5: ; preds = %bb2
20-
br label %bb19
21-
22-
bb18: ; preds = %bb33
23-
ret void
24-
25-
bb19: ; preds = %bb36, %bb5
26-
%tmp21 = phi i64 [ undef, %bb36 ], [ 2, %bb5 ]
27-
%tmp22 = phi i32 [ %tmp65, %bb36 ], [ undef, %bb5 ]
28-
br label %bb50
29-
30-
bb33: ; preds = %bb62
31-
br i1 %arg, label %bb18, label %bb36
32-
33-
bb36: ; preds = %bb33
34-
br label %bb19
35-
36-
bb46: ; preds = %bb50
37-
br i1 %arg, label %bb48, label %bb59
38-
39-
bb48: ; preds = %bb46
40-
%tmp49 = add i32 %tmp52, 14
41-
ret void
42-
43-
bb50: ; preds = %bb50, %bb19
44-
%tmp52 = phi i32 [ %tmp55, %bb50 ], [ %tmp22, %bb19 ]
45-
%tmp53 = phi i64 [ %tmp56, %bb50 ], [ 1, %bb19 ]
46-
%gep = getelementptr inbounds i8, ptr %dst, i64 %tmp53
47-
store i8 1, ptr %gep
48-
%tmp54 = add i32 %tmp52, 12
49-
%tmp55 = add i32 %tmp52, 13
50-
%tmp56 = add nuw nsw i64 %tmp53, 1
51-
%tmp58 = icmp ult i64 %tmp53, undef
52-
br i1 %tmp58, label %bb50, label %bb46
53-
54-
bb59: ; preds = %bb46
55-
br label %bb62
56-
57-
bb62: ; preds = %bb68, %bb59
58-
%tmp63 = phi i32 [ %tmp65, %bb68 ], [ %tmp55, %bb59 ]
59-
%tmp64 = phi i64 [ %tmp66, %bb68 ], [ %tmp56, %bb59 ]
60-
%tmp65 = add i32 %tmp63, 13
61-
%tmp66 = add nuw nsw i64 %tmp64, 1
62-
%tmp67 = icmp ult i64 %tmp66, %tmp21
63-
br i1 %tmp67, label %bb68, label %bb33
64-
65-
bb68: ; preds = %bb62
66-
br label %bb62
67-
}
688

699
define i32 @foo(ptr addrspace(1) %p) {
70-
71-
; CHECK-LABEL: foo
72-
; CHECK: middle.block:
10+
; CHECK-LABEL: define i32 @foo(
11+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) {
12+
; CHECK-NEXT: [[ENTRY:.*]]:
13+
; CHECK-NEXT: br label %[[OUTER:.*]]
14+
; CHECK: [[OUTER]]:
15+
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
16+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[OUTER_LATCH]] ]
17+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDVAR]], 1
18+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 8
19+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
20+
; CHECK: [[VECTOR_PH]]:
21+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP0]], 8
22+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP0]], [[N_MOD_VF]]
23+
; CHECK-NEXT: [[TMP1:%.*]] = add i32 1, [[N_VEC]]
24+
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[N_VEC]], 2
25+
; CHECK-NEXT: [[TMP3:%.*]] = add i32 6, [[TMP2]]
26+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
27+
; CHECK: [[VECTOR_BODY]]:
28+
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
29+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
30+
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
31+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 6, i32 8, i32 10, i32 12>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
32+
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 8)
33+
; CHECK-NEXT: [[TMP4]] = or <4 x i32> [[VEC_PHI]], [[VEC_IND]]
34+
; CHECK-NEXT: [[TMP5]] = or <4 x i32> [[VEC_PHI1]], [[STEP_ADD]]
35+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
36+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 8)
37+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
38+
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
39+
; CHECK: [[MIDDLE_BLOCK]]:
40+
; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]
41+
; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX]])
42+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP0]], [[N_VEC]]
43+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[OUTER_LATCH]], label %[[SCALAR_PH]]
44+
; CHECK: [[SCALAR_PH]]:
45+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER]] ]
46+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 1, %[[OUTER]] ]
47+
; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 6, %[[OUTER]] ]
48+
; CHECK-NEXT: br label %[[INNER:.*]]
49+
; CHECK: [[INNER]]:
50+
; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP10:%.*]], %[[INNER]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
51+
; CHECK-NEXT: [[A:%.*]] = phi i32 [ [[TMP11:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
52+
; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[TMP9:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ]
53+
; CHECK-NEXT: [[TMP9]] = add i32 [[B]], 2
54+
; CHECK-NEXT: [[TMP10]] = or i32 [[TMP8]], [[B]]
55+
; CHECK-NEXT: [[TMP11]] = add nuw nsw i32 [[A]], 1
56+
; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
57+
; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[IV]], [[TMP12]]
58+
; CHECK-NEXT: br i1 [[TMP13]], label %[[INNER]], label %[[OUTER_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
59+
; CHECK: [[OUTER_LATCH]]:
60+
; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP10]], %[[INNER]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]
61+
; CHECK-NEXT: store atomic i32 [[DOTLCSSA]], ptr addrspace(1) [[P]] unordered, align 4
62+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
63+
; CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[IV]], 63
64+
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
65+
; CHECK-NEXT: br i1 [[TMP14]], label %[[EXIT:.*]], label %[[OUTER]]
66+
; CHECK: [[EXIT]]:
67+
; CHECK-NEXT: ret i32 0
68+
;
7369

7470
entry:
7571
br label %outer

‎llvm/test/Transforms/LoopVectorize/if-conversion.ll‎

Lines changed: 25 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -237,22 +237,36 @@ for.end: ; preds = %for.inc, %entry
237237
; Handle PHI with single incoming value having a full mask.
238238
; PR34523
239239

240-
; NOTE: Changing PHI inputs from undef to poison leads to change in
241-
; behaviour of the test. Left as undef for now.
242-
define void @PR34523() {
243-
; CHECK-LABEL: define void @PR34523() {
244-
; CHECK-NEXT: [[BB1:.*:]]
245-
; CHECK-NEXT: br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
240+
define void @PR34523(ptr %p, i16 %val) {
241+
; CHECK-LABEL: define void @PR34523(
242+
; CHECK-SAME: ptr [[P:%.*]], i16 [[VAL:%.*]]) {
243+
; CHECK-NEXT: [[BB1:.*]]:
244+
; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[VAL]], 1
245+
; CHECK-NEXT: [[SMAX:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP0]], i16 2)
246+
; CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[VAL]], -1
247+
; CHECK-NEXT: [[TMP2:%.*]] = add i16 [[SMAX]], [[TMP1]]
248+
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32
249+
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 1
250+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i16 [[TMP2]], 3
251+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
246252
; CHECK: [[VECTOR_PH]]:
253+
; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[TMP4]], 131068
254+
; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i16
255+
; CHECK-NEXT: [[TMP5:%.*]] = add i16 [[VAL]], [[DOTCAST]]
247256
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
248257
; CHECK: [[VECTOR_BODY]]:
249-
; CHECK-NEXT: br i1 poison, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
258+
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
259+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
260+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
261+
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
250262
; CHECK: [[MIDDLE_BLOCK]]:
251-
; CHECK-NEXT: br i1 poison, label %[[BB5:.*]], label %[[SCALAR_PH]]
263+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP4]], [[N_VEC]]
264+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[BB5:.*]], label %[[SCALAR_PH]]
252265
; CHECK: [[SCALAR_PH]]:
266+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[VAL]], %[[BB1]] ]
253267
; CHECK-NEXT: br label %[[BB2:.*]]
254268
; CHECK: [[BB2]]:
255-
; CHECK-NEXT: [[I:%.*]] = phi i16 [ undef, %[[SCALAR_PH]] ], [ [[_TMP2:%.*]], %[[BB4:.*]] ]
269+
; CHECK-NEXT: [[I:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[_TMP2:%.*]], %[[BB4:.*]] ]
256270
; CHECK-NEXT: br label %[[BB3:.*]]
257271
; CHECK: [[BB3]]:
258272
; CHECK-NEXT: br label %[[BB4]]
@@ -267,11 +281,11 @@ bb1:
267281
br label %bb2
268282

269283
bb2: ; preds = %bb4, %bb1
270-
%i = phi i16 [ undef, %bb1 ], [ %_tmp2, %bb4 ]
284+
%i = phi i16 [ %val, %bb1 ], [ %_tmp2, %bb4 ]
271285
br label %bb3
272286

273287
bb3: ; preds = %bb2
274-
%_tmp1 = phi ptr [ undef, %bb2 ]
288+
%_tmp1 = phi ptr [ %p, %bb2 ]
275289
br label %bb4
276290

277291
bb4: ; preds = %bb3

‎llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ thread-pre-split.loopexit: ; preds = %11, %.thread-pre-sp
5858
br i1 %arg, label %11, label %22
5959

6060
; <label>:11 ; preds = %.lr.ph21
61-
%12 = getelementptr inbounds [0 x i8], ptr @PL_utf8skip, i64 0, i64 undef
61+
%12 = getelementptr inbounds [0 x i8], ptr @PL_utf8skip, i64 0, i64 0
6262
%13 = load i8, ptr %12, align 1
6363
%14 = zext i8 %13 to i64
6464
%15 = icmp ugt i64 %14, %10

‎llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll‎

Lines changed: 28 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
1-
; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true < %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
2+
; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
3+
; RUN: -enable-interleaved-mem-accesses=true < %s | FileCheck %s
24

35
; Make sure the vectorizer can handle this loop: The strided load is only used
46
; by the loop's exit condition, which is not vectorized, and is therefore
@@ -29,10 +31,31 @@
2931
%0 zeroinitializer], align 8
3032

3133
define dso_local void @test_dead_load(i32 %arg) {
32-
; CHECK-LABEL: @test_dead_load(
33-
; CHECK: vector.body:
34-
; CHECK: %wide.vec = load <16 x i32>, ptr %3, align 8
35-
; CHECK: %strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
34+
; CHECK-LABEL: define dso_local void @test_dead_load(
35+
; CHECK-SAME: i32 [[ARG:%.*]]) {
36+
; CHECK-NEXT: [[BB1:.*:]]
37+
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
38+
; CHECK: [[VECTOR_PH]]:
39+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
40+
; CHECK: [[VECTOR_BODY]]:
41+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
42+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
43+
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 52
44+
; CHECK-NEXT: br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
45+
; CHECK: [[MIDDLE_BLOCK]]:
46+
; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
47+
; CHECK: [[SCALAR_PH]]:
48+
; CHECK-NEXT: br label %[[BB2:.*]]
49+
; CHECK: [[BB2]]:
50+
; CHECK-NEXT: [[TMP:%.*]] = phi ptr [ [[TMP6:%.*]], %[[BB2]] ], [ getelementptr (i8, ptr @[[GLOB0:[0-9]+]], i64 832), %[[SCALAR_PH]] ]
51+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 0, i32 1
52+
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
53+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 258
54+
; CHECK-NEXT: [[TMP6]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 1
55+
; CHECK-NEXT: br i1 [[TMP5]], label %[[BB65:.*]], label %[[BB2]], !llvm.loop [[LOOP3:![0-9]+]]
56+
; CHECK: [[BB65]]:
57+
; CHECK-NEXT: unreachable
58+
;
3659
bb1:
3760
br label %bb2
3861

‎llvm/test/Transforms/LoopVectorize/iv_outside_user.ll‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -262,15 +262,16 @@ for.end:
262262
ret i32 %phi
263263
}
264264

265-
define void @PR30742() {
266-
; CHECK-LABEL: define void @PR30742() {
265+
define void @PR30742(ptr %p) {
266+
; CHECK-LABEL: define void @PR30742(
267+
; CHECK-SAME: ptr [[P:%.*]]) {
267268
; CHECK-NEXT: [[BB0:.*:]]
268269
; CHECK-NEXT: br label %[[BB1:.*]]
269270
; CHECK: [[BB1_LOOPEXIT:.*]]:
270271
; CHECK-NEXT: br label %[[BB1]]
271272
; CHECK: [[BB1]]:
272-
; CHECK-NEXT: [[TMP00:%.*]] = load i32, ptr undef, align 16
273-
; CHECK-NEXT: [[TMP01:%.*]] = sub i32 [[TMP00]], undef
273+
; CHECK-NEXT: [[TMP00:%.*]] = load i32, ptr [[P]], align 16
274+
; CHECK-NEXT: [[TMP01:%.*]] = sub i32 [[TMP00]], 3
274275
; CHECK-NEXT: [[TMP02:%.*]] = icmp slt i32 [[TMP01]], 1
275276
; CHECK-NEXT: [[TMP03:%.*]] = select i1 [[TMP02]], i32 1, i32 [[TMP01]]
276277
; CHECK-NEXT: [[TMP04:%.*]] = add nsw i32 [[TMP03]], -7
@@ -307,7 +308,7 @@ define void @PR30742() {
307308
; CHECK-NEXT: br i1 [[TMP07]], label %[[BB2]], label %[[BB3]], {{!llvm.loop ![0-9]+}}
308309
; CHECK: [[BB3]]:
309310
; CHECK-NEXT: [[TMP08:%.*]] = phi i32 [ [[TMP05]], %[[BB2]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK10]] ]
310-
; CHECK-NEXT: [[TMP09:%.*]] = sub i32 [[TMP00]], undef
311+
; CHECK-NEXT: [[TMP09:%.*]] = sub i32 [[TMP00]], 4
311312
; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[TMP09]], 1
312313
; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 1, i32 [[TMP09]]
313314
; CHECK-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP11]], -7
@@ -346,8 +347,8 @@ BB0:
346347
br label %BB1
347348

348349
BB1:
349-
%tmp00 = load i32, ptr undef, align 16
350-
%tmp01 = sub i32 %tmp00, undef
350+
%tmp00 = load i32, ptr %p, align 16
351+
%tmp01 = sub i32 %tmp00, 3
351352
%tmp02 = icmp slt i32 %tmp01, 1
352353
%tmp03 = select i1 %tmp02, i32 1, i32 %tmp01
353354
%tmp04 = add nsw i32 %tmp03, -7
@@ -361,7 +362,7 @@ BB2:
361362

362363
BB3:
363364
%tmp08 = phi i32 [ %tmp05, %BB2 ]
364-
%tmp09 = sub i32 %tmp00, undef
365+
%tmp09 = sub i32 %tmp00, 4
365366
%tmp10 = icmp slt i32 %tmp09, 1
366367
%tmp11 = select i1 %tmp10, i32 1, i32 %tmp09
367368
%tmp11.inc = add nsw i32 %tmp11, -7

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