drivers: clock_control: st: add missing bus source clocks

Add missing bus source clocks for STM32H5, U5 and WBA

Signed-off-by: Guillaume Gautier <[email protected]>

Author: gautierg-st

drivers/clock_control/clock_stm32_ll_h5.c

@@ -120,6 +120,10 @@ static uint32_t get_sysclk_frequency(void)
 int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
+	    (src_clk == STM32_SRC_HCLK) ||
+	    (src_clk == STM32_SRC_PCLK1) ||
+	    (src_clk == STM32_SRC_PCLK2) ||
+	    (src_clk == STM32_SRC_PCLK3) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
 	    ((src_clk == STM32_SRC_HSI) && IS_ENABLED(STM32_HSI_ENABLED)) ||
 	    ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
@@ -226,16 +230,20 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 	case STM32_CLOCK_BUS_AHB1:
 	case STM32_CLOCK_BUS_AHB2:
 	case STM32_CLOCK_BUS_AHB4:
+	case STM32_SRC_HCLK:
 		*rate = ahb_clock;
 		break;
 	case STM32_CLOCK_BUS_APB1:
 	case STM32_CLOCK_BUS_APB1_2:
+	case STM32_SRC_PCLK1:
 		*rate = apb1_clock;
 		break;
 	case STM32_CLOCK_BUS_APB2:
+	case STM32_SRC_PCLK2:
 		*rate = apb2_clock;
 		break;
 	case STM32_CLOCK_BUS_APB3:
+	case STM32_SRC_PCLK3:
 		*rate = apb3_clock;
 		break;
 	case STM32_SRC_SYSCLK:

drivers/clock_control/clock_stm32_ll_u5.c

@@ -124,6 +124,10 @@ static uint32_t get_sysclk_frequency(void)
 int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
+	    (src_clk == STM32_SRC_HCLK) ||
+	    (src_clk == STM32_SRC_PCLK1) ||
+	    (src_clk == STM32_SRC_PCLK2) ||
+	    (src_clk == STM32_SRC_PCLK3) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
 	    ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
 	    ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
@@ -234,16 +238,20 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 	case STM32_CLOCK_BUS_AHB2:
 	case STM32_CLOCK_BUS_AHB2_2:
 	case STM32_CLOCK_BUS_AHB3:
+	case STM32_SRC_HCLK:
 		*rate = ahb_clock;
 		break;
 	case STM32_CLOCK_BUS_APB1:
 	case STM32_CLOCK_BUS_APB1_2:
+	case STM32_SRC_PCLK1:
 		*rate = apb1_clock;
 		break;
 	case STM32_CLOCK_BUS_APB2:
+	case STM32_SRC_PCLK2:
 		*rate = apb2_clock;
 		break;
 	case STM32_CLOCK_BUS_APB3:
+	case STM32_SRC_PCLK3:
 		*rate = apb3_clock;
 		break;
 	case STM32_SRC_SYSCLK:

drivers/clock_control/clock_stm32_ll_wba.c

@@ -44,6 +44,11 @@ static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
 int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
+	    (src_clk == STM32_SRC_HCLK1) ||
+	    (src_clk == STM32_SRC_HCLK5) ||
+	    (src_clk == STM32_SRC_PCLK1) ||
+	    (src_clk == STM32_SRC_PCLK2) ||
+	    (src_clk == STM32_SRC_PCLK7) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
 	    ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
 	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
@@ -194,19 +199,24 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 	case STM32_CLOCK_BUS_AHB1:
 	case STM32_CLOCK_BUS_AHB2:
 	case STM32_CLOCK_BUS_AHB4:
+	case STM32_SRC_HCLK1:
 		*rate = ahb_clock;
 		break;
 	case STM32_CLOCK_BUS_AHB5:
+	case STM32_SRC_HCLK5:
 		*rate = ahb5_clock;
 		break;
 	case STM32_CLOCK_BUS_APB1:
 	case STM32_CLOCK_BUS_APB1_2:
+	case STM32_SRC_PCLK1:
 		*rate = apb1_clock;
 		break;
 	case STM32_CLOCK_BUS_APB2:
+	case STM32_SRC_PCLK2:
 		*rate = apb2_clock;
 		break;
 	case STM32_CLOCK_BUS_APB7:
+	case STM32_SRC_PCLK7:
 		*rate = apb7_clock;
 		break;
 	case STM32_SRC_SYSCLK: