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[RISCV][GISel] Remove s32 support for G_ADD/SUB/AND/OR/XOR on RV64.
This is consistent with other patches to remove s32 recently.
1 parent eaed095 commit c280522

39 files changed

+1544
-1677
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,10 +132,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
132132
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};
133133

134134
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
135-
.legalFor({s32, sXLen})
135+
.legalFor({sXLen})
136136
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
137137
.widenScalarToNextPow2(0)
138-
.clampScalar(0, s32, sXLen);
138+
.clampScalar(0, sXLen, sXLen);
139139

140140
getActionDefinitionsBuilder(
141141
{G_UADDE, G_UADDO, G_USUBE, G_USUBO}).lower();

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,6 @@ def : StPat<store, SD, GPR, PtrVT>;
173173
// RV64 i32 patterns not used by SelectionDAG
174174
//===----------------------------------------------------------------------===//
175175

176-
def simm12i32 : ImmLeaf<i32, [{return isInt<12>(Imm);}]>;
177176
def uimm5i32 : ImmLeaf<i32, [{return isUInt<5>(Imm);}]>;
178177

179178
def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
@@ -196,35 +195,17 @@ def : Pat<(anyext GPR:$src), (COPY GPR:$src)>;
196195
def : Pat<(sext GPR:$src), (ADDIW GPR:$src, 0)>;
197196
def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;
198197

199-
def : PatGprGpr<add, ADDW, i32, i32>;
200-
def : PatGprGpr<sub, SUBW, i32, i32>;
201-
def : PatGprGpr<and, AND, i32, i32>;
202-
def : PatGprGpr<or, OR, i32, i32>;
203-
def : PatGprGpr<xor, XOR, i32, i32>;
204198
def : PatGprGpr<shl, SLLW, i32, i32>;
205199
def : PatGprGpr<srl, SRLW, i32, i32>;
206200
def : PatGprGpr<sra, SRAW, i32, i32>;
207201

208-
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
209-
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
210-
def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
211-
(ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
212-
def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
213-
(ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
214-
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
215-
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
216-
217202
def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
218203
(SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
219204
def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
220205
(SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
221206
def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
222207
(SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
223208

224-
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
225-
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
226-
(i64 (XLenSubTrailingOnes $mask)))>;
227-
228209
// Use sext if the sign bit of the input is 0.
229210
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
230211
}
@@ -245,31 +226,13 @@ def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
245226
let Predicates = [HasStdExtZbb, IsRV64] in {
246227
def : Pat<(i32 (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
247228
def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
248-
249-
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
250-
} // Predicates = [HasStdExtZbb, IsRV64]
251-
252-
let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
253-
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
254229
} // Predicates = [HasStdExtZbb, IsRV64]
255230

256-
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
257-
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
258-
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
259-
def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
260-
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
261-
262231
let Predicates = [HasStdExtZba, IsRV64] in {
263232
def : Pat<(shl (i64 (zext GPR:$rs1)), uimm5:$shamt),
264233
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;
265234

266235
def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
267236
(ADD_UW GPR:$rs1, GPR:$rs2)>;
268237
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
269-
270-
foreach i = {1,2,3} in {
271-
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
272-
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
273-
(shxadd GPR:$rs1, GPR:$rs2)>;
274-
}
275238
}

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll‎

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define i8 @add_i8(i8 %a, i8 %b) {
1414
;
1515
; RV64IM-LABEL: add_i8:
1616
; RV64IM: # %bb.0: # %entry
17-
; RV64IM-NEXT: addw a0, a0, a1
17+
; RV64IM-NEXT: add a0, a0, a1
1818
; RV64IM-NEXT: ret
1919
entry:
2020
%0 = add i8 %a, %b
@@ -33,11 +33,11 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
3333
;
3434
; RV64IM-LABEL: add_i8_signext_i32:
3535
; RV64IM: # %bb.0: # %entry
36-
; RV64IM-NEXT: slli a0, a0, 24
37-
; RV64IM-NEXT: sraiw a0, a0, 24
38-
; RV64IM-NEXT: slli a1, a1, 24
39-
; RV64IM-NEXT: sraiw a1, a1, 24
40-
; RV64IM-NEXT: addw a0, a0, a1
36+
; RV64IM-NEXT: slli a0, a0, 56
37+
; RV64IM-NEXT: srai a0, a0, 56
38+
; RV64IM-NEXT: slli a1, a1, 56
39+
; RV64IM-NEXT: srai a1, a1, 56
40+
; RV64IM-NEXT: add a0, a0, a1
4141
; RV64IM-NEXT: ret
4242
entry:
4343
%0 = sext i8 %a to i32
@@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
5858
; RV64IM: # %bb.0: # %entry
5959
; RV64IM-NEXT: andi a0, a0, 255
6060
; RV64IM-NEXT: andi a1, a1, 255
61-
; RV64IM-NEXT: addw a0, a0, a1
61+
; RV64IM-NEXT: add a0, a0, a1
6262
; RV64IM-NEXT: ret
6363
entry:
6464
%0 = zext i8 %a to i32
@@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) {
7878
;
7979
; RV64IM-LABEL: add_i32:
8080
; RV64IM: # %bb.0: # %entry
81-
; RV64IM-NEXT: addw a0, a0, a1
81+
; RV64IM-NEXT: add a0, a0, a1
8282
; RV64IM-NEXT: ret
8383
entry:
8484
%0 = add i32 %a, %b
@@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) {
9393
;
9494
; RV64IM-LABEL: addi_i32:
9595
; RV64IM: # %bb.0: # %entry
96-
; RV64IM-NEXT: addiw a0, a0, 1234
96+
; RV64IM-NEXT: addi a0, a0, 1234
9797
; RV64IM-NEXT: ret
9898
entry:
9999
%0 = add i32 %a, 1234
@@ -108,7 +108,7 @@ define i32 @sub_i32(i32 %a, i32 %b) {
108108
;
109109
; RV64IM-LABEL: sub_i32:
110110
; RV64IM: # %bb.0: # %entry
111-
; RV64IM-NEXT: subw a0, a0, a1
111+
; RV64IM-NEXT: sub a0, a0, a1
112112
; RV64IM-NEXT: ret
113113
entry:
114114
%0 = sub i32 %a, %b
@@ -123,7 +123,10 @@ define i32 @subi_i32(i32 %a) {
123123
;
124124
; RV64IM-LABEL: subi_i32:
125125
; RV64IM: # %bb.0: # %entry
126-
; RV64IM-NEXT: addiw a0, a0, -1234
126+
; RV64IM-NEXT: li a1, 1
127+
; RV64IM-NEXT: slli a1, a1, 32
128+
; RV64IM-NEXT: addi a1, a1, -1234
129+
; RV64IM-NEXT: add a0, a0, a1
127130
; RV64IM-NEXT: ret
128131
entry:
129132
%0 = sub i32 %a, 1234
@@ -138,7 +141,7 @@ define i32 @neg_i32(i32 %a) {
138141
;
139142
; RV64IM-LABEL: neg_i32:
140143
; RV64IM: # %bb.0: # %entry
141-
; RV64IM-NEXT: negw a0, a0
144+
; RV64IM-NEXT: neg a0, a0
142145
; RV64IM-NEXT: ret
143146
entry:
144147
%0 = sub i32 0, %a

‎llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll‎

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV32
33
; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV64
44

5+
; FIXME: andi a0, a0, 1 is unneeded
56
define i2 @bitreverse_i2(i2 %x) {
67
; RV32-LABEL: bitreverse_i2:
78
; RV32: # %bb.0:
@@ -18,12 +19,14 @@ define i2 @bitreverse_i2(i2 %x) {
1819
; RV64-NEXT: andi a1, a1, 2
1920
; RV64-NEXT: andi a0, a0, 3
2021
; RV64-NEXT: srliw a0, a0, 1
22+
; RV64-NEXT: andi a0, a0, 1
2123
; RV64-NEXT: or a0, a1, a0
2224
; RV64-NEXT: ret
2325
%rev = call i2 @llvm.bitreverse.i2(i2 %x)
2426
ret i2 %rev
2527
}
2628

29+
; FIXME: andi a0, a0, 1 is unneeded
2730
define i3 @bitreverse_i3(i3 %x) {
2831
; RV32-LABEL: bitreverse_i3:
2932
; RV32: # %bb.0:
@@ -44,12 +47,14 @@ define i3 @bitreverse_i3(i3 %x) {
4447
; RV64-NEXT: andi a2, a0, 2
4548
; RV64-NEXT: or a1, a1, a2
4649
; RV64-NEXT: srliw a0, a0, 2
50+
; RV64-NEXT: andi a0, a0, 1
4751
; RV64-NEXT: or a0, a1, a0
4852
; RV64-NEXT: ret
4953
%rev = call i3 @llvm.bitreverse.i3(i3 %x)
5054
ret i3 %rev
5155
}
5256

57+
; FIXME: andi a0, a0, 1 is unneeded
5358
define i4 @bitreverse_i4(i4 %x) {
5459
; RV32-LABEL: bitreverse_i4:
5560
; RV32: # %bb.0:
@@ -78,12 +83,14 @@ define i4 @bitreverse_i4(i4 %x) {
7883
; RV64-NEXT: andi a2, a2, 2
7984
; RV64-NEXT: or a1, a1, a2
8085
; RV64-NEXT: srliw a0, a0, 3
86+
; RV64-NEXT: andi a0, a0, 1
8187
; RV64-NEXT: or a0, a1, a0
8288
; RV64-NEXT: ret
8389
%rev = call i4 @llvm.bitreverse.i4(i4 %x)
8490
ret i4 %rev
8591
}
8692

93+
; FIXME: andi a0, a0, 1 is unneeded
8794
define i7 @bitreverse_i7(i7 %x) {
8895
; RV32-LABEL: bitreverse_i7:
8996
; RV32: # %bb.0:
@@ -128,6 +135,7 @@ define i7 @bitreverse_i7(i7 %x) {
128135
; RV64-NEXT: or a2, a2, a3
129136
; RV64-NEXT: or a1, a1, a2
130137
; RV64-NEXT: srliw a0, a0, 6
138+
; RV64-NEXT: andi a0, a0, 1
131139
; RV64-NEXT: or a0, a1, a0
132140
; RV64-NEXT: ret
133141
%rev = call i7 @llvm.bitreverse.i7(i7 %x)
@@ -177,24 +185,27 @@ define i24 @bitreverse_i24(i24 %x) {
177185
; RV64-NEXT: and a0, a0, a2
178186
; RV64-NEXT: srliw a0, a0, 16
179187
; RV64-NEXT: or a0, a0, a1
180-
; RV64-NEXT: lui a1, 1048335
181-
; RV64-NEXT: addi a1, a1, 240
188+
; RV64-NEXT: lui a1, 65521
189+
; RV64-NEXT: addi a1, a1, -241
190+
; RV64-NEXT: slli a1, a1, 4
182191
; RV64-NEXT: and a3, a1, a2
183192
; RV64-NEXT: and a3, a0, a3
184193
; RV64-NEXT: srliw a3, a3, 4
185194
; RV64-NEXT: slli a0, a0, 4
186195
; RV64-NEXT: and a0, a0, a1
187196
; RV64-NEXT: or a0, a3, a0
188-
; RV64-NEXT: lui a1, 1047757
189-
; RV64-NEXT: addi a1, a1, -820
197+
; RV64-NEXT: lui a1, 261939
198+
; RV64-NEXT: addi a1, a1, 819
199+
; RV64-NEXT: slli a1, a1, 2
190200
; RV64-NEXT: and a3, a1, a2
191201
; RV64-NEXT: and a3, a0, a3
192202
; RV64-NEXT: srliw a3, a3, 2
193203
; RV64-NEXT: slli a0, a0, 2
194204
; RV64-NEXT: and a0, a0, a1
195205
; RV64-NEXT: or a0, a3, a0
196-
; RV64-NEXT: lui a1, 1047211
197-
; RV64-NEXT: addiw a1, a1, -1366
206+
; RV64-NEXT: lui a1, 523605
207+
; RV64-NEXT: addiw a1, a1, 1365
208+
; RV64-NEXT: slli a1, a1, 1
198209
; RV64-NEXT: and a2, a1, a2
199210
; RV64-NEXT: and a2, a0, a2
200211
; RV64-NEXT: srliw a2, a2, 1

‎llvm/test/CodeGen/RISCV/GlobalISel/combine.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ define i32 @constant_to_rhs(i32 %x) {
2020
; RV64-O0: # %bb.0:
2121
; RV64-O0-NEXT: mv a1, a0
2222
; RV64-O0-NEXT: li a0, 1
23-
; RV64-O0-NEXT: addw a0, a0, a1
23+
; RV64-O0-NEXT: add a0, a0, a1
2424
; RV64-O0-NEXT: ret
2525
;
2626
; RV32-OPT-LABEL: constant_to_rhs:
@@ -30,7 +30,7 @@ define i32 @constant_to_rhs(i32 %x) {
3030
;
3131
; RV64-OPT-LABEL: constant_to_rhs:
3232
; RV64-OPT: # %bb.0:
33-
; RV64-OPT-NEXT: addiw a0, a0, 1
33+
; RV64-OPT-NEXT: addi a0, a0, 1
3434
; RV64-OPT-NEXT: ret
3535
%a = add i32 1, %x
3636
ret i32 %a

‎llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ define i16 @constant_fold_barrier_i16(i16 %x, i16 %y) {
88
; RV64-NEXT: li a1, 1
99
; RV64-NEXT: slli a1, a1, 11
1010
; RV64-NEXT: and a0, a0, a1
11-
; RV64-NEXT: addiw a1, a1, 289
11+
; RV64-NEXT: addi a1, a1, 289
1212
; RV64-NEXT: or a0, a0, a1
1313
; RV64-NEXT: ret
1414
entry:

‎llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll‎

Lines changed: 20 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -96,19 +96,12 @@ define ptr @freeze_ptr(ptr %x) {
9696
%struct.T = type { i32, i32 }
9797

9898
define i32 @freeze_struct(ptr %p) {
99-
; RV32-LABEL: freeze_struct:
100-
; RV32: # %bb.0:
101-
; RV32-NEXT: lw a1, 0(a0)
102-
; RV32-NEXT: lw a0, 4(a0)
103-
; RV32-NEXT: add a0, a1, a0
104-
; RV32-NEXT: ret
105-
;
106-
; RV64-LABEL: freeze_struct:
107-
; RV64: # %bb.0:
108-
; RV64-NEXT: lw a1, 0(a0)
109-
; RV64-NEXT: lw a0, 4(a0)
110-
; RV64-NEXT: addw a0, a1, a0
111-
; RV64-NEXT: ret
99+
; CHECK-LABEL: freeze_struct:
100+
; CHECK: # %bb.0:
101+
; CHECK-NEXT: lw a1, 0(a0)
102+
; CHECK-NEXT: lw a0, 4(a0)
103+
; CHECK-NEXT: add a0, a1, a0
104+
; CHECK-NEXT: ret
112105
%s = load %struct.T, ptr %p
113106
%y1 = freeze %struct.T %s
114107
%v1 = extractvalue %struct.T %y1, 0
@@ -118,19 +111,12 @@ define i32 @freeze_struct(ptr %p) {
118111
}
119112

120113
define i32 @freeze_anonstruct(ptr %p) {
121-
; RV32-LABEL: freeze_anonstruct:
122-
; RV32: # %bb.0:
123-
; RV32-NEXT: lw a1, 0(a0)
124-
; RV32-NEXT: lw a0, 4(a0)
125-
; RV32-NEXT: add a0, a1, a0
126-
; RV32-NEXT: ret
127-
;
128-
; RV64-LABEL: freeze_anonstruct:
129-
; RV64: # %bb.0:
130-
; RV64-NEXT: lw a1, 0(a0)
131-
; RV64-NEXT: lw a0, 4(a0)
132-
; RV64-NEXT: addw a0, a1, a0
133-
; RV64-NEXT: ret
114+
; CHECK-LABEL: freeze_anonstruct:
115+
; CHECK: # %bb.0:
116+
; CHECK-NEXT: lw a1, 0(a0)
117+
; CHECK-NEXT: lw a0, 4(a0)
118+
; CHECK-NEXT: add a0, a1, a0
119+
; CHECK-NEXT: ret
134120
%s = load {i32, i32}, ptr %p
135121
%y1 = freeze {i32, i32} %s
136122
%v1 = extractvalue {i32, i32} %y1, 0
@@ -155,9 +141,9 @@ define i32 @freeze_anonstruct2(ptr %p) {
155141
; RV64-NEXT: lh a1, 4(a0)
156142
; RV64-NEXT: lw a0, 0(a0)
157143
; RV64-NEXT: lui a2, 16
158-
; RV64-NEXT: addi a2, a2, -1
144+
; RV64-NEXT: addiw a2, a2, -1
159145
; RV64-NEXT: and a1, a1, a2
160-
; RV64-NEXT: addw a0, a0, a1
146+
; RV64-NEXT: add a0, a0, a1
161147
; RV64-NEXT: ret
162148
%s = load {i32, i16}, ptr %p
163149
%y1 = freeze {i32, i16} %s
@@ -169,19 +155,12 @@ define i32 @freeze_anonstruct2(ptr %p) {
169155
}
170156

171157
define i32 @freeze_array(ptr %p) nounwind {
172-
; RV32-LABEL: freeze_array:
173-
; RV32: # %bb.0:
174-
; RV32-NEXT: lw a1, 0(a0)
175-
; RV32-NEXT: lw a0, 4(a0)
176-
; RV32-NEXT: add a0, a1, a0
177-
; RV32-NEXT: ret
178-
;
179-
; RV64-LABEL: freeze_array:
180-
; RV64: # %bb.0:
181-
; RV64-NEXT: lw a1, 0(a0)
182-
; RV64-NEXT: lw a0, 4(a0)
183-
; RV64-NEXT: addw a0, a1, a0
184-
; RV64-NEXT: ret
158+
; CHECK-LABEL: freeze_array:
159+
; CHECK: # %bb.0:
160+
; CHECK-NEXT: lw a1, 0(a0)
161+
; CHECK-NEXT: lw a0, 4(a0)
162+
; CHECK-NEXT: add a0, a1, a0
163+
; CHECK-NEXT: ret
185164
%s = load [2 x i32], ptr %p
186165
%y1 = freeze [2 x i32] %s
187166
%v1 = extractvalue [2 x i32] %y1, 0

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