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tgtakaokatgtakaoka
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[i8096] Check for mul/div instruction operands (#129)
1 parent 1f0e5f6 commit d4eb2b2

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7 files changed

+139
-7
lines changed

7 files changed

+139
-7
lines changed

‎src/asm_i8096.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -184,6 +184,8 @@ void AsmI8096::emitAop(AsmInsn &insn, AddrMode mode, const Operand &op) const {
184184
if (waop && !isWreg(val16))
185185
insn.setErrorIf(op, OPERAND_NOT_ALIGNED);
186186
if (op.isOK() && !op.val.overflow(UINT8_MAX)) {
187+
if (insn.mulDivInsn() && ioAddress(val16))
188+
insn.setErrorIf(op, ILLEGAL_REGISTER);
187189
insn.embedAa(AA_REG);
188190
insn.emitOperand8(val16);
189191
} else {
@@ -278,6 +280,8 @@ void AsmI8096::emitOperand(AsmInsn &insn, AddrMode mode, const Operand &op) cons
278280
case M_BREG:
279281
if (op.val.overflow(UINT8_MAX))
280282
insn.setErrorIf(op, ILLEGAL_REGISTER);
283+
if (insn.mulDivInsn() && ioAddress(val16))
284+
insn.setErrorIf(op, ILLEGAL_REGISTER);
281285
insn.emitOperand8(val16);
282286
return;
283287
case M_INDIR:

‎src/config_i8096.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ struct Config : ConfigImpl<CpuType, ADDRESS_16BIT, ADDRESS_BYTE, OPCODE_8BIT, EN
3333

3434
protected:
3535
bool ioAddress(uint16_t addr) const {
36-
return addr >= 2 && addr < 0x18;
36+
return addr >= 0x02 && addr < 0x18;
3737
}
3838
};
3939

‎src/dis_i8096.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@ StrBuffer &DisI8096::outRegister(StrBuffer &out, DisInsn &insn, uint8_t regno, b
5858
if (ioAddress(regno))
5959
insn.setError(out, ILLEGAL_REGISTER);
6060
out.letter('[');
61+
} else if (insn.mulDivInsn() && ioAddress(regno)) {
62+
insn.setError(out, ILLEGAL_REGISTER);
6163
}
6264
outDec(out, regno, 8);
6365
if (indir)

‎src/insn_i8096.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ struct EntryInsn : EntryInsnPrefix<Config, Entry> {
3131
AddrMode src1() const { return flags().src1(); }
3232
AddrMode src2() const { return flags().src2(); }
3333
void embedAa(AaMode aa) { embed(uint8_t(aa)); }
34+
bool mulDivInsn() const;
3435
};
3536

3637
struct Operand final : ErrorAt {

‎src/table_i8096.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,17 @@ Error TableI8096::searchCpuName(StrScanner &name, CpuType &cpuType) const {
396396
return UNSUPPORTED_CPU;
397397
}
398398

399+
bool EntryInsn::mulDivInsn() const {
400+
const auto pre = prefix();
401+
if (pre == 0 || pre == 0xFE) {
402+
const auto opc = opCode();
403+
const auto opc_lo = opc & 0x0F;
404+
const auto opc_hi = opc & 0xF0;
405+
return opc_lo >= 0x0C && (opc_hi >= 0x40 && opc_hi <= 0x90);
406+
}
407+
return false;
408+
}
409+
399410
const TableI8096 TABLE;
400411

401412
} // namespace i8096

‎test/test_asm_i8096.cpp‎

Lines changed: 58 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,8 @@ void test_2_operands() {
7373
ONAL("ADD 120, 5635H[0]", "5635H[0]", 0x67, 0x01, 0x35, 0x56, 0x78);
7474
TEST("ADD 120, 5634H", 0x67, 0x01, 0x34, 0x56, 0x78);
7575
ONAL("ADD 120, 5635H", "5635H", 0x67, 0x01, 0x35, 0x56, 0x78);
76+
TEST("ADD 16, 32", 0x64, 0x20, 0x10);
77+
TEST("ADD 52, 16", 0x64, 0x10, 0x34);
7678

7779
ERRT("ADD 52, [22]", ILLEGAL_REGISTER, "[22]", 0x66, 0x16, 0x34);
7880
ERRT("ADD 52, [2]+", ILLEGAL_REGISTER, "[2]+", 0x66, 0x03, 0x34);
@@ -155,19 +157,26 @@ void test_2_operands() {
155157
ONAL("CMPL 52, 33", "33", 0xC5, 0x21, 0x34);
156158
}
157159

158-
TEST("MUL 52, 16", 0xFE, 0x6C, 0x10, 0x34);
160+
TEST("MUL 52, 32", 0xFE, 0x6C, 0x20, 0x34);
159161
TEST("MUL 84, #3412H", 0xFE, 0x6D, 0x12, 0x34, 0x54);
160162
TEST("MUL 52, [32]", 0xFE, 0x6E, 0x20, 0x34);
161163
TEST("MUL 52, [32]+", 0xFE, 0x6E, 0x21, 0x34);
162164
TEST("MUL 84, 52[32]", 0xFE, 0x6F, 0x20, 0x34, 0x54);
163165
TEST("MUL 120, 5634H[32]", 0xFE, 0x6F, 0x21, 0x34, 0x56, 0x78);
166+
ERRT("MUL 16, 32", ILLEGAL_REGISTER, "16, 32", 0xFE, 0x6C, 0x20, 0x10);
167+
ERRT("MUL 52, 16", ILLEGAL_REGISTER, "16", 0xFE, 0x6C, 0x10, 0x34);
168+
ERRT("MUL 16, #3412H", ILLEGAL_REGISTER, "16, #3412H", 0xFE, 0x6D, 0x12, 0x34, 0x10);
169+
ERRT("MUL 16, [32]+", ILLEGAL_REGISTER, "16, [32]+", 0xFE, 0x6E, 0x21, 0x10);
170+
ERRT("MUL 16, 52[32]", ILLEGAL_REGISTER, "16, 52[32]", 0xFE, 0x6F, 0x20, 0x34, 0x10);
164171

165172
TEST("MULB 36, 32", 0xFE, 0x7C, 0x20, 0x24);
166173
TEST("MULB 36, #32", 0xFE, 0x7D, 0x20, 0x24);
167174
TEST("MULB 36, [32]", 0xFE, 0x7E, 0x20, 0x24);
168175
TEST("MULB 36, [32]+", 0xFE, 0x7E, 0x21, 0x24);
169176
TEST("MULB 52, 35[32]", 0xFE, 0x7F, 0x20, 0x23, 0x34);
170177
TEST("MULB 70, 3423H[32]", 0xFE, 0x7F, 0x21, 0x23, 0x34, 0x46);
178+
ERRT("MULB 16, 33", ILLEGAL_REGISTER, "16, 33", 0xFE, 0x7C, 0x21, 0x10);
179+
ERRT("MULB 36, 16", ILLEGAL_REGISTER, "16", 0xFE, 0x7C, 0x10, 0x24);
171180

172181
TEST("MULU 52, 32", 0x6C, 0x20, 0x34);
173182
ONAL("MULU 52, 33", "33", 0x6C, 0x21, 0x34);
@@ -185,41 +194,53 @@ void test_2_operands() {
185194
ONAL("MULU 120, 5633H[33]", "5633H[33]", 0x6F, 0x21, 0x33, 0x56, 0x78);
186195
TEST("MULU 120, 5632H", 0x6F, 0x01, 0x32, 0x56, 0x78);
187196
ONAL("MULU 120, 5633H", "5633H", 0x6F, 0x01, 0x33, 0x56, 0x78);
197+
ERRT("MULU 16, 32", ILLEGAL_REGISTER, "16, 32", 0x6C, 0x20, 0x10);
198+
ERRT("MULU 52, 16", ILLEGAL_REGISTER, "16", 0x6C, 0x10, 0x34);
188199

189200
TEST("MULUB 36, 32", 0x7C, 0x20, 0x24);
190201
TEST("MULUB 36, #32", 0x7D, 0x20, 0x24);
191202
TEST("MULUB 36, [32]", 0x7E, 0x20, 0x24);
192203
TEST("MULUB 36, [32]+", 0x7E, 0x21, 0x24);
193204
TEST("MULUB 52, 35[32]", 0x7F, 0x20, 0x23, 0x34);
194205
TEST("MULUB 70, 3423H[32]", 0x7F, 0x21, 0x23, 0x34, 0x46);
206+
ERRT("MULUB 16, 33", ILLEGAL_REGISTER, "16, 33", 0x7C, 0x21, 0x10);
207+
ERRT("MULUB 36, 16", ILLEGAL_REGISTER, "16", 0x7C, 0x10, 0x24);
195208

196209
TEST("DIV 52, 32", 0xFE, 0x8C, 0x20, 0x34);
197210
TEST("DIV 84, #3412H", 0xFE, 0x8D, 0x12, 0x34, 0x54);
198211
TEST("DIV 52, [32]", 0xFE, 0x8E, 0x20, 0x34);
199212
TEST("DIV 52, [32]+", 0xFE, 0x8E, 0x21, 0x34);
200213
TEST("DIV 84, 52[32]", 0xFE, 0x8F, 0x20, 0x34, 0x54);
201214
TEST("DIV 120, 5634H[32]", 0xFE, 0x8F, 0x21, 0x34, 0x56, 0x78);
215+
ERRT("DIV 16, 32", ILLEGAL_REGISTER, "16, 32", 0xFE, 0x8C, 0x20, 0x10);
216+
ERRT("DIV 52, 16", ILLEGAL_REGISTER, "16", 0xFE, 0x8C, 0x10, 0x34);
202217

203218
TEST("DIVB 36, 32", 0xFE, 0x9C, 0x20, 0x24);
204219
TEST("DIVB 36, #32", 0xFE, 0x9D, 0x20, 0x24);
205220
TEST("DIVB 36, [32]", 0xFE, 0x9E, 0x20, 0x24);
206221
TEST("DIVB 36, [32]+", 0xFE, 0x9E, 0x21, 0x24);
207222
TEST("DIVB 52, 35[32]", 0xFE, 0x9F, 0x20, 0x23, 0x34);
208223
TEST("DIVB 70, 3423H[32]", 0xFE, 0x9F, 0x21, 0x23, 0x34, 0x46);
224+
ERRT("DIVB 16, 33", ILLEGAL_REGISTER, "16, 33", 0xFE, 0x9C, 0x21, 0x10);
225+
ERRT("DIVB 36, 16", ILLEGAL_REGISTER, "16", 0xFE, 0x9C, 0x10, 0x24);
209226

210227
TEST("DIVU 52, 32", 0x8C, 0x20, 0x34);
211228
TEST("DIVU 84, #3412H", 0x8D, 0x12, 0x34, 0x54);
212229
TEST("DIVU 52, [32]", 0x8E, 0x20, 0x34);
213230
TEST("DIVU 52, [32]+", 0x8E, 0x21, 0x34);
214231
TEST("DIVU 84, 52[32]", 0x8F, 0x20, 0x34, 0x54);
215232
TEST("DIVU 120, 5634H[32]", 0x8F, 0x21, 0x34, 0x56, 0x78);
233+
ERRT("DIVU 16, 32", ILLEGAL_REGISTER, "16, 32", 0x8C, 0x20, 0x10);
234+
ERRT("DIVU 52, 16", ILLEGAL_REGISTER, "16", 0x8C, 0x10, 0x34);
216235

217236
TEST("DIVUB 36, 32", 0x9C, 0x20, 0x24);
218237
TEST("DIVUB 36, #32", 0x9D, 0x20, 0x24);
219238
TEST("DIVUB 36, [32]", 0x9E, 0x20, 0x24);
220239
TEST("DIVUB 36, [32]+", 0x9E, 0x21, 0x24);
221240
TEST("DIVUB 52, 35[32]", 0x9F, 0x20, 0x23, 0x34);
222241
TEST("DIVUB 70, 3423H[32]", 0x9F, 0x21, 0x23, 0x34, 0x46);
242+
ERRT("DIVUB 16, 33", ILLEGAL_REGISTER, "16, 33", 0x9C, 0x21, 0x10);
243+
ERRT("DIVUB 36, 16", ILLEGAL_REGISTER, "16", 0x9C, 0x10, 0x24);
223244

224245
TEST("AND 52, 32", 0x60, 0x20, 0x34);
225246
TEST("AND 86, #3412H", 0x61, 0x12, 0x34, 0x56);
@@ -315,6 +336,24 @@ void test_3_operands() {
315336
ONAL("MUL 152, 120, 5634H[33]", "5634H[33]", 0xFE, 0x4F, 0x21, 0x34, 0x56, 0x78, 0x98);
316337
TEST("MUL 152, 120, 5634H", 0xFE, 0x4F, 0x01, 0x34, 0x56, 0x78, 0x98);
317338
ONAL("MUL 152, 120, 5635H", "5635H", 0xFE, 0x4F, 0x01, 0x35, 0x56, 0x78, 0x98);
339+
ERRT("MUL 16, 52, 32",
340+
ILLEGAL_REGISTER, "16, 52, 32", 0xFE, 0x4C, 0x20, 0x34, 0x10);
341+
ERRT("MUL 84, 16, 32",
342+
ILLEGAL_REGISTER, "16, 32", 0xFE, 0x4C, 0x20, 0x10, 0x54);
343+
ERRT("MUL 84, 52, 16",
344+
ILLEGAL_REGISTER, "16", 0xFE, 0x4C, 0x10, 0x34, 0x54);
345+
ERRT("MUL 16, 86, #3412H",
346+
ILLEGAL_REGISTER, "16, 86, #3412H", 0xFE, 0x4D, 0x12, 0x34, 0x56, 0x10);
347+
ERRT("MUL 120, 16, #3412H",
348+
ILLEGAL_REGISTER, "16, #3412H", 0xFE, 0x4D, 0x12, 0x34, 0x10, 0x78);
349+
ERRT("MUL 16, 52, [32]",
350+
ILLEGAL_REGISTER, "16, 52, [32]", 0xFE, 0x4E, 0x20, 0x34, 0x10);
351+
ERRT("MUL 84, 16, [32]+",
352+
ILLEGAL_REGISTER, "16, [32]+", 0xFE, 0x4E, 0x21, 0x10, 0x54);
353+
ERRT("MUL 16, 86, 52[32]",
354+
ILLEGAL_REGISTER, "16, 86, 52[32]", 0xFE, 0x4F, 0x20, 0x34, 0x56, 0x10);
355+
ERRT("MUL 120, 16, 52[32]",
356+
ILLEGAL_REGISTER, "16, 52[32]", 0xFE, 0x4F, 0x20, 0x34, 0x10, 0x78);
318357

319358
TEST("MULB 52, 35, 32", 0xFE, 0x5C, 0x20, 0x23, 0x34);
320359
TEST("MULB 52, 34, 33", 0xFE, 0x5C, 0x21, 0x22, 0x34);
@@ -324,6 +363,12 @@ void test_3_operands() {
324363
TEST("MULB 52, 35, [32]+", 0xFE, 0x5E, 0x21, 0x23, 0x34);
325364
TEST("MULB 70, 52, 35[32]", 0xFE, 0x5F, 0x20, 0x23, 0x34, 0x46);
326365
TEST("MULB 86, 69, 3423H[32]", 0xFE, 0x5F, 0x21, 0x23, 0x34, 0x45, 0x56);
366+
ERRT("MULB 16, 52, 32",
367+
ILLEGAL_REGISTER, "16, 52, 32", 0xFE, 0x5C, 0x20, 0x34, 0x10);
368+
ERRT("MULB 84, 16, 32",
369+
ILLEGAL_REGISTER, "16, 32", 0xFE, 0x5C, 0x20, 0x10, 0x54);
370+
ERRT("MULB 84, 52, 16",
371+
ILLEGAL_REGISTER, "16", 0xFE, 0x5C, 0x10, 0x34, 0x54);
327372

328373
TEST("MULU 84, 52, 32", 0x4C, 0x20, 0x34, 0x54);
329374
ONAL("MULU 84, 52, 33", "33", 0x4C, 0x21, 0x34, 0x54);
@@ -338,6 +383,12 @@ void test_3_operands() {
338383
TEST("MULU 84, 52, [32]+", 0x4E, 0x21, 0x34, 0x54);
339384
TEST("MULU 120, 86, 52[32]", 0x4F, 0x20, 0x34, 0x56, 0x78);
340385
TEST("MULU 152, 120, 5634H[32]", 0x4F, 0x21, 0x34, 0x56, 0x78, 0x98);
386+
ERRT("MULU 16, 52, 32",
387+
ILLEGAL_REGISTER, "16, 52, 32", 0x4C, 0x20, 0x34, 0x10);
388+
ERRT("MULU 84, 16, 32",
389+
ILLEGAL_REGISTER, "16, 32", 0x4C, 0x20, 0x10, 0x54);
390+
ERRT("MULU 84, 52, 16",
391+
ILLEGAL_REGISTER, "16", 0x4C, 0x10, 0x34, 0x54);
341392

342393
TEST("MULUB 52, 35, 33", 0x5C, 0x21, 0x23, 0x34);
343394
ONAL("MULUB 53, 34, 32", "53, 34, 32", 0x5C, 0x20, 0x22, 0x35);
@@ -347,6 +398,12 @@ void test_3_operands() {
347398
TEST("MULUB 52, 35, [32]+", 0x5E, 0x21, 0x23, 0x34);
348399
TEST("MULUB 70, 52, 35[32]", 0x5F, 0x20, 0x23, 0x34, 0x46);
349400
TEST("MULUB 86, 69, 3423H[32]", 0x5F, 0x21, 0x23, 0x34, 0x45, 0x56);
401+
ERRT("MULUB 16, 52, 32",
402+
ILLEGAL_REGISTER, "16, 52, 32", 0x5C, 0x20, 0x34, 0x10);
403+
ERRT("MULUB 84, 16, 32",
404+
ILLEGAL_REGISTER, "16, 32", 0x5C, 0x20, 0x10, 0x54);
405+
ERRT("MULUB 84, 52, 16",
406+
ILLEGAL_REGISTER, "16", 0x5C, 0x10, 0x34, 0x54);
350407

351408
TEST("AND 86, 52, 32", 0x40, 0x20, 0x34, 0x56);
352409
TEST("AND 120, 86, #3412H", 0x41, 0x12, 0x34, 0x56, 0x78);

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