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| 1 | +.. _i2s_driver: |
| 2 | + |
| 3 | +I2S IO Driver |
| 4 | +############# |
| 5 | + |
| 6 | +.. uml:: images/i2s_diagram.pu |
| 7 | + :caption: I2S IO Driver overview |
| 8 | + |
| 9 | +Configuration BLOB |
| 10 | +****************** |
| 11 | + |
| 12 | +The Configuration Blob is a build of block structures: |
| 13 | + - TDM slot Map, |
| 14 | + - I2S base registers, |
| 15 | + - MCLK configuration that allows for specifying the ratio for multiple |
| 16 | + dividers, |
| 17 | + - Aggregation configuration |
| 18 | + |
| 19 | +The ``I2sConfigurationBlobHeader`` begins with a signature followed by the BLOB |
| 20 | +version and size. |
| 21 | + |
| 22 | +.. code-block:: text |
| 23 | +
|
| 24 | + I2sConfigurationBlobHeader |
| 25 | + { |
| 26 | + signature and version { 0xEE, BLOB version } |
| 27 | + size in bytes |
| 28 | + } |
| 29 | +
|
| 30 | +Blob Configuration structure that follows the header depends on the BLOB version. |
| 31 | +Currently, only v2.5 is supported with the structure as follows: |
| 32 | + |
| 33 | +.. code-block:: text |
| 34 | +
|
| 35 | + I2sConfigurationBlob2 |
| 36 | + { |
| 37 | + I2sConfigurationBlobHeader |
| 38 | + TDM slot map ver.2 [I2S_TDM_MAX_SLOT_MAP_COUNT] |
| 39 | + I2S base registers |
| 40 | + MCLK configuration ver.2 |
| 41 | + { |
| 42 | + 2.5: Aggregation configuration |
| 43 | + } |
| 44 | + } |
| 45 | +
|
| 46 | +TDM Time Slots |
| 47 | +============== |
| 48 | + |
| 49 | +TDM time slots are statically assigned to streams by definition coming from |
| 50 | +ACPI. A single stream transmits data through time slots of a single time slot |
| 51 | +group. For example, 8 TDM time slots may be grouped by the following definition |
| 52 | +from ACPI: |
| 53 | + |
| 54 | +.. code-block:: text |
| 55 | +
|
| 56 | + tsd[0] = 0xFFFFFF43, tsd[1] = 0xFFFFFF01, ... |
| 57 | +
|
| 58 | +where: |
| 59 | + - Stream 0 specifies time_slot_group_index = 1, |
| 60 | + - Stream 1 uses time_slot_group_index = 0 |
| 61 | + |
| 62 | +that would mean that the 1st TDM slot is mapped to S0 Ch0; the 0th TDM slot is |
| 63 | +mapped to S0 Ch1; the 3rd TDM slot is mapped to S1 Ch0, and 4th TDM slot is |
| 64 | +mapped to S1 Ch1. |
| 65 | + |
| 66 | +.. graphviz:: images/i2s_tdm.dot |
| 67 | + :caption: I2S TDM |
| 68 | + |
| 69 | +Configuring BCLK Clock Input Source |
| 70 | +=================================== |
| 71 | + |
| 72 | +The I2S Link BCLK may be configured to use on the SoC available clock sources. |
| 73 | + |
| 74 | +Example BCLK clock sources: |
| 75 | + |
| 76 | + - XTAL Oscillator clock, |
| 77 | + - Audio Cardinal clock, |
| 78 | + - Audio PLL fixed clock, |
| 79 | + - MCLK |
| 80 | + |
| 81 | +Clock selection is programmed using values provided in the I2S Configuration |
| 82 | +BLOB for the MCDSS and MNDSS fields of the MDIVCTRL register. |
| 83 | + |
| 84 | +Link Synchronization (and Aggregation) |
| 85 | +====================================== |
| 86 | + |
| 87 | +Applies to sync of the streams started together as well as to synchronizing new |
| 88 | +stream with already running ones. |
| 89 | + |
| 90 | +.. note:: The same configuration must be set to all involved I2S ports. Specifically, |
| 91 | + all the ports must be driven by the same clock source. Moreover, there might |
| 92 | + be clock source SoC limitations. For example, in the TGL the M/N divider has |
| 93 | + to be selected for aggregation case. |
| 94 | + |
| 95 | +.. list-table:: |
| 96 | + :widths: 25 25 50 |
| 97 | + :header-rows: 1 |
| 98 | + |
| 99 | + * - Synchronized |
| 100 | + - Provider Mode |
| 101 | + - Consumer Mode |
| 102 | + * - Stream start |
| 103 | + - Yes |
| 104 | + - Yes |
| 105 | + * - BCLK, SFRM |
| 106 | + - Yes |
| 107 | + - By hooking up to the same I2S provider |
| 108 | + |
| 109 | +"Single" I2S links may be synchronized and aggregated by sending I2sSyncData to |
| 110 | +the I2S IO Driver. |
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