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arch: fw: sof-zephyr i2s io driver
sof-zephyr i2s io driver architecture chapter Signed-off-by: Michal Wasko <[email protected]>
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.. _i2s_driver:
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I2S IO Driver
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#############
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.. uml:: images/i2s_diagram.pu
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:caption: I2S IO Driver overview
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Configuration BLOB
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******************
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The Configuration Blob is a build of block structures:
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- TDM slot Map,
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- I2S base registers,
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- MCLK configuration that allows for specifying the ratio for multiple
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dividers,
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- Aggregation configuration
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The ``I2sConfigurationBlobHeader`` begins with a signature followed by the BLOB
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version and size.
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.. code-block:: text
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I2sConfigurationBlobHeader
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{
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signature and version { 0xEE, BLOB version }
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size in bytes
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}
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Blob Configuration structure that follows the header depends on the BLOB version.
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Currently, only v2.5 is supported with the structure as follows:
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.. code-block:: text
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I2sConfigurationBlob2
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{
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I2sConfigurationBlobHeader
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TDM slot map ver.2 [I2S_TDM_MAX_SLOT_MAP_COUNT]
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I2S base registers
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MCLK configuration ver.2
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{
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2.5: Aggregation configuration
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}
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}
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TDM Time Slots
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==============
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TDM time slots are statically assigned to streams by definition coming from
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ACPI. A single stream transmits data through time slots of a single time slot
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group. For example, 8 TDM time slots may be grouped by the following definition
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from ACPI:
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.. code-block:: text
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tsd[0] = 0xFFFFFF43, tsd[1] = 0xFFFFFF01, ...
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where:
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- Stream 0 specifies time_slot_group_index = 1,
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- Stream 1 uses time_slot_group_index = 0
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that would mean that the 1st TDM slot is mapped to S0 Ch0; the 0th TDM slot is
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mapped to S0 Ch1; the 3rd TDM slot is mapped to S1 Ch0, and 4th TDM slot is
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mapped to S1 Ch1.
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.. graphviz:: images/i2s_tdm.dot
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:caption: I2S TDM
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Configuring BCLK Clock Input Source
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===================================
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The I2S Link BCLK may be configured to use on the SoC available clock sources.
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Example BCLK clock sources:
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- XTAL Oscillator clock,
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- Audio Cardinal clock,
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- Audio PLL fixed clock,
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- MCLK
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Clock selection is programmed using values provided in the I2S Configuration
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BLOB for the MCDSS and MNDSS fields of the MDIVCTRL register.
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Link Synchronization (and Aggregation)
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======================================
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Applies to sync of the streams started together as well as to synchronizing new
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stream with already running ones.
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.. note:: The same configuration must be set to all involved I2S ports. Specifically,
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all the ports must be driven by the same clock source. Moreover, there might
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be clock source SoC limitations. For example, in the TGL the M/N divider has
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to be selected for aggregation case.
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.. list-table::
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:widths: 25 25 50
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:header-rows: 1
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* - Synchronized
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- Provider Mode
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- Consumer Mode
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* - Stream start
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- Yes
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- Yes
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* - BCLK, SFRM
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- Yes
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- By hooking up to the same I2S provider
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"Single" I2S links may be synchronized and aggregated by sending I2sSyncData to
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the I2S IO Driver.
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@startuml
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hide methods
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hide attributes
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class I2sSink --() Gateway
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class I2sSource --() Gateway
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class I2sDriver --() IoDriver
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class I2sChannel
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class I2sInputChannel
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I2sChannel --* I2sDriver
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I2sInputChannel --|> I2sChannel
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I2sOutputChannel --|> I2sChannel
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I2sSink --o I2sOutputChannel
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I2sSource --o I2sInputChannel
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@enduml
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digraph G {
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node [fontsize=10,shape=record,height=.1];
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splines=false
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subgraph clusterAcpi {
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label="tdm_ts_group[8]"; fontsize=10;
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tdm_acpi [label="<acpi0>FFFFFF43 |<acpi1>FFFFFF01 |..."];
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}
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subgraph clusterStr0 {
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label="Stream 0"; fontsize=10; color="#C4D600";
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str0_cfg [label="\{ time_slot_group_index=1\}"];
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str0_cfg -> tdm_acpi:acpi1 [style=dotted];
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str0 [label="<l>L |<r>R |... |<p>" color="#C4D600"];
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}
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subgraph clusterStr1 {
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label="Stream 1"; fontsize=10; color="#FFA300"
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str1_cfg [label="\{ time_slot_group_index=0\}"]
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str1_cfg -> tdm_acpi:acpi0 [style=dotted]
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str1 [label="<l>L |<r>R |..." color="#FFA300"]
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}
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str [label="<0>R |<1>L |<2> |<3>L |<4>R |<5> |<6> |<7> "]
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str0:l -> str:1
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str0:r -> str:0
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str1:l -> str:3
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str1:r -> str:4
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{rank=min; tdm_acpi}
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{rank=max; str}
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}

architectures/firmware/sof-zephyr/rtos_layer/io_drivers/index.rst

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:maxdepth: 1
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hda/hda_driver
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i2s/i2s_driver

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