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Design of DP scheduling with deadline calculations
this commit contains a detailed description of DP scheduling and DP deadline calculations Signed-off-by: Marcin Szkudlinski <[email protected]>
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‎architectures/firmware/sof-zephyr/mpp_layer/dp_scheduling.rst‎

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‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n100ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n10ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n15ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1_1.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n109ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n10ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n6ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1_2.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n109ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n0ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n16ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1_3.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n14ms of data\n" as buf1
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note bottom of buf1
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there was 109ms
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LL1 produced 5ms
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DP1 consumed 100ms
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109+5-100 = 14ms
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end note
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n100ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n11ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1_4.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n100ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n10ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n15ms of data\n" as buf3
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note bottom of buf3
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there was 11ms
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DP2 produced 90ms
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LL2 consumed 86ms
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11+90-86 = 15ms
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end note
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example1_5.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n105ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 100ms
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LPT: 5ms
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end note
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rectangle "BUF2\n\n0ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 10ms
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LPT: 9ms
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end note
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rectangle "BUF3\n\n20ms of data\n" as buf3
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note bottom of buf3
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there was 15ms
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DP2 produced 10ms
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LL2 consumed 5ms
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15+10-5 = 20ms
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end note
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example2.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n5ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 5ms
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LPT: 2ms
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end note
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rectangle "BUF2\n\n15ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 20ms
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LPT: 10ms
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end note
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rectangle "BUF3\n\n18ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example2_1.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n2ms of data\n" as buf1
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note bottom of buf1
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there was 5ms
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LL1 produced 2ms
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DP1 consumed 5ms
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5-5+2 = 2ms
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end note
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 5ms
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LPT: 2ms
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end note
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rectangle "BUF2\n\n20ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 20ms
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LPT: 10ms
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end note
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rectangle "BUF3\n\n16ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example2_1a.pu‎

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@startuml
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left to right direction
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(LL1) as mod1 #f6ed80
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rectangle "BUF1\n\n5ms of data\n" as buf1
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(DP1) as mod2 #ADD1B2
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note bottom of mod2
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period 5ms
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LPT: 2ms
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end note
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rectangle "BUF2\n\n20ms of data\n" as buf2
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(DP2) as mod3 #ADD1B2
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note bottom of mod3
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period 20ms
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LPT: 10ms
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end note
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rectangle "BUF3\n\n13ms of data\n" as buf3
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(LL2) as mod4 #f6ed80
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mod1--> buf1
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buf1 --> mod2
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mod2-->buf2
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buf2 --> mod3
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mod3-->buf3
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buf3 --> mod4
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@enduml

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