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arch: fw: mpp scheduling using zephyr
SOF MPP scheduling description and flows using zephyr rtos infrastructure Signed-off-by: Michal Wasko <[email protected]>
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‎architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/edf_scheduling.diag‎

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blockdiag edf_scheduling {
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node_width = 250;
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node_height = 120;
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default_fontsize = 16;
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Comp_1 -> Comp_2
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comment_1 -> Comp_2 [style=dashed]
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Comp_2 -> Comp_3
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comment_2 -> Comp_3 [style=dashed]
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Comp_3 -> Comp_4
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comment_3 -> Comp_4 [style=dashed]
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Comp_4 -> sink
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comment_4 -> sink [style=dashed]
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Comp_1 [label="DP component 1\n
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*processing period\n
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*compute requirement"]
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Comp_2 [label="DP component 2\n
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*processing period\n
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*compute requirement"]
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Comp_3 [label="DP component 3\n
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*processing period\n
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*compute requirement"]
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Comp_4 [label="DP component 4\n
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*processing period\n
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*compute requirement"]
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sink [label="real time sink", shape=endpoint, fontsize = 16]
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comment_1 [label="DP1 to deliver data let\n
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DP2 meet its objective"]
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comment_2 [label="DP2 to deliver data let\n
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DP3 meet its objective"]
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comment_3 [label="DP3 to deliver data let\n
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DP4 meet its objective"]
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comment_4 [label="DP4 to deliver data\n
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to real time-sink"]
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}

‎architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_DP_secondary_core_timeline.pu‎

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@startuml
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Title DP tasks scheduling on secondary DSP core
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legend
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Assumptions:
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1) 1ms scheduling
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2) No LL tasks assigned to example secondary DSP core
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3) DP Task B do not depend on Task A completion
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(otherwise, Task B would start on next timer interrupt after A
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completion)
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end legend
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scale 1 as 150 pixels
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concise "Task B" as Task_B
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concise "Task A" as Task_A
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concise "DP task processing" as DP_Processing
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robust "DSP" as DSP
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concise "Timer interrupt" as Interrupt
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@Task_A
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0 is Busy
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1.5 is {-}
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4 is Busy
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5.5 is {-}
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8 is Busy
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9.5 is {-}
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@0 <-> @4: Task A schedule period (4ms)
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@4 <-> @5.5: Task A execution time (1.5ms)
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DP_Processing@0 -[#Orange]> Task_A@0
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DP_Processing@1 -[#Orange]> Task_A@1
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[email protected] -[#Orange]> [email protected]
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@Task_B
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0 is Busy
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2 is {-}
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6 is Busy
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8 is {-}
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@0 <-> @6: Task B schedule period (6ms)
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@6 <-> @8: Task B execution time (2ms)
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[email protected] -[#Brown]> Task_B@0
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DP_Processing@2 -[#Brown]> [email protected]
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DP_Processing@3 -[#Brown]> [email protected]
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[email protected] -[#Brown]> Task_B@2
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DSP is Idle
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DP_Processing is {-}
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@0
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DP_Processing is "A"
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@0
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DSP is "Scheduling"
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DP_Processing is "A"
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@1
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "A"
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@1.5
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DP_Processing -> DSP
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DSP -> DP_Processing
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DP_Processing is "B"
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@2
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "B"
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@3
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "B"
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@3.5
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DP_Processing -> DSP
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DSP is Idle
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DP_Processing is {-}
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@4
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Interrupt -[#DarkViolet]> DSP
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DSP is "Scheduling"
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DSP -> DP_Processing
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DP_Processing is "A"
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@5
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "A"
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@5.5
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DP_Processing -> DSP
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DSP is Idle
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DP_Processing is {-}
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@6.001
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DSP is "Scheduling"
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DP_Processing is "B"
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@7.001
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "B"
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@8.001
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "A"
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@9.001
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Interrupt -[#DarkViolet]> DSP
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DSP -> DP_Processing
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DP_Processing is "A"
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@9.5
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DP_Processing -> DSP
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DSP is Idle
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DP_Processing is {-}
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_LL_DP_timeline.pu‎

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@startuml
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Title Task scheduling on DSP core
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legend
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Assumptions:
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1) 1ms scheduling
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2) 0.1ms takes LL task execution
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3) 0.5ms takes execution of all DP tasks
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end legend
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scale 1 as 200 pixels
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concise "DP Tasks Processing" as DP_Processing
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concise "LL Tasks Processing" as LL_Processing
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robust "DSP" as DSP
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concise "Timer Interrupt" as Interrupt
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DSP is Idle
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@DSP
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@1.2 <-> @2: Time available for\nDP tasks execution
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@2.2 <-> @2.7: Actual execution time\nof DP tasks
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@3 <-> @3.2: Actual execution time\nof LL tasks
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@Interrupt
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@0 <-> @1 : Schedule period
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@0
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Interrupt -> DSP
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DSP -> LL_Processing
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DSP is "Scheduling tasks"
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LL_Processing is Busy
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DP_Processing is {-}
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@+0.2
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DSP -> DP_Processing
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LL_Processing is {-}
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DP_Processing is Busy
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@+0.5
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DP_Processing -> DSP
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DP_Processing is {-}
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DSP is Idle
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@1
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Interrupt -> DSP
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DSP -> LL_Processing
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DSP is "Scheduling tasks"
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LL_Processing is Busy
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@+0.2
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DSP -> DP_Processing
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LL_Processing is {-}
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DP_Processing is Busy
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@+0.5
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DP_Processing -> DSP
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DP_Processing is {-}
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DSP is Idle
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@2
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Interrupt -> DSP
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DSP -> LL_Processing
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DSP is "Scheduling tasks"
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LL_Processing is Busy
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@+0.2
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DSP -> DP_Processing
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LL_Processing is {-}
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DP_Processing is Busy
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@+0.5
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DP_Processing -> DSP
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DP_Processing is {-}
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DSP is Idle
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@3
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Interrupt -> DSP
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DSP -> LL_Processing
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DSP is "Scheduling tasks"
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LL_Processing is Busy
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@+0.2
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DSP -> DP_Processing
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LL_Processing is {-}
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DP_Processing is Busy
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@+0.5
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DP_Processing -> DSP
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DP_Processing is {-}
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DSP is Idle
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@enduml

‎architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_multiple_cores_timeline.pu‎

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@startuml
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Title Tasks scheduling on multiple DSP cores
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legend
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Assumptions:
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1) 1ms system tick
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Notes:
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2) Core #0 has only LL tasks assigned schedule in 1ms period
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3) Core #1 has one DP task assigned that is dependent on Core #0 LL tasks data, scheduled in 1ms period
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(e.g. multicore pipeline with DP module scheduled on separate core)
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4) Core #2 has LL tasks scheduled in 1ms period and DP task scheduled in 2ms period
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(e.g. pipeline processing with LL and DP components components where DP component has 2ms scheduling period)
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end legend
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scale 1 as 300 pixels
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concise "DSP #2" as DSP_2
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concise "DSP #1" as DSP_1
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concise "DSP #0" as DSP_0
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concise "Timer interrupt" as Interrupt
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@DSP_0
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0 is "LL proc."
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0.5 is {-}
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1 is "LL proc."
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1.5 is {-}
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2 is "LL proc."
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2.5 is {-}
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3 is "LL proc."
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3.5 is {-}
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4 is "LL proc."
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4.5 is {-}
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@0 <-> @1: DSP#0 LL schedule period (1ms)
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@DSP_1
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0 is {-}
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1 is "DP proc."
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1.6 is {-}
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2 is "DP proc."
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2.6 is {-}
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3 is "DP proc."
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3.6 is {-}
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4 is "DP proc."
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4.6 is {-}
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5 is {-}
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@0 <-> @1: delay one period (waiting for first DSP#0 LL data)
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@1 <-> @2: DSP#1 DP schedule period (1ms)
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@DSP_2
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0 is "LL proc."
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0.3 is {-}
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1 is "LL proc."
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1.3 is {-}
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2 is "LL proc."
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2.3 is "DP proc."
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3 is "LL proc."
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3.3 is "DP proc."
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3.7 is {-}
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4 is "LL proc."
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4.3 is "DP proc."
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@0 <-> @1: DSP#2 LL schedule period (1ms)
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@2.3 <-> @4.3: DSP#2 DP schedule period (2ms)
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@0
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Interrupt -[#DarkViolet]> DSP_0
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Interrupt -[#DarkViolet]> DSP_1
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Interrupt -[#DarkViolet]> DSP_2
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@1
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Interrupt -[#DarkViolet]> DSP_0
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Interrupt -[#DarkViolet]> DSP_1
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Interrupt -[#DarkViolet]> DSP_2
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@2
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Interrupt -[#DarkViolet]> DSP_0
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Interrupt -[#DarkViolet]> DSP_1
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Interrupt -[#DarkViolet]> DSP_2
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@3
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Interrupt -[#DarkViolet]> DSP_0
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Interrupt -[#DarkViolet]> DSP_1
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Interrupt -[#DarkViolet]> DSP_2
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@4
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Interrupt -[#DarkViolet]> DSP_0
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Interrupt -[#DarkViolet]> DSP_1
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Interrupt -[#DarkViolet]> DSP_2
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@enduml

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