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Edit vendor-specific toc for better navigation
Signed-off-by: Deb <[email protected]>
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‎architectures/firmware/index.rst‎

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sof-xtos/index
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sof-zephyr/index
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Vendor Specific Architecture Information
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========================================
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Architecture details of any vendor specific code and flows. This is architecture
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specific to a single vendor that falls outside the scope of the high level
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generic SOF architecture.
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.. toctree::
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:maxdepth: 1
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intel/cavs/index
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vendor-specific/index

‎architectures/firmware/intel/cavs/index.rst‎

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‎architectures/firmware/vendor-specific/index.rst‎

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.. _vendor-specific:
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Vendor-Specific Architecture Information
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########################################
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Architecture details of any vendor specific code and flows. This is architecture
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specific to a single vendor that falls outside the scope of the high level
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generic SOF architecture.
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.. toctree::
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:maxdepth: 1
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vend-intel/index

‎architectures/firmware/vendor-specific/vend-intel/cavs-boot/apollolake/apl-boot-ldr.rst‎

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.. _apl-boot-ldr:
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Apollo Lake Boot Loader
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#######################
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* Additional HPSRAM memory initialization.
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* L2 cache disabled in ``boot_entry`` (enabled by default by APL ROM).
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Example list of sections in the APL boot_ldr::
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Idx Name Size VMA LMA File off Algn
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0 .boot_entry.text 00000036 b000a000 b000a000 000000d4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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1 .boot_entry.literal 0000000c b000a040 b000a040 0000010c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .text 000007d2 b000a0b0 b000a0b0 00000120 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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3 .rodata 00000008 b0002000 b0002000 000008f4 2**2
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CONTENTS, ALLOC, LOAD, DATA
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... more debug sections ...

‎architectures/firmware/vendor-specific/vend-intel/cavs-boot/apollolake/apl-boot-rom.rst‎

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.. _apl-boot-rom:
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Apollo Lake Boot ROM
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####################
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Progress of the boot process is reflected by the status information updated by
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the ROM in an SRAM area called *FW Registers*. It is available to the host
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driver through a memory window.
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ROM FW Registers
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****************
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This SRAM area updated by the ROM during the boot process is available via
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memory window #0, the limit is set to 4K.
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Offset 0x00
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FwStatus - Current ROM status
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Offset 0x04
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ErrorCode - Last ROM error code
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Offset 0x08
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FwPwrStatus - Current DSP clock status (ToBeVerified on APL/CNL)
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FwStatus
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========
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The FwStatus register contains current FW status, initialized to 0 on the DSP
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startup.
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The ErrorCode register is updated by ROM when *FwStatus* ``running`` bit is
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set to “halted on critical error”, initialized to 0 (`ADSP_SUCCESS`) on the
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DSP startup.
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Once Base FW is being executed, *ErrorCode* is updated every time some error is
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detected while calling internal API components. Some of the error codes might be
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helpful for driver writers hence documented in this specification.
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.. code-block:: c
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union fw_status_reg
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{
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int32_t full;
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struct Bits
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{
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uint32_t state : 24;
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uint32_t wait_state : 4;
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uint32_t module : 3;
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uint32_t running : 1;
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} bits;
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};
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running
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This field is used to report current FW running state.
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0 – running,
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1 – halted.
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When FW reports halted state, ErrorCode register contains error
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code.
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module
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This field is used to report FW module (that indicates boot phase
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component/module in this context, not a processing module) that is being
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executed.
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wait_state
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This field is updated to non-zero code of operation when ROM is waiting
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for completion of that operation.
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state
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This field is used to report phase of the FW module that is being executed.
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When FW switches to another module (reported by Module field) this value
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may get started again from 0, so it is Module context sensitive.
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.. uml:: images/apl-rom-flow.pu
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:caption: APL ROM Boot Sequence
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.. code-block:: c
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:caption: APL ROM Wait States
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// Waiting for IPC busy bit to be set
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#define WAIT_FOR_IPC_BUSY 0x1
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// Waiting for IPC done bit to be set
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#define WAIT_FOR_IPC_DONE 0x2
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// Waiting for L2$ invalidation to be ack'ed
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#define WAIT_FOR_CACHE_INVALIDATION 0x3
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// Waiting for DMA buffer to be filled
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#define WAIT_FOR_DMA_BUFFER_FULL 0x5
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.. code-block:: c
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:caption: APL ROM Status Codes
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#define FSR_ROM_INIT 0x0
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#define FSR_ROM_INIT_DONE 0x1
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#define FSR_ROM_CSE_MANIFEST_LOADED 0x2
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#define FSR_ROM_FW_MANIFEST_LOADED 0x3
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#define FSR_ROM_FW_FW_LOADED 0x4
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#define FSR_ROM_FW_ENTERED 0x5
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#define FSR_ROM_VERIFY_FEATURE_MASK 0x6
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#define FSR_ROM_GET_LOAD_OFFSET 0x7
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#define FSR_ROM_BASEFW_CSE_IMR_REQUEST 0x10
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#define FSR_ROM_BASEFW_CSE_IMR_GRANTED 0x11
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#define FSR_ROM_BASEFW_CSE_VALIDATE_IMAGE_REQUEST 0x12
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#define FSR_ROM_BASEFW_CSE_IMAGE_VALIDATED 0x13
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.. code-block:: c
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:caption: APL ROM Error Codes
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#define ADSP_UNHANDLED_INTERRUPT 0xBEE00000
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// Memory hole/ECC error
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// Status bits are provided:
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// [0] - L2 SRAM ECC error
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// [1] - L2 memory hole error
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#define ADSP_MEMORY_HOLE_ECC 0xECC00000
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#define ADSP_USER_EXCEPTION 0xBEEF0000
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#define ADSP_KERNEL_EXCEPTION 0xCAFE0000
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// Other critical error
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#define ADSP_FAILURE 6
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// FW image does not match the feature mask read from HW register.
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#define ADSP_INVALID_FEAT_MASK 20
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// Invalid parameter
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#define ADSP_INVALID_PARAM 21
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// CSE responded with error on an IPC request
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#define ADSP_CSE_ERROR 40
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// Invalid IPC response sent back by CSE.
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#define ADSP_CSE_WRONG_RESPONSE 41
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// Size of IMR assigned by CSE is too small to load FW Image.
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#define ADSP_IMR_TOO_SMALL 42
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// Base FW module not found in FW Image.
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#define ADSP_BASE_FW_NOT_FOUND 43
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// CSE responded with error on FW image validation request.
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#define ADSP_CSE_VALIDATION_FAILED 44
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// IPC communication failed with fatal error.
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#define ADSP_IPC_FATAL_ERROR 45
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// L2 cache command failed.
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#define ADSP_L2_CACHE_ERROR 46
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// Load offset set in FW Image Manifest is too small.
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#define ADSP_LOAD_OFFSET_TOO_SMALL 47
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ROM -> FW Transition
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====================
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Once APL ROM jumps to the entry point of the first module in the main binary,
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the memory and caches are in the following state:
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* L2$ is turned on, so the FW boot procedure may either execute via L2
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cacheable address space or directly via L2 uncacheable alias.
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* HPSRAM areas allocated by the ROM listed in the next table.
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APL ROM HPSRAM Allocation
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=========================
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+---------------------+------------+--------------+
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| Area | Base Addr | Size |
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+=====================+============+==============+
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| Code load buffer | 0xBE008000 | 0x8000 (32K) |
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+---------------------+------------+--------------+
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| BSS (inc. stack) | 0xBE010000 | 0x8000 (32K) |
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+---------------------+------------+--------------+
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| FW Registers | 0xBE01E000 | 0x800 (2K) |
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+---------------------+------------+--------------+

‎architectures/firmware/vendor-specific/vend-intel/cavs-boot/apollolake/images/apl-rom-flow.pu‎

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participant "State" as st
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participant "Error" as err
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participant "Host\nDriver" as host
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participant "APL\nROM" as rom
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participant "CSE" as cse
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host -> rom : <<IPC>> RomControl (purge=1, dma_id)
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== Initialization ==
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rom -> rom : Boot
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err <[#red]- rom : ADSP_UNHANDLED_INTERRUPT [anytime unhandled int reported]
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err <[#red]- rom : ADSP_MEMORY_HOLE_ECC [anytime memory hole int reported]
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err <[#red]- rom : ADSP_USER_EXCEPTION [anytime unhandled user mode exception happens]
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err <[#red]- rom : ADSP_KERNEL_EXCEPTION [anytime unhandled kernel mode exception happens]
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rom -> rom : L2Cache Initialization
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err <[#red]- rom : ADSP_L2_CACHE_ERROR [Failed to init L2$]
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rom -> rom : Requesting IMR
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st <[#green]- rom : FSR_ROM_BASEFW_CSE_IMR_REQUEST
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rom -> cse : <<IPC>> IPC_ADSP2CSE_REQUEST_IMR
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rom <- cse : <<IPC>> IPC_CSE2ADSP_REQUEST_IMR_RESPONSE
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st <[#green]- rom : FSR_ROM_BASEFW_CSE_IMR_GRANTED
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rom -> rom : Initializing Code Load DMA
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err <[#red]- rom : ADSP_INVALID_PARAM [dma_id out of range]
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st <[#green]- rom : FSR_ROM_INIT_DONE
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== Loading Image ==
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rom -> rom : Loading Firmware
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' First fw image block is loaded and feature mask is verified
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st <[#green]- rom : FSR_ROM_VERIFY_FEATURE_MASK
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err <[#red]- rom : ADSP_INVALID_FEAT_MASK [mft mask does not match SKUID]
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' Load offset is verified
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st <[#green]- rom : FSR_ROM_GET_LOAD_OFFSET
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err <[#red]- rom : ADSP_LOAD_OFFSET_TOO_SMALL [load offset less then Rsvd space]
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err <[#red]- rom : ADSP_IMR_TOO_SMALL [load offset greater than assigned IMR size]
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' CSE Manifest if loaded
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rom -> rom : Loading CSE Manifest
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err <[#red]- rom : ADSP_IMR_TOO_SMALL [CSE manifest > IMR size]
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st <[#green]- rom : FSR_ROM_CSE_MANIFEST_LOADED
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' FW Manifest is loaded
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rom -> rom : Loading ADSP FW Manifest
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err <[#red]- rom : ADSP_IMR_TOO_SMALL [ADSP FW manifest > IMR size]
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st <[#green]- rom : FSR_ROM_FW_MANIFEST_LOADED
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err <[#red]- rom : ADSP_BASE_FW_NOT_FOUND [module entry not found in manifest]
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' Loading rest of FW
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rom -> rom : Loading FW
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st <[#green]- rom : FSR_ROM_FW_FW_LOADED
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== Authenticating Image ==
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st <[#green]- rom : FSR_ROM_BASEFW_CSE_VALIDATE_IMAGE_REQUEST
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rom -> cse : <<IPC>> IPC_CSE2ADSP_START_FW_AUTH
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rom <- cse : <<IPC>> IPC_CSE2ADSP_START_FW_AUTH_RESPONSE
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err <[#red]- rom : ADSP_CSE_VALIDATION_FAILED [invalid image signature]
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st <[#green]- rom : FSR_ROM_BASEFW_CSE_IMAGE_VALIDATED
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== Booting FW ==
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st <[#green]- rom : FSR_ROM_FW_ENTERED

‎architectures/firmware/vendor-specific/vend-intel/cavs-boot/apollolake/index.rst‎

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.. _cavs-boot-apl:
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Apollo Lake Boot Process
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########################
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.. toctree::
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:maxdepth: 1
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apl-boot-rom
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apl-boot-ldr

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