Skip to content

Commit 975cf45

Browse files
committed
add data type spec per register: either 'int' or 'float'
1 parent 9a9d47b commit 975cf45

File tree

2 files changed

+14
-8
lines changed

2 files changed

+14
-8
lines changed

debian/changelog

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ te-modbus-plugin (0.3.0) unstable; urgency=medium
33
* Add register and coil mapping for Event
44
* Add register mapping for Alarms
55
* Raise alarm only on change of value
6+
* Add data type hint for float/int parsing if a field has a length > 16 bit
67

78
-- Mario Heidenreich <[email protected]> Tue, 08 Nov 2022 14:22:54 +0100
89

modbus_reader/mapper.py

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@
99
decoder_func = {
1010
'int16': lambda d: d.decode_16bit_int(),
1111
'uint16': lambda d: d.decode_16bit_uint(),
12+
'int32': lambda d: d.decode_32bit_int(),
13+
'uint32': lambda d: d.decode_32bit_uint(),
14+
'int64': lambda d: d.decode_64bit_int(),
15+
'uint64': lambda d: d.decode_64bit_uint(),
1216
'float32': lambda d: d.decode_32bit_float(),
1317
'float64': lambda d: d.decode_64bit_float()
1418
}
@@ -46,9 +50,9 @@ def mapregister(self, registerresponse: ReadRegistersResponseBase, registerdef):
4650
is_litte_word_endian = self.device.get('littlewordendian') or False
4751
readregister = registerresponse.registers
4852
registertype = 'ir' if (registerdef.get('input') or False) else 'hr'
49-
registerkey = f'${registerdef["number"]}:${registerdef["startbit"]}'
53+
registerkey = f'{registerdef["number"]}:{registerdef["startbit"]}'
5054
if fieldlength > 16 and startbit > 0:
51-
raise Exception('float values must align to the zero bit of the start register')
55+
raise Exception('values spanning registers must align to the zero bit of the start register')
5256
if fieldlength > 16:
5357
value = self.parse_register_value(readregister, self.gettargettype(registerdef),
5458
little_endian=is_little_endian, word_endian=is_litte_word_endian)
@@ -98,7 +102,7 @@ def checkalarm(self, value, alarmmapping, registertype, registerkey):
98102
messages = []
99103
old_data = self.data.get(registertype).get(registerkey)
100104
# raise alarm if bit is 1
101-
if old_data is not None and old_data == 0 and value > 0:
105+
if (old_data is None or old_data == 0) and value > 0:
102106
severity = alarmmapping['severity'].lower()
103107
alarmtype = alarmmapping['type']
104108
text = alarmmapping['text']
@@ -126,13 +130,14 @@ def checkevent(self, value, eventmapping, registertype, registerkey):
126130

127131
@staticmethod
128132
def gettargettype(registerdef):
133+
dtype = 'int' if registerdef.get('datatype') == 'int' else 'float'
134+
signed = 'u' if dtype == 'int' and registerdef.get('signed') == False else ''
135+
length = 16
129136
if registerdef['nobits'] > 32:
130-
return 'float64'
137+
length = 64
131138
elif registerdef['nobits'] > 16:
132-
return 'float32'
133-
elif registerdef.get('signed') == False:
134-
return 'uint16'
135-
return 'int16'
139+
length = 32
140+
return f'{signed}{dtype}{length}'
136141

137142
@staticmethod
138143
def parse_register_value(read_registers, target_type, little_endian, word_endian):

0 commit comments

Comments
 (0)