Modeling Strategy for Solder-Mask Coated Microstrip Traces?

[biergaizi]

One important potential application of openEMS is the simulation of impedance discontinuities of microstrip transmission lines on circuit boards, which are often manufactured with a thin layer of solder mask. This has the effect of creating an extra layer of dielectric above the traces. Experimentally, it can be shown that it causes a reduction of characteristic impedance around 2-3 ohms in a 50-ohm transmission line. Modeling this effect is highly desirable, since it affects the results of many kinds of optimizations.

Many 2D and 2.5D field solvers (especially those specifically designed for transmission lines) are able to model this effect. However, it creates difficulties in a 3D FDTD simulation. I had a discussion with Matt Huszagh at pyEMS's repository, and our conclusions are:

1. This solder mask layer has a thickness of around 0.5 mils to 1 mils, this is an extremely fine structure compared to the enormous millimeter-size of the circuit board. It means an extremely fine mesh must be created around the microstrip traces, which seems impractical for FDTD.

2. Microstrips are modeled mainly via AddConductingSheet or AddMetal. AddConductingSheet can only add a 2D metal layer, and Matt told me it that its math behind it simply "doesn't really work with physical structure of the solder mask over trace." Is it true? Meanwhile AddConductingSheet is 3D, but it doesn't model any loss. The proper solution that models both would be the Drude-Lorentz model, but it will likely make the simulation even slower.

What would be a good modeling strategy for this problem?

1. Just give up. One can argue that FDTD is simply not suitable for modeling this problem. Even on a bare board with a single dielectric layer, there will be an error of a few ohms if the meshing is deviated from the 1/3-2/3 rule, so modeling the effect of the solder mask is simply hopeless. Not to mention that the material property of solder mask itself is already poorly controlled. On precise RF boards, it's common to remove solder mask around sensitive areas, so modeling it is pointless. If one wants to model it anyway, a 2D/2.5D solver would be a proper tool.

   But this answer is not entirely satisfactory.

2. Adjusting the circuit board substrate to compensate. This is the easiest method, however, it creates an opposite problem - it will underestimate the characteristic impedance of uncoated traces. This can be important when modeling the transition from coated traces to uncoated traces. For example, on a circuit board, planar transmission line structures like couplers and filters are often uncoated, mounting pads for connectors and SMD components are also uncoated, meanwhile other traces are coated. Finding the optimal geometry to minimize the impedance discontinuity is a common optimization problem, and I'd really like to demonstrate that in openEMS, so both kinds of traces must be modeled.

What is your advise on this modeling problem?

[biergaizi]

I'm started to think that using a "virtual" dielectric layer may work as a workaround to simulate the effect of solder mask. That is, it doesn't have to physically model the actual solder mask, we can just tweak its parameter (i.e. dielectric constant) until the trace impedance matches the experimental value (or 2D solver value). Thus, we can bypass the problem of modeling the extremely thin layer of coating, which is problematic for FDTD.

[biergaizi]

Accurately impedance determination of transmission lines is the most basic problem in RF engineering, so free and open source solvers are of crucial importance for free hardware development. From this perspective, a comparison of different methods and solvers is a question of fundamental importance. Some free solvers include ATLC, TNT-MMTL, MEEP, and openEMS. ATLC and TNT-MMTL are quasi-static frequency-domain (MoM & BEM) solvers, openEMS is a time-domain solver, and it would be a useful cross-check if different solvers give similar results for multi-layer PCBs - if only as an academic exercise.

Now I'm start to wonder if brute-force calculation in FDTD is more practical than I thought, at least for these demo/research/benchmark problems. Suppose that we're simulating a 1.6 mm PCB with a 1.6 mil copper layer (1 oz) and a 1.2 mil solder mask. For other parts of the board, a 0.1 mm grid is likely adequate, so a 16x16x16 grid should cover the board, we use 32x32x64 to avoid PML and create air on top of the board. Near the surface of the board, we need a Z-axis resolution of at least 0.1 mil, or 0.0025 mm. Simple math says we need 640 Yee cells to cover the PCB. But if we use a non-uniform mesh with a 10% increment, we just need 39 cells to transition from the fine 0.0025 mm mesh back into the regular grid size 0.1 mm mesh since 0.0025 x 1.1 ^ 39 = 0.103. So the grid size would be 32x32x103. If the simulation is running at 500 MC/s, one CPU second is 4740 timesteps (should be achievable on a single desktop, and may even be faster if my optimized code works as planned). A 0.0025 mm cubic cell translates to a 4.8 ps timestep in the CFL stability criteria (for EC-FDTD, it's actually better as follows Rennigs' criteria with slightly relaxed requirements). If we use a 100 nanosecond excitation, it takes 20833 timesteps and 4.39 s CPU time. Then we wait 100x more timesteps, it's just 439 seconds.

Thus, brute-force impedance calculation seems to be completely within reach for these demo problems (but perhaps there can be some numerical stability problems that would require one to tweak the meshing).

[biergaizi]

For the actual PCB, I would not go for brute force, and use an equivalent material instead.

Sure, it's not practical for realistic tasks, but my new plan is whether it can be used for "one-off study" type problems to verify the correctness of other solvers or models. For these validation case studies, one can devote "unlimited" amount of computational resource that wouldn't otherwise make sense for real problems.

The equivalent material properties can be "calibrated" against a simple through line model where the actual stackup including solder mask is meshed with rather higher mesh density.

This is a great idea. I was thinking about using a MoM solver like TNT-MMTL to calibrate the artificial material properties for openEMS for simplified models, but I completely missed the idea of using openEMS to calibrate itself.

The solder stop will then be conformal ("sugar coating") in these regions, not even planar.

Yes, the transition region between the solder mask on the subtrate and the solder mask on the metal trace would be the most problematic area. I specifically mentioned this problem in my discussion with Matt Huszagh at pyEMS's repository. Even for 2D it's a headache. In TNT-MMTL, my workaround is to cheat and place a small rectangular block near this region, which seems to produce nearly-correct numbers.

This is somewhat specific to the line/gap dimensions

My results from 2D solvers indicate that the impedance of coplanar waveguide is strongly affected by the solder mask fill between a differential pair (likely because the almost all field exists above the surface). Common formulas and calculators can disagree with field solvers by 10-20 Ω (30%) for simple 50 Ω test problems. I imagine that it would be a useful demo problem to do in FDTD as well to show its capabilities.

[VolkerMuehlhaus]

@biergaizi Can you suggest cross section dimensions and materials for a testcase? I would like to try a few things, and for comparisons we should work on the exact same testcase.

[biergaizi]

My eventual plan is to do a big cross-comparison project to test different transmission line structures and sizes (~10 combinations) with 3 to 5 different tools. But for starter, here's a benchmark problem from Si9000's "Surface Coplanar Strip 1B" and "Coated Coplanar Strip 1B", with these parameters.

• 0.1 mm coplanar waveguide, 0.1 mm gap to ground

  

  1. Substrate 1 Height (H1): 0.21031 mm (8.28 mils)
  2. Substrate 1 Dielectric (Er1): 4.4
  3. Lower Trace Width (W1): 0.1 mm (3.9370 mils)
  4. Upper Trace Width (W2): 0.0746 mm (2.9370 mils)
  5. Lower/Upper Ground Strip Widthi (G1/G2): 10 mm
  6. Ground Strip Separation (D1): 0.1 mm
  7. Trace Thickness (T1): 0.04064 mm (1.6 mils)
  8. Coating Above Substrate (C1): 0.01524 mm (0.6 mils)
  9. Coating Above Trace (C2): 0.03048 mm (1.2 mils)
  10. Coating Between Traces (C3): 0.01524 mm (0.6 mils)
  11. Coating Dielectric (CEr): 3.8

Si9000 gives 68.87 Ω for the uncoated case and 61.78 Ω for the coated case. Meanwhile, TNT-MMTL gives 66.78 Ω and 58.52 Ω. But TransCalc (also integrated in KiCad and Qucs) gives 77.02 Ω (uncoated). This is a clear example that shows the limitation of calculators in comparison to field solvers.

I did this calculation to answer someone's practical question regarding to the reliability of different impedance calculations. You don't have to copy the numbers exactly, you can select some nice round numbers.

[VolkerMuehlhaus]

Hello @biergaizi ,

thanks for posting your testcase! This is very sensitive to solder stop, because the line itself is narrow (small capacitance from broad side) and the gap is small (large capacitance from side walls). Very useful because it gives an estimate what can be expected worst case!

One question: I wonder if all calculations use a bottom ground, so that we can compare them directly? The left picture shows a coplanar line with bottom ground, but that bottom ground is missing in the right picture with solder stop. My results below show that missing ground plane causes + 6 Ohm difference in line impedance for this geometry.

I have built a few FDTD models with/without passivation, with/without bottom ground and with/without the trapezoidal shape. To make sure I'm not doing any modelling mistakes at this early stage, I used Empire XPU which I am very familiar with from my day job. And for comparison, I also looked at results from an equation based tool (ADS Linecalc) and from a 2D cross section solver (ADS controlled impedance line designer).

Overview/Structure

I decided to start this comparison with an FDTD result considered very accurate, which includes all effects from your Si9000 model, including trapezoidal conductor shape and bottom ground, and test line impedance with/without conformal solder stop coating.

For this testcase I created 10mm of line length, with the end of the line running into a PML8 wall. Conductor and dielectrics are simulated without losses.

The mesh is an ultra-fine resolution mesh that allows to resolve the trapezoidal shapes and conformal solder stop coating. Solder stop is 0.6mils and in my model that ends at some distance from the gap, because solder stop on top of the far away grounds does not change fields anyway.

Due to the PML8 at the end of the line, there is no reflection and input impedance into the port is equal to the line impedance, so this is easy to evaluate. Results show less than 1 Ohm variation in the range 0-20 GHz, so only one average value is listed below.

Baseline: High resolution FDTD model with/without solder stop

Here is a view of the geometry and mesh lines for this baseline model:

For comparison of line impedance in this baseline configuration with/without solder stop, I decided to use the exact same mesh, so that we don't see any artefacts caused by different mesh density.

These are my baseline results for the exact testcase:
Line impedance with solder stop: 64.3 Ohm
Line impedance without solder stop: 69.4 ohm

Above I had asked about the bottom ground in some of the calculators, so for reference here is the high resolution FDTD result if we remove that bottom ground, with all other details unchanged:

Line impedance with solder stop, no bottom ground: 70.5 Ohm

It must be noted that bottom ground has limited effect here because the signal line is rather narrow compared to the gap width, and the substrate thickness is much larger than the signal line width. The side grounds are more significant for this particular testcase.

Simplification: FDTD model with rectangular conductors

Many calculators and also some EM cross section solvers cannot handle trapezoidal shape, so I modified the FDTD model to use simple rectangular cross section for signal line and side grounds, i.e. trace 0.1mm width and 0.1mm gap. Mesh density is unchanged, so that we don't see any artefacts caused by different mesh density.

Line impedance, rectangular shape with solder stop: 60.7 Ohm
Line impedance, rectangular shape without solder stop: 66.3 ohm

As expected, the square shape has higher capacitance to the side grounds, so that line impedance drops.

To be ready for a comparison with equation-based calculators that simulate pure CPW without bottom ground, I also simulated that case: rectangular conductor model without solder stop and without ground plane: 73.0 Ohm

Comparison to equation-based calculator

We can now compare results to an equation based calculator. I used the good old ADS linecalc here, which means several limitations to modelling: no solder stop, rectangular cross section. Bottom ground is included here in this CPWG model.

Line impedance from Linecalc CPW model, with limitations listed above: 66.8 Ohm
This is in excellent agreement to FDTD results for the exact same geometry.

Comparison to 2D cross section solver

I also tested the "Controlled Impedance Line Designer" tool in ADS, which is based on a 2D cross section solver. There are some limitations how lines can intersect dielectrics, so I could not model the conformal solder stop.

Model with rectangular conductors, bottom ground included, no solder stop: 66.2 Ohm
This is in excellent agreement to FDTD results and Linecalc results for the exact same geometry.

Possible next steps

That's what I have so far. One possible next step is now to calculate an effective "fake" dielectric that we can place onto a zero thickness conductor, to provide the extra capacitance C' that we would get from including thickness and solder stop. That equivalent "fake" material could then be applied to more complex, real layouts wihout the need for excessive mesh density.

Best regards
Volker

[biergaizi]

One question: I wonder if all calculations use a bottom ground, so that we can compare them directly?

Yes, I gave both calculations with bottom grounds. The right picture was incorrect.