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arsenmPravin Jagtap
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Pravin Jagtap
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AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (llvm#117379)
Co-authored-by: Pravin Jagtap <[email protected]>
1 parent e97fb22 commit 6f8e7c1

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‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -997,6 +997,12 @@ def FeatureVmemWriteVgprInOrder : SubtargetFeature<"vmem-write-vgpr-in-order",
997997
"VMEM instructions of the same type write VGPR results in order"
998998
>;
999999

1000+
def FeatureBitOp3Insts : SubtargetFeature<"bitop3-insts",
1001+
"HasBitOp3Insts",
1002+
"true",
1003+
"Has v_bitop3_b32/v_bitop3_b16 instructions"
1004+
>;
1005+
10001006
def FeaturePrngInst : SubtargetFeature<"prng-inst",
10011007
"HasPrngInst",
10021008
"true",
@@ -1524,7 +1530,8 @@ def FeatureISAVersion9_5_Common : FeatureSet<
15241530
FeatureCvtFP8VOP1Bug,
15251531
FeatureGFX950Insts,
15261532
FeaturePrngInst,
1527-
FeatureBF16ConversionInsts
1533+
FeatureBF16ConversionInsts,
1534+
FeatureBitOp3Insts
15281535
])>;
15291536

15301537
def FeatureISAVersion9_4_0 : FeatureSet<
@@ -2392,6 +2399,9 @@ def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">,
23922399
def HasPseudoScalarTrans : Predicate<"Subtarget->hasPseudoScalarTrans()">,
23932400
AssemblerPredicate<(all_of FeaturePseudoScalarTrans)>;
23942401

2402+
def HasBitOp3Insts : Predicate<"Subtarget->hasBitOp3Insts()">,
2403+
AssemblerPredicate<(all_of FeatureBitOp3Insts)>;
2404+
23952405
def HasPrngInst : Predicate<"Subtarget->hasPrngInst()">,
23962406
AssemblerPredicate<(all_of FeaturePrngInst)>;
23972407

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
171171
ImmTyWaitVAVDst,
172172
ImmTyWaitVMVSrc,
173173
ImmTyByteSel,
174+
ImmTyBitOp3,
174175
};
175176

176177
// Immediate operand kind.
@@ -410,6 +411,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
410411
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
411412
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
412413
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
414+
bool isBitOp3() const { return isImmTy(ImmTyBitOp3) && isUInt<8>(getImm()); }
413415

414416
bool isRegOrImm() const {
415417
return isReg() || isImm();
@@ -1138,6 +1140,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
11381140
case ImmTyWaitVAVDst: OS << "WaitVAVDst"; break;
11391141
case ImmTyWaitVMVSrc: OS << "WaitVMVSrc"; break;
11401142
case ImmTyByteSel: OS << "ByteSel" ; break;
1143+
case ImmTyBitOp3: OS << "BitOp3"; break;
11411144
}
11421145
// clang-format on
11431146
}
@@ -1913,6 +1916,9 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
19131916
ParseStatus parseEndpgm(OperandVector &Operands);
19141917

19151918
ParseStatus parseVOPD(OperandVector &Operands);
1919+
1920+
ParseStatus parseBitOp3(OperandVector &Operands);
1921+
AMDGPUOperand::Ptr defaultBitOp3() const;
19161922
};
19171923

19181924
} // end anonymous namespace
@@ -8841,6 +8847,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
88418847
Inst.addOperand(Inst.getOperand(0));
88428848
}
88438849

8850+
int BitOp3Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::bitop3);
8851+
if (BitOp3Idx != -1) {
8852+
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyBitOp3);
8853+
}
8854+
88448855
// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
88458856
// instruction, and then figure out where to actually put the modifiers
88468857

@@ -9748,6 +9759,20 @@ ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {
97489759

97499760
bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
97509761

9762+
//===----------------------------------------------------------------------===//
9763+
// BITOP3
9764+
//===----------------------------------------------------------------------===//
9765+
9766+
ParseStatus AMDGPUAsmParser::parseBitOp3(OperandVector &Operands) {
9767+
ParseStatus Res =
9768+
parseIntWithPrefix("bitop3", Operands, AMDGPUOperand::ImmTyBitOp3);
9769+
return Res;
9770+
}
9771+
9772+
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBitOp3() const {
9773+
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyBitOp3);
9774+
}
9775+
97519776
//===----------------------------------------------------------------------===//
97529777
// Split Barrier
97539778
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
220220
bool HasSALUFloatInsts = false;
221221
bool HasPseudoScalarTrans = false;
222222
bool HasRestrictedSOffset = false;
223+
bool HasBitOp3Insts = false;
223224
bool HasPrngInst = false;
224225
bool HasPermlane16Swap = false;
225226
bool HasPermlane32Swap = false;
@@ -1321,6 +1322,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
13211322
/// \returns true if the target has instructions with xf32 format support.
13221323
bool hasXF32Insts() const { return HasXF32Insts; }
13231324

1325+
bool hasBitOp3Insts() const { return HasBitOp3Insts; }
1326+
13241327
bool hasPermlane16Swap() const { return HasPermlane16Swap; }
13251328
bool hasPermlane32Swap() const { return HasPermlane32Swap; }
13261329

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1714,4 +1714,18 @@ void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
17141714
O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
17151715
}
17161716

1717+
void AMDGPUInstPrinter::printBitOp3(const MCInst *MI, unsigned OpNo,
1718+
const MCSubtargetInfo &STI,
1719+
raw_ostream &O) {
1720+
uint8_t Imm = MI->getOperand(OpNo).getImm();
1721+
if (!Imm)
1722+
return;
1723+
1724+
O << " bitop3:";
1725+
if (Imm <= 10)
1726+
O << formatDec(Imm);
1727+
else
1728+
O << formatHex(static_cast<uint64_t>(Imm));
1729+
}
1730+
17171731
#include "AMDGPUGenAsmWriter.inc"

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
163163
const MCSubtargetInfo &STI, raw_ostream &O,
164164
StringRef Prefix, bool PrintInHex, bool AlwaysPrint);
165165

166+
void printBitOp3(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
167+
raw_ostream &O);
168+
166169
public:
167170
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
168171
StringRef Asm, StringRef Default = "");

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1271,6 +1271,9 @@ def ByteSel : NamedIntOperand<"byte_sel"> {
12711271
let Validator = "isUInt<2>";
12721272
}
12731273

1274+
def BitOp3 : CustomOperand<i8, 1, "BitOp3">;
1275+
def bitop3_0 : DefaultOperand<BitOp3, 0>;
1276+
12741277
class KImmFPOperand<ValueType vt> : ImmOperand<vt> {
12751278
let OperandNamespace = "AMDGPU";
12761279
let OperandType = "OPERAND_KIMM"#vt.Size;

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -856,6 +856,24 @@ class PermlaneVarPat<SDPatternOperator permlane,
856856
VGPR_32:$src1, VGPR_32:$vdst_in)
857857
>;
858858

859+
class VOP3_BITOP3_Profile<VOPProfile pfl, VOP3Features f> : VOP3_Profile<pfl, f> {
860+
let HasClamp = 0;
861+
let HasOMod = 0;
862+
let HasModifiers = 0;
863+
864+
let Ins64 = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
865+
0 /* HasIntClamp */, HasModifiers, HasSrc2Mods,
866+
HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret,
867+
(ins bitop3_0:$bitop3));
868+
869+
let InsVOP3OpSel = !con(getInsVOP3Base<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, 0, 1, 1, 0,
870+
Src0Mod, Src1Mod, Src2Mod, 0>.ret,
871+
(ins bitop3_0:$bitop3, op_sel0:$op_sel));
872+
873+
let Asm64 = "$vdst, $src0, $src1, $src2$bitop3";
874+
let AsmVOP3OpSel = !subst("$op_sel", "$bitop3$op_sel", getAsmVOP3OpSel<3, 0, 0, 0, 0, 0>.ret);
875+
}
876+
859877
let SubtargetPredicate = isGFX10Plus in {
860878
let isCommutable = 1, isReMaterializable = 1 in {
861879
defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
@@ -908,6 +926,16 @@ let SubtargetPredicate = isGFX12Plus in {
908926

909927
} // End SubtargetPredicate = isGFX12Plus
910928

929+
let SubtargetPredicate = HasBitOp3Insts in {
930+
let isReMaterializable = 1 in {
931+
defm V_BITOP3_B16 : VOP3Inst <"v_bitop3_b16",
932+
VOP3_BITOP3_Profile<VOPProfile_True16<VOPProfile <[i16, i16, i16, i16, i8]>>,
933+
VOP3_OPSEL>>;
934+
defm V_BITOP3_B32 : VOP3Inst <"v_bitop3_b32",
935+
VOP3_BITOP3_Profile<VOPProfile <[i32, i32, i32, i32, i8]>, VOP3_REGULAR>>;
936+
}
937+
} // End SubtargetPredicate = HasBitOp3Insts
938+
911939
class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
912940
(AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
913941
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)),
@@ -1606,6 +1634,23 @@ multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
16061634
}
16071635
}
16081636

1637+
multiclass VOP3_Real_BITOP3_gfx9<bits<10> op, string AsmName, bit isSingle = 0> {
1638+
defvar ps = !cast<VOP_Pseudo>(NAME#"_e64");
1639+
let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
1640+
def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1641+
VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> {
1642+
let AsmString = AsmName # ps.AsmOperands;
1643+
bits<8> bitop3;
1644+
let Inst{60-59} = bitop3{7-6};
1645+
let Inst{10-8} = bitop3{5-3};
1646+
let Inst{63-61} = bitop3{2-0};
1647+
let Inst{11} = !if(ps.Pfl.HasOpSel, src0_modifiers{2}, 0);
1648+
let Inst{12} = !if(ps.Pfl.HasOpSel, src1_modifiers{2}, 0);
1649+
let Inst{13} = !if(ps.Pfl.HasOpSel, src2_modifiers{2}, 0);
1650+
let Inst{14} = !if(ps.Pfl.HasOpSel, src0_modifiers{3}, 0);
1651+
}
1652+
}
1653+
}
16091654
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
16101655

16111656
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
@@ -1748,3 +1793,6 @@ defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>;
17481793
defm V_CVT_PK_BF16_F32: VOP3OpSel_Real_gfx9 <0x268>;
17491794
defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>;
17501795
defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;
1796+
1797+
defm V_BITOP3_B16 : VOP3_Real_BITOP3_gfx9<0x233, "v_bitop3_b16">;
1798+
defm V_BITOP3_B32 : VOP3_Real_BITOP3_gfx9<0x234, "v_bitop3_b32">;

‎llvm/test/MC/AMDGPU/gfx950_asm_vop3.s‎

Lines changed: 58 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,76 @@
1-
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx950 -show-encoding %s | FileCheck --check-prefix=GFX950 %s
2-
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck -check-prefix=GFX940-ERR --strict-whitespace %s
1+
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX906-ERR %s
2+
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX940-ERR %s
3+
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx950 -show-encoding < %s | FileCheck --check-prefix=GFX950 %s
4+
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
35

46
v_cvt_pk_bf16_f32 v5, v1, v2
7+
// GFX906-ERR: error: instruction not supported on this GPU
8+
// GFX940-ERR: error: instruction not supported on this GPU
59
// GFX950: v_cvt_pk_bf16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x68,0xd2,0x01,0x05,0x02,0x00]
6-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
10+
// GFX12-ERR: error: instruction not supported on this GPU
711

812
v_cvt_pk_bf16_f32 v5, v255, v255
13+
// GFX906-ERR: error: instruction not supported on this GPU
14+
// GFX940-ERR: error: instruction not supported on this GPU
915
// GFX950: v_cvt_pk_bf16_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x68,0xd2,0xff,0xff,0x03,0x00]
10-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
16+
// GFX12-ERR: error: instruction not supported on this GPU
1117

1218
v_cvt_pk_bf16_f32 v5, v1, s2
19+
// GFX906-ERR: error: instruction not supported on this GPU
20+
// GFX940-ERR: error: instruction not supported on this GPU
1321
// GFX950: v_cvt_pk_bf16_f32 v5, v1, s2 ; encoding: [0x05,0x00,0x68,0xd2,0x01,0x05,0x00,0x00]
14-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
22+
// GFX12-ERR: error: instruction not supported on this GPU
1523

1624
v_cvt_pk_bf16_f32 v5, m0, 0.5
25+
// GFX906-ERR: error: instruction not supported on this GPU
26+
// GFX940-ERR: error: instruction not supported on this GPU
1727
// GFX950: v_cvt_pk_bf16_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x68,0xd2,0x7c,0xe0,0x01,0x00]
18-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
28+
// GFX12-ERR: error: instruction not supported on this GPU
1929

2030
v_cvt_pk_bf16_f32 v5, -1, exec_hi
31+
// GFX906-ERR: error: instruction not supported on this GPU
32+
// GFX940-ERR: error: instruction not supported on this GPU
2133
// GFX950: v_cvt_pk_bf16_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x68,0xd2,0xc1,0xfe,0x00,0x00]
22-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
34+
// GFX12-ERR: error: instruction not supported on this GPU
2335

2436
v_cvt_pk_bf16_f32 v5, 0.5, m0 mul:2
37+
// GFX906-ERR: error: instruction not supported on this GPU
38+
// GFX940-ERR: error: instruction not supported on this GPU
2539
// GFX950: v_cvt_pk_bf16_f32 v5, 0.5, m0 mul:2 ; encoding: [0x05,0x00,0x68,0xd2,0xf0,0xf8,0x00,0x08]
26-
// GFX940-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
40+
// GFX12-ERR: error: instruction not supported on this GPU
41+
42+
v_bitop3_b32 v5, v1, v2, s3
43+
// GFX906-ERR: error: instruction not supported on this GPU
44+
// GFX940-ERR: error: instruction not supported on this GPU
45+
// GFX950: v_bitop3_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x34,0xd2,0x01,0x05,0x0e,0x00]
46+
// GFX12-ERR: error: instruction not supported on this GPU
47+
48+
v_bitop3_b32 v5, v1, v2, s3 bitop3:161
49+
// GFX906-ERR: error: instruction not supported on this GPU
50+
// GFX940-ERR: error: instruction not supported on this GPU
51+
// GFX950: v_bitop3_b32 v5, v1, v2, s3 bitop3:0xa1 ; encoding: [0x05,0x04,0x34,0xd2,0x01,0x05,0x0e,0x30]
52+
// GFX12-ERR: error: instruction not supported on this GPU
53+
54+
v_bitop3_b32 v5, m0, 0.5, m0 bitop3:5
55+
// GFX906-ERR: error: instruction not supported on this GPU
56+
// GFX940-ERR: error: instruction not supported on this GPU
57+
// GFX950: v_bitop3_b32 v5, m0, 0.5, m0 bitop3:5 ; encoding: [0x05,0x00,0x34,0xd2,0x7c,0xe0,0xf1,0xa1]
58+
// GFX12-ERR: error: instruction not supported on this GPU
59+
60+
v_bitop3_b32 v5, 0.5, m0, 0.5 bitop3:101
61+
// GFX906-ERR: error: instruction not supported on this GPU
62+
// GFX940-ERR: error: instruction not supported on this GPU
63+
// GFX950: v_bitop3_b32 v5, 0.5, m0, 0.5 bitop3:0x65 ; encoding: [0x05,0x04,0x34,0xd2,0xf0,0xf8,0xc0,0xab]
64+
// GFX12-ERR: error: instruction not supported on this GPU
65+
66+
v_bitop3_b16 v5, v1, v2, s3
67+
// GFX906-ERR: error: instruction not supported on this GPU
68+
// GFX940-ERR: error: instruction not supported on this GPU
69+
// GFX950: v_bitop3_b16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x33,0xd2,0x01,0x05,0x0e,0x00]
70+
// GFX12-ERR: error: instruction not supported on this GPU
71+
72+
v_bitop3_b16 v5, v1, v2, s3 bitop3:161
73+
// GFX906-ERR: error: instruction not supported on this GPU
74+
// GFX940-ERR: error: instruction not supported on this GPU
75+
// GFX950: v_bitop3_b16 v5, v1, v2, s3 bitop3:0xa1 ; encoding: [0x05,0x04,0x33,0xd2,0x01,0x05,0x0e,0x30]
76+
// GFX12-ERR: error: instruction not supported on this GPU

‎llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,3 +17,21 @@
1717

1818
# GFX950: v_cvt_pk_bf16_f32 v5, 0.5, m0 mul:2 ; encoding: [0x05,0x00,0x68,0xd2,0xf0,0xf8,0x00,0x08]
1919
0x05,0x00,0x68,0xd2,0xf0,0xf8,0x00,0x08
20+
21+
# GFX950: v_bitop3_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x34,0xd2,0x01,0x05,0x0e,0x00]
22+
0x05,0x00,0x34,0xd2,0x01,0x05,0x0e,0x00
23+
24+
# GFX950: v_bitop3_b32 v5, v1, v2, s3 bitop3:0xa1 ; encoding: [0x05,0x04,0x34,0xd2,0x01,0x05,0x0e,0x30]
25+
0x05,0x04,0x34,0xd2,0x01,0x05,0x0e,0x30
26+
27+
# GFX950: v_bitop3_b32 v5, m0, 0.5, m0 bitop3:5 ; encoding: [0x05,0x00,0x34,0xd2,0x7c,0xe0,0xf1,0xa1]
28+
0x05,0x00,0x34,0xd2,0x7c,0xe0,0xf1,0xa1
29+
30+
# GFX950: v_bitop3_b32 v5, 0.5, m0, 0.5 bitop3:0x65 ; encoding: [0x05,0x04,0x34,0xd2,0xf0,0xf8,0xc0,0xab]
31+
0x05,0x04,0x34,0xd2,0xf0,0xf8,0xc0,0xab
32+
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# GFX950: v_bitop3_b16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x33,0xd2,0x01,0x05,0x0e,0x00]
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0x05,0x00,0x33,0xd2,0x01,0x05,0x0e,0x00
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# GFX950: v_bitop3_b16 v5, v1, v2, s3 bitop3:0xa1 ; encoding: [0x05,0x04,0x33,0xd2,0x01,0x05,0x0e,0x30]
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0x05,0x04,0x33,0xd2,0x01,0x05,0x0e,0x30

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