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arsenmPravin Jagtap
arsenm
and
Pravin Jagtap
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AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (llvm#117383)
OPSEL[0] selects srcword to read. Co-authored-by: Pravin Jagtap <[email protected]>
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‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

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Original file line numberDiff line numberDiff line change
@@ -899,16 +899,31 @@ def VOP3_CVT_SCALE_FP8BF8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, f32,
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let HasOMod = 0;
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}
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def VOP3_CVT_SCALE_PK_F32_FP8BF8_Profile : VOP3_Profile<VOPProfile<[v2f32, i32, f32, untyped]>,
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VOP3_OPSEL> {
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let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
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FP32InputMods:$src1_modifiers, Src1RC64:$src1,
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op_sel0:$op_sel);
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let HasClamp = 0;
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let HasSrc2 = 0;
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let HasSrc2Mods = 0;
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let HasExtVOP3DPP = 0;
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let HasOpSel = 1;
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let HasOMod = 0;
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}
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let SubtargetPredicate = HasFP8ConversionScaleInsts, mayRaiseFPException = 0 in {
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defm V_CVT_SCALEF32_F16_FP8 : VOP3Inst<"v_cvt_scalef32_f16_fp8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f16>>;
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defm V_CVT_SCALEF32_F32_FP8 : VOP3Inst<"v_cvt_scalef32_f32_fp8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f32>>;
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defm V_CVT_SCALEF32_PK_FP8_F32 : VOP3Inst<"v_cvt_scalef32_pk_fp8_f32", VOP3_CVT_SCALE_FP8BF8_F32_Profile>;
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defm V_CVT_SCALEF32_PK_F32_FP8 : VOP3Inst<"v_cvt_scalef32_pk_f32_fp8", VOP3_CVT_SCALE_PK_F32_FP8BF8_Profile>;
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}
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let SubtargetPredicate = HasBF8ConversionScaleInsts, mayRaiseFPException = 0 in {
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defm V_CVT_SCALEF32_F16_BF8 : VOP3Inst<"v_cvt_scalef32_f16_bf8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f16>>;
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defm V_CVT_SCALEF32_F32_BF8 : VOP3Inst<"v_cvt_scalef32_f32_bf8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f32>>;
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defm V_CVT_SCALEF32_PK_BF8_F32 : VOP3Inst<"v_cvt_scalef32_pk_bf8_f32", VOP3_CVT_SCALE_FP8BF8_F32_Profile>;
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defm V_CVT_SCALEF32_PK_F32_BF8 : VOP3Inst<"v_cvt_scalef32_pk_f32_bf8", VOP3_CVT_SCALE_PK_F32_FP8BF8_Profile>;
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}
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let SubtargetPredicate = isGFX10Plus in {
@@ -1837,9 +1852,11 @@ let OtherPredicates = [HasFP8ConversionScaleInsts] in {
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defm V_CVT_SCALEF32_F16_FP8 : VOP3OpSel_Real_gfx9 <0x24a>;
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defm V_CVT_SCALEF32_F32_FP8 : VOP3OpSel_Real_gfx9 <0x23b>;
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defm V_CVT_SCALEF32_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x235>;
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defm V_CVT_SCALEF32_PK_F32_FP8 : VOP3OpSel_Real_gfx9 <0x239>;
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}
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let OtherPredicates = [HasBF8ConversionScaleInsts] in {
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defm V_CVT_SCALEF32_F16_BF8 : VOP3OpSel_Real_gfx9 <0x24b>;
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defm V_CVT_SCALEF32_F32_BF8 : VOP3OpSel_Real_gfx9 <0x23c>;
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defm V_CVT_SCALEF32_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x236>;
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defm V_CVT_SCALEF32_PK_F32_BF8 : VOP3OpSel_Real_gfx9 <0x23a>;
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}

‎llvm/test/MC/AMDGPU/gfx950_asm_features.s‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -549,3 +549,51 @@ v_cvt_scalef32_pk_bf8_f32 v1, v1, -v2, |v3| op_sel:[0,0,0,1]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_bf8_f32 v1, v1, s2, 3 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x36,0xd2,0x01,0x05,0x0c,0x02]
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v_cvt_scalef32_pk_bf8_f32 v1, v1, s2, 3 op_sel:[0,0,0,1]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x07,0x02,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x07,0x00,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x06,0x01,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x07,0x02,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3 op_sel:[1,0,0]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x07,0x00,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3 op_sel:[1,0,0]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x06,0x01,0x00]
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v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3 op_sel:[1,0,0]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x07,0x02,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x07,0x00,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x06,0x01,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x07,0x02,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3 op_sel:[1,0,0]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x07,0x00,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3 op_sel:[1,0,0]
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x06,0x01,0x00]
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v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3 op_sel:[1,0,0]

‎llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -359,3 +359,39 @@
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# GFX950: v_cvt_scalef32_pk_bf8_f32 v1, v1, s2, 3 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x36,0xd2,0x01,0x05,0x0c,0x02]
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0x01,0x40,0x36,0xd2,0x01,0x05,0x0c,0x02
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x07,0x02,0x00]
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0x02,0x00,0x39,0xd2,0x02,0x07,0x02,0x00
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x07,0x00,0x00]
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0x02,0x00,0x39,0xd2,0x02,0x07,0x00,0x00
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3 ; encoding: [0x02,0x00,0x39,0xd2,0x02,0x06,0x01,0x00]
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0x02,0x00,0x39,0xd2,0x02,0x06,0x01,0x00
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, v3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x07,0x02,0x00]
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0x02,0x08,0x39,0xd2,0x02,0x07,0x02,0x00
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], v2, s3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x07,0x00,0x00]
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0x02,0x08,0x39,0xd2,0x02,0x07,0x00,0x00
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# GFX950: v_cvt_scalef32_pk_f32_fp8 v[2:3], s2, 3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x39,0xd2,0x02,0x06,0x01,0x00]
379+
0x02,0x08,0x39,0xd2,0x02,0x06,0x01,0x00
380+
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x07,0x02,0x00]
382+
0x02,0x00,0x3a,0xd2,0x02,0x07,0x02,0x00
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x07,0x00,0x00]
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0x02,0x00,0x3a,0xd2,0x02,0x07,0x00,0x00
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3 ; encoding: [0x02,0x00,0x3a,0xd2,0x02,0x06,0x01,0x00]
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0x02,0x00,0x3a,0xd2,0x02,0x06,0x01,0x00
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, v3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x07,0x02,0x00]
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0x02,0x08,0x3a,0xd2,0x02,0x07,0x02,0x00
392+
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], v2, s3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x07,0x00,0x00]
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0x02,0x08,0x3a,0xd2,0x02,0x07,0x00,0x00
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# GFX950: v_cvt_scalef32_pk_f32_bf8 v[2:3], s2, 3 op_sel:[1,0,0] ; encoding: [0x02,0x08,0x3a,0xd2,0x02,0x06,0x01,0x00]
397+
0x02,0x08,0x3a,0xd2,0x02,0x06,0x01,0x00

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