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[CIR] Add InlineAsmOp lowering to LLVM (llvm#153387)
- Part of llvm#153267 Added support for lowering `InlineAsmOp` directly to LLVM IR --------- Co-authored-by: Morris Hafner <[email protected]>
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‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -2276,6 +2276,8 @@ void ConvertCIRToLLVMPass::runOnOperation() {
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patterns.add<CIRToLLVMCastOpLowering>(converter, patterns.getContext(), dl);
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patterns.add<CIRToLLVMPtrStrideOpLowering>(converter, patterns.getContext(),
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dl);
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patterns.add<CIRToLLVMInlineAsmOpLowering>(converter, patterns.getContext(),
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dl);
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patterns.add<
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// clang-format off
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CIRToLLVMAssumeOpLowering,
@@ -2956,6 +2958,68 @@ mlir::LogicalResult CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
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return mlir::success();
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}
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mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
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cir::InlineAsmOp op, OpAdaptor adaptor,
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mlir::ConversionPatternRewriter &rewriter) const {
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mlir::Type llResTy;
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if (op.getNumResults())
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llResTy = getTypeConverter()->convertType(op.getType(0));
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cir::AsmFlavor dialect = op.getAsmFlavor();
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mlir::LLVM::AsmDialect llDialect = dialect == cir::AsmFlavor::x86_att
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? mlir::LLVM::AsmDialect::AD_ATT
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: mlir::LLVM::AsmDialect::AD_Intel;
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SmallVector<mlir::Attribute> opAttrs;
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StringRef llvmAttrName = mlir::LLVM::InlineAsmOp::getElementTypeAttrName();
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// this is for the lowering to LLVM from LLVM dialect. Otherwise, if we
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// don't have the result (i.e. void type as a result of operation), the
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// element type attribute will be attached to the whole instruction, but not
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// to the operand
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if (!op.getNumResults())
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opAttrs.push_back(mlir::Attribute());
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SmallVector<mlir::Value> llvmOperands;
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SmallVector<mlir::Value> cirOperands;
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for (auto const&[llvmOp, cirOp] :
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zip(adaptor.getAsmOperands(), op.getAsmOperands())) {
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append_range(llvmOperands, llvmOp);
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append_range(cirOperands, cirOp);
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}
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// so far we infer the llvm dialect element type attr from
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// CIR operand type.
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for (auto const&[cirOpAttr, cirOp] : zip(op.getOperandAttrs(), cirOperands)) {
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if (!cirOpAttr) {
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opAttrs.push_back(mlir::Attribute());
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continue;
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}
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llvm::SmallVector<mlir::NamedAttribute, 1> attrs;
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cir::PointerType typ =
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mlir::cast<cir::PointerType>(cirOp.getType());
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mlir::TypeAttr typAttr = mlir::TypeAttr::get(convertTypeForMemory(
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*getTypeConverter(), dataLayout, typ.getPointee()));
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attrs.push_back(rewriter.getNamedAttr(llvmAttrName, typAttr));
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mlir::DictionaryAttr newDict = rewriter.getDictionaryAttr(attrs);
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opAttrs.push_back(newDict);
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}
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rewriter.replaceOpWithNewOp<mlir::LLVM::InlineAsmOp>(
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op, llResTy, llvmOperands, op.getAsmStringAttr(), op.getConstraintsAttr(),
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op.getSideEffectsAttr(),
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/*is_align_stack*/ mlir::UnitAttr(),
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/*tail_call_kind*/
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mlir::LLVM::TailCallKindAttr::get(
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getContext(), mlir::LLVM::tailcallkind::TailCallKind::None),
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mlir::LLVM::AsmDialectAttr::get(getContext(), llDialect),
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rewriter.getArrayAttr(opAttrs));
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return mlir::success();
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}
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std::unique_ptr<mlir::Pass> createConvertCIRToLLVMPass() {
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return std::make_unique<ConvertCIRToLLVMPass>();
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}

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h‎

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Original file line numberDiff line numberDiff line change
@@ -667,6 +667,23 @@ class CIRToLLVMFAbsOpLowering : public mlir::OpConversionPattern<cir::FAbsOp> {
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mlir::ConversionPatternRewriter &) const override;
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};
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class CIRToLLVMInlineAsmOpLowering
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: public mlir::OpConversionPattern<cir::InlineAsmOp> {
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mlir::DataLayout const &dataLayout;
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public:
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CIRToLLVMInlineAsmOpLowering(const mlir::TypeConverter &typeConverter,
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mlir::MLIRContext *context,
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mlir::DataLayout const &dataLayout)
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: OpConversionPattern(typeConverter, context), dataLayout(dataLayout) {}
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using mlir::OpConversionPattern<cir::InlineAsmOp>::OpConversionPattern;
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mlir::LogicalResult
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matchAndRewrite(cir::InlineAsmOp op, OpAdaptor,
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mlir::ConversionPatternRewriter &) const override;
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};
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} // namespace direct
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} // namespace cir
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‎clang/test/CIR/Lowering/inline-asm.cir‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
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// RUN: cir-translate %s -cir-to-llvmir --target x86_64-unknown-linux-gnu --disable-cc-lowering | FileCheck %s
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!s32i = !cir.int<s, 32>
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!u32i = !cir.int<u, 32>
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module {
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cir.func @f1() {
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// CHECK: call void asm "", "~{dirflag},~{fpsr},~{flags}"()
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cir.asm(x86_att,
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out = [],
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in = [],
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in_out = [],
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{"" "~{dirflag},~{fpsr},~{flags}"})
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cir.return
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}
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cir.func @f2() {
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// CHECK: call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
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cir.asm(x86_att,
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out = [],
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in = [],
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in_out = [],
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{"" "~{dirflag},~{fpsr},~{flags}"}) side_effects
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cir.return
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}
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cir.func @f3() {
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// CHECK: call void asm sideeffect "abc", "~{dirflag},~{fpsr},~{flags}"()
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cir.asm(x86_att,
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out = [],
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in = [],
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in_out = [],
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{"abc" "~{dirflag},~{fpsr},~{flags}"}) side_effects
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cir.return
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}
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cir.func @f4(%arg0: !s32i) {
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%0 = cir.alloca !s32i, !cir.ptr<!s32i>, ["x", init] {alignment = 4 : i64}
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cir.store %arg0, %0 : !s32i, !cir.ptr<!s32i>
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// CHECK: call void asm sideeffect "", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %2)
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cir.asm(x86_att,
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out = [],
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in = [%0 : !cir.ptr<!s32i> (maybe_memory)],
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in_out = [],
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{"" "*m,~{dirflag},~{fpsr},~{flags}"}) side_effects
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cir.return
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}
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cir.func @f5() {
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// CHECK: call void asm inteldialect "", "~{dirflag},~{fpsr},~{flags}"()
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cir.asm(x86_intel,
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out = [],
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in = [],
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in_out = [],
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{"" "~{dirflag},~{fpsr},~{flags}"})
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cir.return
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}
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cir.func @f6() -> !s32i {
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%0 = cir.alloca !s32i, !cir.ptr<!s32i>, ["x", init] {alignment = 4 : i64}
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// CHECK: %2 = call i32 asm sideeffect "movl $$42, $0", "=r,~{dirflag},~{fpsr},~{flags}"()
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%1 = cir.asm(x86_att,
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out = [],
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in = [],
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in_out = [],
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{"movl $$42, $0" "=r,~{dirflag},~{fpsr},~{flags}"}) side_effects -> !s32i
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cir.store align(4) %1, %0 : !s32i, !cir.ptr<!s32i>
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%3 = cir.load align(4) %0 : !cir.ptr<!s32i>, !s32i
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cir.return %3 : !s32i
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}
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cir.func @f7(%arg0: !u32i) -> !u32i {
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%0 = cir.alloca !u32i, !cir.ptr<!u32i>, ["x", init] {alignment = 4 : i64}
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cir.store %arg0, %0 : !u32i, !cir.ptr<!u32i>
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%1 = cir.load align(4) %0 : !cir.ptr<!u32i>, !u32i
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// CHECK: %4 = call i32 asm sideeffect "addl $$42, $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %3)
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%2 = cir.asm(x86_att,
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out = [],
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in = [],
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in_out = [%1 : !u32i],
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{"addl $$42, $0" "=r,0,~{dirflag},~{fpsr},~{flags}"}) side_effects -> !u32i
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cir.store align(4) %2, %0 : !u32i, !cir.ptr<!u32i>
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%3 = cir.load align(4) %0 : !cir.ptr<!u32i>, !u32i
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cir.return %3 : !u32i
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}
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}

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