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[SelectionDAG] Move SDNode::use_iterator::getOperandNo to SDUse. (llvm#120536)
This allows us to write more range based for loops because we no longer need the iterator. It also matches IR's Use class.
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11 files changed

+61
-72
lines changed

11 files changed

+61
-72
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,9 @@ class SDUse {
310310
/// Get the next SDUse in the use list.
311311
SDUse *getNext() const { return Next; }
312312

313+
/// Return the operand # of this use in its user.
314+
inline unsigned getOperandNo() const;
315+
313316
/// Convenience function for get().getNode().
314317
SDNode *getNode() const { return Val.getNode(); }
315318
/// Convenience function for get().getResNo().
@@ -824,12 +827,6 @@ END_TWO_BYTE_PACK()
824827
}
825828

826829
SDUse *operator->() const { return &operator*(); }
827-
828-
/// Retrieve the operand # of this use in its user.
829-
unsigned getOperandNo() const {
830-
assert(Op && "Cannot dereference end iterator!");
831-
return (unsigned)(Op - Op->getUser()->OperandList);
832-
}
833830
};
834831

835832
class user_iterator {
@@ -1303,6 +1300,9 @@ inline void SDValue::dumpr(const SelectionDAG *G) const {
13031300
}
13041301

13051302
// Define inline functions from the SDUse class.
1303+
inline unsigned SDUse::getOperandNo() const {
1304+
return this - getUser()->op_begin();
1305+
}
13061306

13071307
inline void SDUse::set(const SDValue &V) {
13081308
if (Val.getNode()) removeFromList();

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 11 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -18921,10 +18921,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
1892118921
SmallVector<SDNode *, 16> OtherUses;
1892218922
unsigned MaxSteps = SelectionDAG::getHasPredecessorMaxSteps();
1892318923
if (isa<ConstantSDNode>(Offset))
18924-
for (SDNode::use_iterator UI = BasePtr->use_begin(),
18925-
UE = BasePtr->use_end();
18926-
UI != UE; ++UI) {
18927-
SDUse &Use = *UI;
18924+
for (SDUse &Use : BasePtr->uses()) {
1892818925
// Skip the use that is Ptr and uses of other results from BasePtr's
1892918926
// node (important for nodes that return multiple results).
1893018927
if (Use.getUser() == Ptr.getNode() || Use != BasePtr)
@@ -18940,7 +18937,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
1894018937
break;
1894118938
}
1894218939

18943-
SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1);
18940+
SDValue Op1 = Use.getUser()->getOperand((Use.getOperandNo() + 1) & 1);
1894418941
if (!isa<ConstantSDNode>(Op1)) {
1894518942
OtherUses.clear();
1894618943
break;
@@ -20931,11 +20928,11 @@ DAGCombiner::getStoreMergeCandidates(StoreSDNode *St,
2093120928
RootCount->second.second > StoreMergeDependenceLimit;
2093220929
};
2093320930

20934-
auto TryToAddCandidate = [&](SDNode::use_iterator UseIter) {
20931+
auto TryToAddCandidate = [&](SDUse &Use) {
2093520932
// This must be a chain use.
20936-
if (UseIter.getOperandNo() != 0)
20933+
if (Use.getOperandNo() != 0)
2093720934
return;
20938-
if (auto *OtherStore = dyn_cast<StoreSDNode>(UseIter->getUser())) {
20935+
if (auto *OtherStore = dyn_cast<StoreSDNode>(Use.getUser())) {
2093920936
BaseIndexOffset Ptr;
2094020937
int64_t PtrDiff;
2094120938
if (CandidateMatch(OtherStore, Ptr, PtrDiff) &&
@@ -20954,19 +20951,19 @@ DAGCombiner::getStoreMergeCandidates(StoreSDNode *St,
2095420951
for (auto I = RootNode->use_begin(), E = RootNode->use_end();
2095520952
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) {
2095620953
SDNode *User = I->getUser();
20957-
if (I.getOperandNo() == 0 && isa<LoadSDNode>(User)) { // walk down chain
20958-
for (auto I2 = User->use_begin(), E2 = User->use_end(); I2 != E2; ++I2)
20959-
TryToAddCandidate(I2);
20954+
if (I->getOperandNo() == 0 && isa<LoadSDNode>(User)) { // walk down chain
20955+
for (SDUse &U2 : User->uses())
20956+
TryToAddCandidate(U2);
2096020957
}
2096120958
// Check stores that depend on the root (e.g. Store 3 in the chart above).
20962-
if (I.getOperandNo() == 0 && isa<StoreSDNode>(User)) {
20963-
TryToAddCandidate(I);
20959+
if (I->getOperandNo() == 0 && isa<StoreSDNode>(User)) {
20960+
TryToAddCandidate(*I);
2096420961
}
2096520962
}
2096620963
} else {
2096720964
for (auto I = RootNode->use_begin(), E = RootNode->use_end();
2096820965
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored)
20969-
TryToAddCandidate(I);
20966+
TryToAddCandidate(*I);
2097020967
}
2097120968

2097220969
return RootNode;

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3755,7 +3755,7 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
37553755
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
37563756
Limit < 10 && U != E; ++U, ++Limit) {
37573757
const TargetRegisterClass *RC =
3758-
getOperandRegClass(U->getUser(), U.getOperandNo());
3758+
getOperandRegClass(U->getUser(), U->getOperandNo());
37593759

37603760
// If the register class is unknown, it could be an unknown
37613761
// register class that needs to be an SGPR, e.g. an inline asm
@@ -3770,7 +3770,7 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
37703770
unsigned Opc = User->getMachineOpcode();
37713771
const MCInstrDesc &Desc = SII->get(Opc);
37723772
if (Desc.isCommutable()) {
3773-
unsigned OpIdx = Desc.getNumDefs() + U.getOperandNo();
3773+
unsigned OpIdx = Desc.getNumDefs() + U->getOperandNo();
37743774
unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
37753775
if (SII->findCommutedOpIndices(Desc, OpIdx, CommuteIdx1)) {
37763776
unsigned CommutedOpNo = CommuteIdx1 - Desc.getNumDefs();

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16874,10 +16874,9 @@ bool SITargetLowering::requiresUniformRegister(MachineFunction &MF,
1687416874
}
1687516875

1687616876
bool SITargetLowering::hasMemSDNodeUser(SDNode *N) const {
16877-
SDNode::use_iterator I = N->use_begin(), E = N->use_end();
16878-
for (; I != E; ++I) {
16879-
if (MemSDNode *M = dyn_cast<MemSDNode>(I->getUser())) {
16880-
if (getBasePtrIndex(M) == I.getOperandNo())
16877+
for (SDUse &Use : N->uses()) {
16878+
if (MemSDNode *M = dyn_cast<MemSDNode>(Use.getUser())) {
16879+
if (getBasePtrIndex(M) == Use.getOperandNo())
1688116880
return true;
1688216881
}
1688316882
}

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16219,13 +16219,12 @@ static SDValue CombineBaseUpdate(SDNode *N,
1621916219
SmallVector<BaseUpdateUser, 8> BaseUpdates;
1622016220

1622116221
// Search for a use of the address operand that is an increment.
16222-
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
16223-
UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
16224-
SDNode *User = UI->getUser();
16225-
if (UI->getResNo() != Addr.getResNo() || User->getNumOperands() != 2)
16222+
for (SDUse &Use : Addr->uses()) {
16223+
SDNode *User = Use.getUser();
16224+
if (Use.getResNo() != Addr.getResNo() || User->getNumOperands() != 2)
1622616225
continue;
1622716226

16228-
SDValue Inc = User->getOperand(UI.getOperandNo() == 1 ? 0 : 1);
16227+
SDValue Inc = User->getOperand(Use.getOperandNo() == 1 ? 0 : 1);
1622916228
unsigned ConstInc =
1623016229
getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG);
1623116230

@@ -16240,15 +16239,14 @@ static SDValue CombineBaseUpdate(SDNode *N,
1624016239
if (findPointerConstIncrement(Addr.getNode(), &Base, &CInc)) {
1624116240
unsigned Offset =
1624216241
getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG);
16243-
for (SDNode::use_iterator UI = Base->use_begin(), UE = Base->use_end();
16244-
UI != UE; ++UI) {
16242+
for (SDUse &Use : Base->uses()) {
1624516243

16246-
SDNode *User = UI->getUser();
16247-
if (UI->getResNo() != Base.getResNo() || User == Addr.getNode() ||
16244+
SDNode *User = Use.getUser();
16245+
if (Use.getResNo() != Base.getResNo() || User == Addr.getNode() ||
1624816246
User->getNumOperands() != 2)
1624916247
continue;
1625016248

16251-
SDValue UserInc = User->getOperand(UI.getOperandNo() == 0 ? 1 : 0);
16249+
SDValue UserInc = User->getOperand(Use.getOperandNo() == 0 ? 1 : 0);
1625216250
unsigned UserOffset =
1625316251
getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG);
1625416252

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1302,8 +1302,8 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
13021302
EVT OpVT = OpI1.getValueType();
13031303
if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1)
13041304
continue;
1305-
for (auto I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1306-
SDNode *U = I->getUser();
1305+
for (SDUse &Use : N->uses()) {
1306+
SDNode *U = Use.getUser();
13071307
if (U->getNumValues() != 1)
13081308
continue;
13091309
EVT UVT = U->getValueType(0);
@@ -1316,7 +1316,7 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
13161316
continue;
13171317

13181318
// Potentially simplifiable operation.
1319-
unsigned I1N = I.getOperandNo();
1319+
unsigned I1N = Use.getOperandNo();
13201320
SmallVector<SDValue,2> Ops(U->getNumOperands());
13211321
for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i)
13221322
Ops[i] = U->getOperand(i);

‎llvm/lib/Target/M68k/M68kISelLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1849,10 +1849,10 @@ static bool hasNonFlagsUse(SDValue Op) {
18491849
for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
18501850
++UI) {
18511851
SDNode *User = UI->getUser();
1852-
unsigned UOpNo = UI.getOperandNo();
1852+
unsigned UOpNo = UI->getOperandNo();
18531853
if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1854-
// Look pass truncate.
1855-
UOpNo = User->use_begin().getOperandNo();
1854+
// Look past truncate.
1855+
UOpNo = User->use_begin()->getOperandNo();
18561856
User = User->use_begin()->getUser();
18571857
}
18581858

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -954,9 +954,8 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
954954
// Cannot use range-based for loop here as we need the actual use (i.e. we
955955
// need the operand number corresponding to the use). A range-based for
956956
// will unbox the use and provide an SDNode*.
957-
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
958-
++UI) {
959-
SDNode *User = UI->getUser();
957+
for (SDUse &Use : N->uses()) {
958+
SDNode *User = Use.getUser();
960959
unsigned Opc =
961960
User->isMachineOpcode() ? User->getMachineOpcode() : User->getOpcode();
962961
switch (Opc) {
@@ -972,7 +971,7 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
972971
return 0;
973972
StoreSDNode *STN = cast<StoreSDNode>(User);
974973
unsigned MemVTSize = STN->getMemoryVT().getSizeInBits();
975-
if (MemVTSize == 64 || UI.getOperandNo() != 0)
974+
if (MemVTSize == 64 || Use.getOperandNo() != 0)
976975
return 0;
977976
MaxTruncation = std::max(MaxTruncation, MemVTSize);
978977
continue;
@@ -981,23 +980,23 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
981980
case PPC::STWX8:
982981
case PPC::STWU8:
983982
case PPC::STWUX8:
984-
if (UI.getOperandNo() != 0)
983+
if (Use.getOperandNo() != 0)
985984
return 0;
986985
MaxTruncation = std::max(MaxTruncation, 32u);
987986
continue;
988987
case PPC::STH8:
989988
case PPC::STHX8:
990989
case PPC::STHU8:
991990
case PPC::STHUX8:
992-
if (UI.getOperandNo() != 0)
991+
if (Use.getOperandNo() != 0)
993992
return 0;
994993
MaxTruncation = std::max(MaxTruncation, 16u);
995994
continue;
996995
case PPC::STB8:
997996
case PPC::STBX8:
998997
case PPC::STBU8:
999998
case PPC::STBUX8:
1000-
if (UI.getOperandNo() != 0)
999+
if (Use.getOperandNo() != 0)
10011000
return 0;
10021001
MaxTruncation = std::max(MaxTruncation, 8u);
10031002
continue;

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3293,16 +3293,16 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
32933293
if (Depth == 0 && !Node->getValueType(0).isScalarInteger())
32943294
return false;
32953295

3296-
for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {
3297-
SDNode *User = UI->getUser();
3296+
for (SDUse &Use : Node->uses()) {
3297+
SDNode *User = Use.getUser();
32983298
// Users of this node should have already been instruction selected
32993299
if (!User->isMachineOpcode())
33003300
return false;
33013301

33023302
// TODO: Add more opcodes?
33033303
switch (User->getMachineOpcode()) {
33043304
default:
3305-
if (vectorPseudoHasAllNBitUsers(User, UI.getOperandNo(), Bits, TII))
3305+
if (vectorPseudoHasAllNBitUsers(User, Use.getOperandNo(), Bits, TII))
33063306
break;
33073307
return false;
33083308
case RISCV::ADDW:
@@ -3353,7 +3353,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
33533353
case RISCV::BCLR:
33543354
case RISCV::BINV:
33553355
// Shift amount operands only use log2(Xlen) bits.
3356-
if (UI.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen()))
3356+
if (Use.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen()))
33573357
break;
33583358
return false;
33593359
case RISCV::SLLI:
@@ -3417,19 +3417,19 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
34173417
case RISCV::SH3ADD_UW:
34183418
// The first operand to add.uw/shXadd.uw is implicitly zero extended from
34193419
// 32 bits.
3420-
if (UI.getOperandNo() == 0 && Bits >= 32)
3420+
if (Use.getOperandNo() == 0 && Bits >= 32)
34213421
break;
34223422
return false;
34233423
case RISCV::SB:
3424-
if (UI.getOperandNo() == 0 && Bits >= 8)
3424+
if (Use.getOperandNo() == 0 && Bits >= 8)
34253425
break;
34263426
return false;
34273427
case RISCV::SH:
3428-
if (UI.getOperandNo() == 0 && Bits >= 16)
3428+
if (Use.getOperandNo() == 0 && Bits >= 16)
34293429
break;
34303430
return false;
34313431
case RISCV::SW:
3432-
if (UI.getOperandNo() == 0 && Bits >= 32)
3432+
if (Use.getOperandNo() == 0 && Bits >= 32)
34333433
break;
34343434
return false;
34353435
}

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15688,14 +15688,12 @@ static SDValue combineOp_VLToVWOp_VL(SDNode *N,
1568815688
auto AppendUsersIfNeeded = [&Worklist, &Subtarget,
1568915689
&Inserted](const NodeExtensionHelper &Op) {
1569015690
if (Op.needToPromoteOtherUsers()) {
15691-
for (SDNode::use_iterator UI = Op.OrigOperand->use_begin(),
15692-
UE = Op.OrigOperand->use_end();
15693-
UI != UE; ++UI) {
15694-
SDNode *TheUser = UI->getUser();
15691+
for (SDUse &Use : Op.OrigOperand->uses()) {
15692+
SDNode *TheUser = Use.getUser();
1569515693
if (!NodeExtensionHelper::isSupportedRoot(TheUser, Subtarget))
1569615694
return false;
1569715695
// We only support the first 2 operands of FMA.
15698-
if (UI.getOperandNo() >= 2)
15696+
if (Use.getOperandNo() >= 2)
1569915697
return false;
1570015698
if (Inserted.insert(TheUser).second)
1570115699
Worklist.push_back(TheUser);

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