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<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.cache.</span></span><spanclass="sig-name descname"><spanclass="pre">get_cache_dir</span></span><spanclass="sig-paren">(</span><spanclass="sig-paren">)</span><spanclass="sig-return"><spanclass="sig-return-icon">→</span><spanclass="sig-return-typehint"><spanclass="pre">Path</span></span></span><aclass="headerlink" href="#tilelang.cache.get_cache_dir" title="Permalink to this definition">#</a></dt>
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<dd><p>Gets the cache directory for the kernel cache.
<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.cache.</span></span><spanclass="sig-name descname"><spanclass="pre">set_cache_dir</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="n"><spanclass="pre">cache_dir</span></span><spanclass="p"><spanclass="pre">:</span></span><spanclass="w"></span><spanclass="n"><spanclass="pre">str</span></span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.cache.set_cache_dir" title="Permalink to this definition">#</a></dt>
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<dd><p>Sets the cache directory for the kernel cache.
<spanclass="sig-name descname"><spanclass="pre">cache_dir</span></span><emclass="property"><spanclass="p"><spanclass="pre">:</span></span><spanclass="w"></span><spanclass="pre">Path</span></em><emclass="property"><spanclass="w"></span><spanclass="p"><spanclass="pre">=</span></span><spanclass="w"></span><spanclass="pre">PosixPath('/home/t-leiwang/.tilelang/cache')</span></em><aclass="headerlink" href="#tilelang.cache.kernel_cache.KernelCache.cache_dir" title="Permalink to this definition">#</a></dt>
<spanclass="sig-name descname"><spanclass="pre">get_cache_dir</span></span><spanclass="sig-paren">(</span><spanclass="sig-paren">)</span><spanclass="sig-return"><spanclass="sig-return-icon">→</span><spanclass="sig-return-typehint"><spanclass="pre">Path</span></span></span><aclass="headerlink" href="#tilelang.cache.kernel_cache.KernelCache.get_cache_dir" title="Permalink to this definition">#</a></dt>
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<dd><p>Gets the cache directory for the kernel cache.</p>
<spanclass="sig-name descname"><spanclass="pre">set_cache_dir</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="n"><spanclass="pre">cache_dir</span></span><spanclass="p"><spanclass="pre">:</span></span><spanclass="w"></span><spanclass="n"><spanclass="pre">str</span></span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.cache.kernel_cache.KernelCache.set_cache_dir" title="Permalink to this definition">#</a></dt>
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<dd><p>Sets the cache directory for the kernel cache.</p>
<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.language.logical.</span></span><spanclass="sig-name descname"><spanclass="pre">all_of</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="pre">buffer:</span><spanclass="pre">~typing.Union[<tilelang.language.proxy.TensorProxy</span><spanclass="pre">object</span><spanclass="pre">at</span><spanclass="pre">0x7f0bb4ecb250>,</span><spanclass="pre">~tvm.tir.stmt.BufferRegion]</span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.language.logical.all_of" title="Permalink to this definition">#</a></dt>
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<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.language.logical.</span></span><spanclass="sig-name descname"><spanclass="pre">all_of</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="pre">buffer:</span><spanclass="pre">~typing.Union[<tilelang.language.proxy.TensorProxy</span><spanclass="pre">object</span><spanclass="pre">at</span><spanclass="pre">0x7f138cbb8790>,</span><spanclass="pre">~tvm.tir.stmt.BufferRegion]</span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.language.logical.all_of" title="Permalink to this definition">#</a></dt>
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<dd><p>Check if all elements in the buffer are true.</p>
<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.language.logical.</span></span><spanclass="sig-name descname"><spanclass="pre">any_of</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="pre">buffer:</span><spanclass="pre">~typing.Union[<tilelang.language.proxy.TensorProxy</span><spanclass="pre">object</span><spanclass="pre">at</span><spanclass="pre">0x7f0bb4ecb250>,</span><spanclass="pre">~tvm.tir.stmt.BufferRegion]</span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.language.logical.any_of" title="Permalink to this definition">#</a></dt>
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<spanclass="sig-prename descclassname"><spanclass="pre">tilelang.language.logical.</span></span><spanclass="sig-name descname"><spanclass="pre">any_of</span></span><spanclass="sig-paren">(</span><emclass="sig-param"><spanclass="pre">buffer:</span><spanclass="pre">~typing.Union[<tilelang.language.proxy.TensorProxy</span><spanclass="pre">object</span><spanclass="pre">at</span><spanclass="pre">0x7f138cbb8790>,</span><spanclass="pre">~tvm.tir.stmt.BufferRegion]</span></em><spanclass="sig-paren">)</span><aclass="headerlink" href="#tilelang.language.logical.any_of" title="Permalink to this definition">#</a></dt>
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<dd><p>Check if any element in the buffer is true.</p>
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