|
| 1 | +# InjectFenceProxy Pass |
| 2 | + |
| 3 | +`tl.InjectFenceProxy` is a TIR-level transform that keeps the GPU proxy state consistent on NVIDIA Hopper (SM90+) by inserting `fence.proxy.async` instructions when control flow switches from generic memory operations to asynchronous proxy operations. |
| 4 | + |
| 5 | +## Why Fences Are Needed |
| 6 | + |
| 7 | +Hopper separates memory instructions into generic and asynchronous proxy paths. When an asynchronous instruction (for example, `cp.async` or `tma.load`) issues after generic traffic (like `ldmatrix` or plain buffer stores), the hardware requires a `fence.proxy.async` to guarantee ordering. Missing fences can lead to race conditions or undefined behaviour. |
| 8 | + |
| 9 | +## What the Pass Does |
| 10 | + |
| 11 | +- Walks every statement in the `PrimFunc`, tracking whether it behaves as a **generic**, **async**, or **neutral** proxy (neutral statements reset the state, such as an explicit fence). |
| 12 | +- Automatically lowers `tma_store` intrinsics into the required `arrive`/`wait` handshake so that TMA stores participate correctly in synchronization. |
| 13 | +- Injects an explicit `fence.proxy.async` whenever a generic statement is followed by an async statement without an intervening neutral barrier. |
| 14 | + |
| 15 | +The pass is conservative: unknown extern calls are treated as async so that the fence is inserted rather than accidentally omitted. |
| 16 | + |
| 17 | +### Timeline View |
| 18 | + |
| 19 | +``` |
| 20 | +generic initialize_descriptor → generic shared-store → async wgmma |
| 21 | + │ │ │ |
| 22 | + └─ generic proxy ┴─ generic proxy ┴─ async proxy |
| 23 | + │ fence inserted here ↑ |
| 24 | + └──────────────────────────────┘ |
| 25 | +``` |
| 26 | + |
| 27 | +The proxy tracker scans the sequence from left to right. The moment it detects a transition from generic to async (between the store and `cp.async` above), it synthesizes a `fence.proxy.async` to reset the hardware proxy state before the async path runs. |
| 28 | + |
| 29 | +## Coverage of Intrinsics |
| 30 | + |
| 31 | +The tracker understands the TileLang intrinsics for TMA load/store, shared-memory MMA (`wgmma`), and TVM/PTX async copy intrinsics (`cp.async` variants). Generic operations currently include `ldmatrix`, `stmatrix`, and descriptor initialization. Other IR nodes (loops, blocks, attributes) receive a proxy kind derived from their bodies so that the analysis survives structured control flow. |
| 32 | + |
| 33 | +## Usage |
| 34 | + |
| 35 | +The pass is part of the default TileLang lowering pipeline. To apply it manually: |
| 36 | + |
| 37 | +```python |
| 38 | +from tilelang import tl |
| 39 | +from tvm import IRModule |
| 40 | + |
| 41 | +mod = IRModule({"main": prim_func}) |
| 42 | +with tvm.transform.PassContext(): |
| 43 | + mod = tl.transform.InjectFenceProxy()(mod) |
| 44 | +``` |
| 45 | + |
| 46 | +## End-to-End Example |
| 47 | + |
| 48 | +Before the pass: |
| 49 | + |
| 50 | +```python |
| 51 | +@T.prim_func |
| 52 | +def kernel(): |
| 53 | + with T.Kernel(1): |
| 54 | + desc = T.decl_buffer((1,), "uint64", scope="local.descriptor") |
| 55 | + smem = T.decl_buffer((128,), "float16", scope="shared") |
| 56 | + T.initialize_descriptor(desc, T.uint64(0), 2, 1, 32) |
| 57 | + smem[0] = T.float16(0) |
| 58 | + T.ptx_wgmma_ss( |
| 59 | + "float16", |
| 60 | + "m64n64k16", |
| 61 | + T.bool(True), |
| 62 | + T.bool(True), |
| 63 | + "fp16", |
| 64 | + "fp16", |
| 65 | + "fp16", |
| 66 | + desc.data, |
| 67 | + T.int32(0), |
| 68 | + desc.data, |
| 69 | + T.int32(0), |
| 70 | + smem.data, |
| 71 | + T.int32(0), |
| 72 | + T.bool(True), |
| 73 | + 1, |
| 74 | + 1, |
| 75 | + ) |
| 76 | +``` |
| 77 | + |
| 78 | +After `tl.transform.InjectFenceProxy`: |
| 79 | + |
| 80 | +```python |
| 81 | +@T.prim_func |
| 82 | +def kernel(): |
| 83 | + with T.Kernel(1): |
| 84 | + desc = T.decl_buffer((1,), "uint64", scope="local.descriptor") |
| 85 | + smem = T.decl_buffer((128,), "float16", scope="shared") |
| 86 | + T.initialize_descriptor(desc, T.uint64(0), 2, 1, 32) |
| 87 | + smem[0] = T.float16(0) |
| 88 | + T.fence_proxy_async() |
| 89 | + T.ptx_wgmma_ss( |
| 90 | + "float16", |
| 91 | + "m64n64k16", |
| 92 | + T.bool(True), |
| 93 | + T.bool(True), |
| 94 | + "fp16", |
| 95 | + "fp16", |
| 96 | + "fp16", |
| 97 | + desc.data, |
| 98 | + T.int32(0), |
| 99 | + desc.data, |
| 100 | + T.int32(0), |
| 101 | + smem.data, |
| 102 | + T.int32(0), |
| 103 | + T.bool(True), |
| 104 | + 1, |
| 105 | + 1, |
| 106 | + ) |
| 107 | +``` |
| 108 | + |
| 109 | +The only change is the `fence_proxy_async` between the generic descriptor setup / shared-memory write and the async `wgmma`. In larger kernels the pass performs the same operation across nested blocks, loops, and conditional branches. |
| 110 | + |
| 111 | +## Extending the Pass |
| 112 | + |
| 113 | +If you introduce a new intrinsic that behaves like an async proxy, add it to `IsAsyncIntrinsic` in `src/transform/inject_fence_proxy.cc`. Likewise, extend `IsKnownGeneric` for additional generic operations. When adding new neutral barriers, make sure they set the proxy kind to `kNeutral` so the state resets correctly. |
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