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| 1 | +The Tile Language: A Brief Introduction |
| 2 | +=============================== |
| 3 | + |
| 4 | +.. _sec-overview: |
| 5 | + |
| 6 | +Programming Interface |
| 7 | +--------------------- |
| 8 | + |
| 9 | +The figure below depicts how **TileLang** programs are progressively lowered from a high-level description to hardware-specific executables. We provide three different programming interfaces—targeted at **Beginner**, **Developer**, and **Expert** users—that each reside at different levels in this lowering pipeline. The **Tile Language** also allows mixing these interfaces within the same kernel, enabling users to work at whichever level of abstraction best suits their needs. |
| 10 | + |
| 11 | +.. _fig-overview: |
| 12 | + |
| 13 | +.. figure:: ../_static/img/overview.png |
| 14 | + :align: center |
| 15 | + :width: 50% |
| 16 | + :alt: Overview |
| 17 | + |
| 18 | + High-level overview of the TileLang compilation flow. |
| 19 | + |
| 20 | +Programming Interfaces |
| 21 | +---------------------- |
| 22 | + |
| 23 | +1. **Beginner Level (Hardware-Unaware)** |
| 24 | + - Intended for users who need to write code that is independent of specific hardware details. |
| 25 | + - The goal is to let developers focus on the basic logic without worrying about memory hierarchies or hardware-specific optimizations. |
| 26 | + - *Note:* This interface is not yet fully implemented. |
| 27 | + |
| 28 | +2. **Developer Level (Hardware-Aware with Tile Library)** |
| 29 | + - Designed for developers who have a basic understanding of GPU memory hierarchies and performance considerations. |
| 30 | + - Provides a **Tile Library**, containing predefined operations and patterns optimized for various hardware architectures. |
| 31 | + - Users at this level can leverage these ready-made primitives without diving into low-level threading details. |
| 32 | + |
| 33 | +3. **Expert Level (Hardware-Aware with Thread Primitives)** |
| 34 | + - For highly experienced users who have an in-depth understanding of low-level hardware characteristics (e.g., threading models, memory coalescing). |
| 35 | + - Offers direct access to **thread primitives** and other low-level constructs, allowing for fine-grained control of performance-critical kernels. |
| 36 | + - This level grants maximum flexibility for specialized optimizations tailored to specific GPU or multi-core architectures. |
| 37 | + |
| 38 | +Compilation Flow |
| 39 | +---------------- |
| 40 | + |
| 41 | +1. **Tile Program** |
| 42 | + A high-level specification of the computation. Depending on the user’s expertise, they may write a purely hardware-unaware tile program or incorporate constructs from the Tile Library or thread primitives. |
| 43 | + |
| 44 | +2. **Tile Program with Tile Library** |
| 45 | + When developers choose from the Tile Library, the original Tile Program is expanded with specialized library calls. These calls encapsulate efficient implementation patterns for different operations. |
| 46 | + |
| 47 | +3. **Tile Program with Thread Primitives** |
| 48 | + Expert-level developers can explicitly use low-level threading constructs to hand-optimize data layout, synchronization, and memory usage. |
| 49 | + |
| 50 | +4. **IRModule** |
| 51 | + After the program is composed with libraries or thread primitives, it is lowered to an intermediate representation (IR) that captures the necessary hardware details. |
| 52 | + |
| 53 | +5. **Source Code Generation (C/CUDA/HIP/LLVM/…)** |
| 54 | + From the IR, the system generates target-specific source code. This source code is tuned for the desired backends or GPU architectures (e.g., NVIDIA, AMD). |
| 55 | + |
| 56 | +6. **Hardware-Specific Executable/Runtime** |
| 57 | + Finally, the generated source is compiled into hardware-specific executables, ready to run on the corresponding devices. The pipeline supports multiple GPU backends and can be extended to additional architectures. |
| 58 | + |
| 59 | + |
| 60 | +.. _sec-tile_based_programming_model: |
| 61 | + |
| 62 | +Tile-based Programming Model |
| 63 | +---------------------------- |
| 64 | + |
| 65 | +Figure :ref:`fig-matmul_example` provides a concise matrix multiplication (GEMM) example in ``TileLang``, |
| 66 | +illustrating how developers can employ high-level constructs such as tiles, memory placement, pipelining, |
| 67 | +and operator calls to manage data movement and computation with fine-grained control. |
| 68 | +In particular, this snippet (Figure :ref:`fig-matmul_example` (a)) demonstrates how multi-level tiling |
| 69 | +leverages different memory hierarchies (global, shared, and registers) to optimize bandwidth utilization |
| 70 | +and reduce latency. |
| 71 | +Overall, Figure :ref:`fig-matmul_example` (b) showcases how the Python-like syntax of ``TileLang`` |
| 72 | +allows developers to reason about performance-critical optimizations within a user-friendly programming model. |
| 73 | + |
| 74 | +.. _fig-matmul_example: |
| 75 | + |
| 76 | +.. figure:: ../_static/img/MatmulExample.png |
| 77 | + :align: center |
| 78 | + :width: 100% |
| 79 | + :alt: GEMM with Multi-Level Tiling on GPUs |
| 80 | + |
| 81 | + Optimizing GEMM with Multi-Level Tiling on GPUs via ``TileLang``. |
| 82 | + |
| 83 | +Tile declarations |
| 84 | +~~~~~~~~~~~~~~~~~ |
| 85 | + |
| 86 | +At the heart of our approach is the notion of *tiles* as first-class objects in the programming model. |
| 87 | +A tile represents a shaped portion of data, which can be owned and manipulated by a warp, thread block, |
| 88 | +or equivalent parallel unit. |
| 89 | +In the ``Matmul`` example, the ``A`` and ``B`` buffers are read in tiled chunks (determined by ``block_M``, |
| 90 | +``block_N``, ``block_K``) inside the kernel loop. |
| 91 | +With ``T.Kernel``, ``TileLang`` defines the execution context, which includes the thread block index (``bx`` |
| 92 | +and ``by``) and the number of threads. |
| 93 | +These contexts can help compute the index for each thread block and make it easier for ``TileLang`` |
| 94 | +to automatically infer and optimize memory access and computation. |
| 95 | +Additionally, these contexts allow users to manually control the behavior of each independent thread within |
| 96 | +a thread block. |
| 97 | + |
| 98 | +Explicit Hardware Memory Allocation |
| 99 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 100 | + |
| 101 | +A hallmark of ``TileLang`` is the ability to explicitly place these tile buffers in the hardware memory hierarchy. |
| 102 | +Rather than leaving it to a compiler's opaque optimization passes, ``TileLang`` exposes user-facing intrinsics |
| 103 | +that map directly to physical memory spaces or accelerator-specific constructs. |
| 104 | +In particular: |
| 105 | + |
| 106 | +- ``T.alloc_shared``: Allocates memory in a fast, on-chip storage space, which corresponds to shared memory on NVIDIA GPUs. |
| 107 | + Shared memory is ideal for caching intermediate data during computations, as it is significantly faster than global memory |
| 108 | + and allows for efficient data sharing between threads in the same thread block. |
| 109 | + For example, in matrix multiplication, tiles of matrices can be loaded into shared memory |
| 110 | + to reduce global memory bandwidth demands and improve performance. |
| 111 | + |
| 112 | +- ``T.alloc_fragment``: Allocates accumulators in fragment memory, which corresponds to register files on NVIDIA GPUs. |
| 113 | + By keeping inputs and partial sums in registers or hardware-level caches, latency is further minimized. |
| 114 | + Note that in this tile program, each tile allocates the same local buffers as shared memory, |
| 115 | + which might seem counterintuitive, as shared memory is generally faster but more abundant, |
| 116 | + whereas register file space is limited. |
| 117 | + This is because the allocation here refers to the register files for an entire thread block. |
| 118 | + ``TileLang`` uses a Layout Inference Pass during compilation to derive a Layout object ``T.Fragment``, |
| 119 | + which determines how to allocate the corresponding register files for each thread. |
| 120 | + This process will be discussed in detail in subsequent sections. |
| 121 | + |
| 122 | +Data transfer between global memory and hardware-specific memory can be managed using ``T.copy``. |
| 123 | +Furthermore, hardware-specific buffers can be initialized using ``T.clear`` or ``T.fill``. |
| 124 | +For data assignments, operations can also be performed in parallel using ``T.Parallel``, |
| 125 | +as demonstrated in Layout Inference Pass in the following sections. |
| 126 | + |
| 127 | + |
| 128 | +.. _fig-layout_inference: |
| 129 | + |
| 130 | +.. figure:: ../_static/img/LayoutInference.png |
| 131 | + :align: center |
| 132 | + :width: 100% |
| 133 | + :alt: GEMM with Multi-Level Tiling on GPUs |
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