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| 1 | +package l3gd20 |
| 2 | + |
| 3 | +// Expected identification number for L3GD20. |
| 4 | +const ( |
| 5 | + // For L3GD20 |
| 6 | + expectedWHOAMI = 0xD4 |
| 7 | + // For L3GD20H |
| 8 | + expectedWHOAMI_H = 0xD7 |
| 9 | +) |
| 10 | + |
| 11 | +// Register bits masks |
| 12 | +const ( |
| 13 | + reg5RebootBit = 1 << 7 |
| 14 | + reg5FIFOEnableBit = 1 << 6 |
| 15 | + reg1NormalBits = 0b1111 |
| 16 | +) |
| 17 | + |
| 18 | +// Register addresses. Comments from https://github.com/adafruit/Adafruit_L3GD20_U/blob/master/Adafruit_L3GD20_U.cpp |
| 19 | +const ( |
| 20 | + // The Slave ADdress (SAD) associated with the L3GD20 is 110101xb |
| 21 | + I2CAddr = 0b1101011 |
| 22 | + // The SDO pin can be used to modify the less significant bit of the device address. |
| 23 | + I2CAddrSDOLow = 0b1101010 |
| 24 | + WHOAMI uint8 = 0x0F |
| 25 | + // CTRL_REG1 (0x20) |
| 26 | + // ==================================================================== |
| 27 | + // BIT Symbol Description Default |
| 28 | + // --- ------ --------------------------------------------- ------- |
| 29 | + // 7-6 DR1/0 Output data rate 00 |
| 30 | + // 5-4 BW1/0 Bandwidth selection 00 |
| 31 | + // 3 PD 0 = Power-down mode, 1 = normal/sleep mode 0 |
| 32 | + // 2 ZEN Z-axis enable (0 = disabled, 1 = enabled) 1 |
| 33 | + // 1 YEN Y-axis enable (0 = disabled, 1 = enabled) 1 |
| 34 | + // 0 XEN X-axis enable (0 = disabled, 1 = enabled) 1 |
| 35 | + CTRL_REG1 uint8 = 0x20 |
| 36 | + // Set CTRL_REG2 (0x21) |
| 37 | + // ==================================================================== |
| 38 | + // BIT Symbol Description Default |
| 39 | + // --- ------ --------------------------------------------- ------- |
| 40 | + // 5-4 HPM1/0 High-pass filter mode selection 00 |
| 41 | + // 3-0 HPCF3..0 High-pass filter cutoff frequency selection 0000 |
| 42 | + CTRL_REG2 uint8 = 0x21 |
| 43 | + // CTRL_REG3 (0x22) |
| 44 | + // ==================================================================== |
| 45 | + // BIT Symbol Description Default |
| 46 | + // --- ------ --------------------------------------------- ------- |
| 47 | + // 7 I1_Int1 Interrupt enable on INT1 (0=disable,1=enable) 0 |
| 48 | + // 6 I1_Boot Boot status on INT1 (0=disable,1=enable) 0 |
| 49 | + // 5 H-Lactive Interrupt active config on INT1 (0=high,1=low) 0 |
| 50 | + // 4 PP_OD Push-Pull/Open-Drain (0=PP, 1=OD) 0 |
| 51 | + // 3 I2_DRDY Data ready on DRDY/INT2 (0=disable,1=enable) 0 |
| 52 | + // 2 I2_WTM FIFO wtrmrk int on DRDY/INT2 (0=dsbl,1=enbl) 0 |
| 53 | + // 1 I2_ORun FIFO overrun int on DRDY/INT2 (0=dsbl,1=enbl) 0 |
| 54 | + // 0 I2_Empty FIFI empty int on DRDY/INT2 (0=dsbl,1=enbl) 0 |
| 55 | + CTRL_REG3 uint8 = 0x22 |
| 56 | + // CTRL_REG4 (0x23) |
| 57 | + // ==================================================================== |
| 58 | + // BIT Symbol Description Default |
| 59 | + // --- ------ --------------------------------------------- ------- |
| 60 | + // 7 BDU Block Data Update (0=continuous, 1=LSB/MSB) 0 |
| 61 | + // 6 BLE Big/Little-Endian (0=Data LSB, 1=Data MSB) 0 |
| 62 | + // 5-4 FS1/0 Full scale selection 00 |
| 63 | + // 00 = 250 dps |
| 64 | + // 01 = 500 dps |
| 65 | + // 10 = 2000 dps |
| 66 | + // 11 = 2000 dps |
| 67 | + // 0 SIM SPI Mode (0=4-wire, 1=3-wire) 0 |
| 68 | + CTRL_REG4 uint8 = 0x23 |
| 69 | + // CTRL_REG5 (0x24) |
| 70 | + // ==================================================================== |
| 71 | + // BIT Symbol Description Default |
| 72 | + // --- ------ --------------------------------------------- ------- |
| 73 | + // 7 BOOT Reboot memory content (0=normal, 1=reboot) 0 |
| 74 | + // 6 FIFO_EN FIFO enable (0=FIFO disable, 1=enable) 0 |
| 75 | + // 4 HPen High-pass filter enable (0=disable,1=enable) 0 |
| 76 | + // 3-2 INT1_SEL INT1 Selection config 00 |
| 77 | + // 1-0 OUT_SEL Out selection config 00 |
| 78 | + CTRL_REG5 uint8 = 0x24 |
| 79 | + REFERENCE uint8 = 0x25 |
| 80 | + OUT_TEMP uint8 = 0x26 |
| 81 | + STATUS_REG uint8 = 0x27 |
| 82 | + OUT_X_L uint8 = 0x28 |
| 83 | + OUT_X_H uint8 = 0x29 |
| 84 | + OUT_Y_L uint8 = 0x2A |
| 85 | + OUT_Y_H uint8 = 0x2B |
| 86 | + OUT_Z_L uint8 = 0x2C |
| 87 | + OUT_Z_H uint8 = 0x2D |
| 88 | + FIFO_CTRL_REG uint8 = 0x2E |
| 89 | + FIFO_SRC_REG uint8 = 0x2F |
| 90 | + INT1_CFG uint8 = 0x30 |
| 91 | + INT1_SRC uint8 = 0x31 |
| 92 | + INT1_TSH_XH uint8 = 0x32 |
| 93 | + INT1_TSH_XL uint8 = 0x33 |
| 94 | + INT1_TSH_YH uint8 = 0x34 |
| 95 | + INT1_TSH_YL uint8 = 0x35 |
| 96 | + INT1_TSH_ZH uint8 = 0x36 |
| 97 | + INT1_TSH_ZL uint8 = 0x37 |
| 98 | + INT1_DURATION uint8 = 0x38 |
| 99 | +) |
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