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[Xtensa] Correct lowering BR_CC with FP operands.
Remove register class for boolean operands, because it is only suitable for FP compare operations and may lead to problems in other cases. Disable load width reduction, because for IRAM memory it may cause exceptions.
1 parent a46e1a6 commit 3f5d05b

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6 files changed

+90
-84
lines changed

6 files changed

+90
-84
lines changed

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp‎

Lines changed: 29 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -335,10 +335,6 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
335335

336336
// Compute derived properties from the register classes
337337
computeRegisterProperties(STI.getRegisterInfo());
338-
339-
if (Subtarget.hasBoolean()) {
340-
addRegisterClass(MVT::i1, &Xtensa::BRRegClass);
341-
}
342338
}
343339

344340
/// If a physical register, this returns the register that receives the
@@ -1084,73 +1080,6 @@ XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
10841080
DL, MVT::Other, RetOps);
10851081
}
10861082

1087-
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, SDLoc dl,
1088-
SelectionDAG &DAG, int &br_code) {
1089-
// Minor optimization: if LHS is a constant, swap operands, then the
1090-
// constant can be folded into comparison.
1091-
if (LHS.getOpcode() == ISD::Constant)
1092-
std::swap(LHS, RHS);
1093-
int cmp_code = 0;
1094-
1095-
switch (CC) {
1096-
default:
1097-
llvm_unreachable("Invalid condition!");
1098-
break;
1099-
case ISD::SETUNE:
1100-
br_code = XtensaISD::BR_CC_F;
1101-
cmp_code = XtensaISD::CMPOEQ;
1102-
break;
1103-
case ISD::SETUO:
1104-
br_code = XtensaISD::BR_CC_T;
1105-
cmp_code = XtensaISD::CMPUO;
1106-
break;
1107-
case ISD::SETO:
1108-
br_code = XtensaISD::BR_CC_F;
1109-
cmp_code = XtensaISD::CMPUO;
1110-
break;
1111-
case ISD::SETUEQ:
1112-
br_code = XtensaISD::BR_CC_T;
1113-
cmp_code = XtensaISD::CMPUEQ;
1114-
break;
1115-
case ISD::SETULE:
1116-
br_code = XtensaISD::BR_CC_T;
1117-
cmp_code = XtensaISD::CMPULE;
1118-
break;
1119-
case ISD::SETULT:
1120-
br_code = XtensaISD::BR_CC_T;
1121-
cmp_code = XtensaISD::CMPULT;
1122-
break;
1123-
case ISD::SETEQ:
1124-
case ISD::SETOEQ:
1125-
br_code = XtensaISD::BR_CC_T;
1126-
cmp_code = XtensaISD::CMPOEQ;
1127-
break;
1128-
case ISD::SETNE:
1129-
br_code = XtensaISD::BR_CC_F;
1130-
cmp_code = XtensaISD::CMPOEQ;
1131-
break;
1132-
case ISD::SETLE:
1133-
case ISD::SETOLE:
1134-
br_code = XtensaISD::BR_CC_T;
1135-
cmp_code = XtensaISD::CMPOLE;
1136-
break;
1137-
case ISD::SETLT:
1138-
case ISD::SETOLT:
1139-
br_code = XtensaISD::BR_CC_T;
1140-
cmp_code = XtensaISD::CMPOLT;
1141-
break;
1142-
case ISD::SETGE:
1143-
br_code = XtensaISD::BR_CC_F;
1144-
cmp_code = XtensaISD::CMPOLT;
1145-
break;
1146-
case ISD::SETGT:
1147-
br_code = XtensaISD::BR_CC_F;
1148-
cmp_code = XtensaISD::CMPOLE;
1149-
break;
1150-
}
1151-
return DAG.getNode(cmp_code, dl, MVT::i1, LHS, RHS);
1152-
}
1153-
11541083
SDValue XtensaTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
11551084
SDValue Chain = Op.getOperand(0);
11561085
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
@@ -1160,9 +1089,9 @@ SDValue XtensaTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
11601089
SDLoc DL(Op);
11611090

11621091
if (LHS.getValueType() == MVT::f32) {
1163-
int br_code;
1164-
SDValue Flag = EmitCMP(LHS, RHS, CC, DL, DAG, br_code);
1165-
return DAG.getNode(br_code, DL, Op.getValueType(), Chain, Flag, Dest);
1092+
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
1093+
return DAG.getNode(XtensaISD::BR_CC_FP, DL, Op.getValueType(), Chain,
1094+
TargetCC, LHS, RHS, Dest);
11661095
} else {
11671096
llvm_unreachable("invalid BR_CC to lower");
11681097
}
@@ -1765,8 +1694,9 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
17651694
OPCODE(SELECT);
17661695
OPCODE(SELECT_CC);
17671696
OPCODE(SELECT_CC_FP);
1768-
OPCODE(BR_CC_T);
1769-
OPCODE(BR_CC_F);
1697+
OPCODE(BR_T);
1698+
OPCODE(BR_F);
1699+
OPCODE(BR_CC_FP);
17701700
OPCODE(BR_JT);
17711701
OPCODE(CMPUO);
17721702
OPCODE(CMPUEQ);
@@ -1943,7 +1873,7 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
19431873
int CmpKind = 0;
19441874
MachineFunction *MF = BB->getParent();
19451875
MachineRegisterInfo &RegInfo = MF->getRegInfo();
1946-
const TargetRegisterClass *RC = getRegClassFor(MVT::i1);
1876+
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
19471877
unsigned b = RegInfo.createVirtualRegister(RC);
19481878
GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
19491879
BuildMI(BB, DL, TII.get(CmpKind), b)
@@ -2997,6 +2927,28 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
29972927
return MBB;
29982928
}
29992929

2930+
case Xtensa::BRCC_FP: {
2931+
MachineOperand &Cond = MI.getOperand(0);
2932+
MachineOperand &LHS = MI.getOperand(1);
2933+
MachineOperand &RHS = MI.getOperand(2);
2934+
MachineBasicBlock *TargetBB = MI.getOperand(3).getMBB();
2935+
int BrKind = 0;
2936+
int CmpKind = 0;
2937+
MachineFunction *MF = MBB->getParent();
2938+
MachineRegisterInfo &RegInfo = MF->getRegInfo();
2939+
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
2940+
2941+
unsigned RegB = RegInfo.createVirtualRegister(RC);
2942+
GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
2943+
BuildMI(*MBB, MI, DL, TII.get(CmpKind), RegB)
2944+
.addReg(LHS.getReg())
2945+
.addReg(RHS.getReg());
2946+
BuildMI(*MBB, MI, DL, TII.get(BrKind)).addReg(RegB).addMBB(TargetBB);
2947+
2948+
MI.eraseFromParent();
2949+
return MBB;
2950+
}
2951+
30002952
case Xtensa::SELECT_CC_FP_FP:
30012953
case Xtensa::SELECT_CC_FP_INT:
30022954
case Xtensa::SELECT_CC_INT_FP:

‎llvm/lib/Target/Xtensa/XtensaISelLowering.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,11 @@ namespace XtensaISD {
2525
enum {
2626
FIRST_NUMBER = ISD::BUILTIN_OP_END,
2727

28-
BR_CC_T,
29-
BR_CC_F,
28+
BR_T,
29+
BR_F,
30+
31+
//Conditional branch with FP operands
32+
BR_CC_FP,
3033

3134
BR_JT,
3235

@@ -163,6 +166,11 @@ class XtensaTargetLowering : public TargetLowering {
163166
return true;
164167
}
165168

169+
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
170+
EVT NewVT) const override {
171+
return false;
172+
}
173+
166174
MachineBasicBlock *
167175
EmitInstrWithCustomInserter(MachineInstr &MI,
168176
MachineBasicBlock *BB) const override;

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -937,8 +937,8 @@ def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t),
937937
def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t),
938938
"xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
939939

940-
def : Pat<(Xtensa_brcc_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>;
941-
def : Pat<(Xtensa_brcc_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>;
940+
def : Pat<(Xtensa_br_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>;
941+
def : Pat<(Xtensa_br_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>;
942942

943943
//===----------------------------------------------------------------------===//
944944
// Floating-Point Instructions
@@ -1236,6 +1236,14 @@ let usesCustomInserter = 1 in {
12361236
"!select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond",
12371237
[(set FPR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, FPR:$t, FPR:$f, imm:$cond))]>;
12381238
}
1239+
1240+
// FP brcc pesudo operation
1241+
let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1242+
def BRCC_FP : Pseudo<(outs), (ins i32imm:$cond, FPR:$lhs, FPR:$rhs, brtarget:$target),
1243+
"!brcc_fp $cond, $lhs, $rhs, $target",
1244+
[(Xtensa_brcc_fp imm:$cond, FPR:$lhs, FPR:$rhs, bb:$target)]>;
1245+
}
1246+
12391247
//===----------------------------------------------------------------------===//
12401248
// Loop Instructions
12411249
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Xtensa/XtensaOperators.td‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,8 @@ def SDT_XtensaSelectCC : SDTypeProfile<1, 5,
2525
SDTCisVT<5, i32>]>;
2626

2727
def SDT_XtensaMOVSP : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>;
28-
def SDT_XtensaBrCC : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>;
28+
def SDT_XtensaBrBool : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>;
29+
def SDT_XtensaBrCCFP : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, SDTCisVT<3, OtherVT>]>;
2930
def SDT_XtensaCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>;
3031
def SDT_XtensaMADD : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>;
3132
def SDT_XtensaMOVS : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>;
@@ -72,9 +73,11 @@ def Xtensa_select_cc_fp: SDNode<"XtensaISD::SELECT_CC_FP", SDT_XtensaSelectCCFP,
7273
def Xtensa_movsp: SDNode<"XtensaISD::MOVSP", SDT_XtensaMOVSP,
7374
[SDNPInGlue]>;
7475

75-
def Xtensa_brcc_t : SDNode<"XtensaISD::BR_CC_T", SDT_XtensaBrCC,
76+
def Xtensa_br_t : SDNode<"XtensaISD::BR_T", SDT_XtensaBrBool,
7677
[SDNPHasChain, SDNPInGlue]>;
77-
def Xtensa_brcc_f : SDNode<"XtensaISD::BR_CC_F", SDT_XtensaBrCC,
78+
def Xtensa_br_f : SDNode<"XtensaISD::BR_F", SDT_XtensaBrBool,
79+
[SDNPHasChain, SDNPInGlue]>;
80+
def Xtensa_brcc_fp : SDNode<"XtensaISD::BR_CC_FP", SDT_XtensaBrCCFP,
7881
[SDNPHasChain, SDNPInGlue]>;
7982

8083
def Xtensa_cmpoeq : SDNode<"XtensaISD::CMPOEQ", SDT_XtensaCmp, [SDNPOutGlue]>;

‎llvm/test/CodeGen/Xtensa/xtensa-fcmp.ll‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s
2+
3+
define void @test_fcmp(i32 %x.coerce) {
4+
; CHECK-LABEL: @test_fcmp
5+
entry:
6+
%0 = bitcast i32 %x.coerce to float
7+
%cmp = fcmp oeq float %0, 0x7FF0000000000000
8+
br i1 %cmp, label %if.then, label %if.else
9+
; CHECK: oeq.s b0, f9, f8
10+
; CHECK: bf b0, .LBB0_2
11+
12+
if.then: ; preds = %entry
13+
unreachable
14+
15+
if.else: ; preds = %entry
16+
unreachable
17+
}
18+

‎llvm/test/CodeGen/Xtensa/xtensa-icmp.ll‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
; RUN: llc -O1 -mtriple=xtensa -mcpu=esp32 %s -o - | FileCheck %s
2+
3+
define i8 @test_bit(i8 %a) {
4+
; CHECK-LABEL: @test_bit
5+
%b = and i8 %a, 16
6+
%bool = icmp eq i8 %b, 0
7+
br i1 %bool, label %true, label %false
8+
; CHECK: movi.n a8, 16
9+
; CHECK: and a8, a2, a8
10+
; CHECK: bnez a8, .LBB0_2
11+
12+
true:
13+
ret i8 1
14+
15+
false:
16+
ret i8 0
17+
}

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