[Xtensa] Support 'f' Inline Assembly Constraint

This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register.

This patch adds support in both the clang frontend, and LLVM itself.

Author: andreisfr

clang/lib/Basic/Targets/Xtensa.h

@@ -82,6 +82,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
     default:
       return false;
     case 'a':
+    case 'f':
       Info.setAllowsRegister();
       return true;
     }

clang/test/CodeGen/xtensa-inline-asm.c

@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple xtensa -O1 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+// Test Xtensa specific inline assembly constraints.
+
+float f;
+void test_f() {
+// CHECK-LABEL: define dso_local void @test_f() local_unnamed_addr #0 {
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
+// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
+  asm volatile ("" :: "f"(f));
+}
+

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

@@ -376,6 +376,7 @@ XtensaTargetLowering::getConstraintType(StringRef Constraint) const {
     switch (Constraint[0]) {
     case 'a':
     case 'd':
+    case 'f':
     case 'r':
       return C_RegisterClass;
 
@@ -396,6 +397,8 @@ XtensaTargetLowering::getSingleConstraintMatchWeight(
   if (CallOperandVal == NULL)
     return CW_Default;
 
+  Type *type = CallOperandVal->getType();
+
   // Look at the constraint type.
   switch (*constraint) {
   default:
@@ -405,9 +408,14 @@ XtensaTargetLowering::getSingleConstraintMatchWeight(
   case 'a':
   case 'd':
   case 'r':
-    if (CallOperandVal->getType()->isIntegerTy())
+    if (type->isIntegerTy())
+      weight = CW_Register;
+    break;
+  case 'f':
+    if (type->isFloatingPointTy())
       weight = CW_Register;
     break;
+
   }
   return weight;
 }
@@ -424,6 +432,9 @@ XtensaTargetLowering::getRegForInlineAsmConstraint(
     case 'd': // Data register (equivalent to 'r')
     case 'r': // General-purpose register
       return std::make_pair(0U, &Xtensa::ARRegClass);
+    case 'f': // Floating-point register
+      if (Subtarget.hasSingleFloat())
+        return std::make_pair(0U, &Xtensa::FPRRegClass);
     }
   }
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);

llvm/test/CodeGen/Xtensa/inline-asm-constraints.ll

@@ -0,0 +1,23 @@
+; RUN: llc -mtriple=xtensa  -mcpu=esp32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=Xtensa %s
+
+
+@gf = external global float
+
+define float @constraint_f_float(float %a) nounwind {
+; Xtensa-LABEL: constraint_f_float:
+; Xtensa:       # %bb.0:
+; Xtensa-NEXT:    entry a1, 32
+; Xtensa-NEXT:    wfr f8, a2
+; Xtensa-NEXT:    l32r a8, .LCPI0_0
+; Xtensa-NEXT:    lsi f9, a8, 0
+; Xtensa-NEXT:    #APP
+; Xtensa-NEXT:    add.s f8, f8, f9
+; Xtensa-NEXT:    #NO_APP
+; Xtensa-NEXT:    rfr a2, f8
+; Xtensa-NEXT:    retw
+  %1 = load float, float* @gf
+  %2 = tail call float asm "add.s $0, $1, $2", "=f,f,f"(float %a, float %1)
+  ret float %2
+}
+

llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll

@@ -0,0 +1,8 @@
+; RUN: not llc -mtriple=xtensa -mcpu=generic < %s 2>&1 | FileCheck %s
+
+define void @constraint_f() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'f'
+  tail call void asm "add.s f0, f1, $0", "f"(float 0.0)
+  ret void
+}
+