[Xtensa] Correction of the ESP32-S2 target.

The ESP32-S2 chip includes Xtensa ISA extension which
helps to work with GPIO, so we add instructions description
and test. Add MEMCTL feature to ESP32-S@ target. Implement
Xtensa illegal instructions with tests.

Author: andreisfr

llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

@@ -350,6 +350,8 @@ struct XtensaOperand : public MCParsedAsmOperand {
 
   bool isseimm7_22() const { return isImm(7, 22); }
 
+  bool isSelect_256() const { return isImm(0, 255); }
+
   /// getStartLoc - Gets location of the first token of this operand
   SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Gets location of the last token of this operand
@@ -621,6 +623,9 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_Invalidseimm7_22:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected immediate in range [7, 22]");
+  case Match_InvalidSelect_256:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected immediate in range [0, 255]");
   }
 
   report_fatal_error("Unknown match type detected!");

llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

@@ -568,6 +568,14 @@ static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm,
+                                            int64_t Address,
+                                            const void *Decoder) {
+  assert(isUInt<8>(Imm) && "Invalid immediate");
+  Inst.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 static int64_t TableB4const[16] = {-1, 1,  2,  3,  4,  5,  6,   7,
                                    8,  10, 12, 16, 32, 64, 128, 256};
 static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm,

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

@@ -436,3 +436,14 @@ void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum,
   } else
     printOperand(MI, OpNum, O);
 }
+
+void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum,
+                                                   raw_ostream &O) {
+  if (MI->getOperand(OpNum).isImm()) {
+    int64_t Value = MI->getOperand(OpNum).getImm();
+    assert((Value >= 0 && Value <= 255) &&
+           "Invalid argument, value must be in range [0,255]");
+    O << Value;
+  } else
+    printOperand(MI, OpNum, O);
+}

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h

@@ -73,6 +73,7 @@ class XtensaInstPrinter : public MCInstPrinter {
   void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+  void printSelect_256_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
 };
 } // end namespace llvm
 

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp

@@ -142,6 +142,11 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
   uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
+
+  uint32_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
+                                SmallVectorImpl<MCFixup> &Fixups,
+                                const MCSubtargetInfo &STI) const;
+
 };
 } // namespace
 
@@ -593,4 +598,16 @@ XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
   return res;
 }
 
+uint32_t
+XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  uint32_t Res = static_cast<uint32_t>(MO.getImm());
+
+  assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!");
+
+  return Res;
+}
+
 #include "XtensaGenMCCodeEmitter.inc"

llvm/lib/Target/Xtensa/Xtensa.td

@@ -153,6 +153,11 @@ def FeatureMiscSR            : SubtargetFeature<"miscsr", "HasMiscSR", "true",
 def HasMiscSR                : Predicate<"Subtarget->hasMiscSR()">,
                                           AssemblerPredicate<(all_of FeatureMiscSR)>;
 
+def FeatureESP32S2Ops        : SubtargetFeature<"esp32s2", "HasESP32S2Ops", "true",
+                                                "Support Xtensa esp32-s2 ISA extension">;
+def HasESP32S2Ops            : Predicate<"Subtarget->hasESP32S2Ops()">,
+                                          AssemblerPredicate<(all_of FeatureESP32S2Ops)>;
+
 //===----------------------------------------------------------------------===//
 // Xtensa supported processors.
 //===----------------------------------------------------------------------===//
@@ -170,8 +175,8 @@ def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul32, FeatureExtended
                        FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>;
 
 def : Proc<"esp32-s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul32, FeatureMul32High, FeatureTHREADPTR, FeatureDiv32,
-                        FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector,
-						FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR]>;
+                        FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt,
+                        FeatureRelocatableVector,	FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureESP32S2Ops]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

@@ -1450,6 +1450,27 @@ def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
   let r = 0x6;
 }
 
+//===----------------------------------------------------------------------===//
+// Illegal instructions
+//===----------------------------------------------------------------------===//
+
+let isBarrier = 1, isTerminator = 1 in {
+  def ILL : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),
+                      "ill", []> {
+    let m = 0x0;
+    let n = 0x0;
+    let r = 0;
+    let s = 0;
+  }
+
+  def ILL_N : RRRN_Inst<0x0C, (outs), (ins),
+                       "ill.n", []>, Requires<[HasDensity]> {
+    let r = 0xf;
+    let s = 0x0;
+    let t = 0x6;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Atomic patterns
 //===----------------------------------------------------------------------===//
@@ -1584,6 +1605,40 @@ let usesCustomInserter = 1, Predicates = [HasS32C1I] in {
                                     [(set AR:$dst, (atomic_load_umax_32 AR:$ptr, AR:$arg))]>;	
 }
 
+//===----------------------------------------------------------------------===//
+// Xtensa ESP32S2 Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasESP32S2Ops] in {
+  def WR_MASK_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins AR:$s, AR:$t),
+                                 "wr_mask_gpio_out\t$s, $t", []> {
+    let r = 0x2;
+  }
+
+  def SET_BIT_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins select_256:$imm),
+                                 "set_bit_gpio_out\t$imm", []> {
+    bits<8> imm;
+
+    let r = 0x1;
+    let s = imm{7-4};
+    let t = imm{3-0};
+  }
+
+  def CLR_BIT_GPIO_OUT : RRR_Inst<0x0, 0x06, 0x0, (outs), (ins select_256:$imm),
+                                 "clr_bit_gpio_out\t$imm", []> {
+    bits<8> imm;
+
+    let r = 0x0;
+    let s = imm{7-4};
+    let t = imm{3-0};
+  }
+
+  def GET_GPIO_IN : RRR_Inst<0x0, 0x06, 0x0, (outs AR:$t), (ins),
+                            "get_gpio_in\t$t", []> {
+    let r = 0x3;
+    let s = 0x0;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // DSP Instructions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaOperands.td

@@ -175,6 +175,13 @@ def seimm7_22: Immediate<i32, [{ return Imm >= 7 && Imm <= 22; }], "Seimm7_22_As
   let DecoderMethod = "decodeSeimm7_22Operand";
 }
 
+// select_256 predicate - Immediate in the range [0,255]
+def Select_256_AsmOperand: ImmAsmOperand<"Select_256">;
+def select_256: Immediate<i32, [{ return Imm >= 0 && Imm <= 255; }], "Select_256_AsmOperand"> {
+  let EncoderMethod = "getSelect_256OpValue";
+  let DecoderMethod = "decodeSelect_256Operand";
+}
+
 //===----------------------------------------------------------------------===//
 // Memory address operands
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaSubtarget.cpp

@@ -59,6 +59,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasPRID = false;
   HasRegionProtection = false;
   HasMiscSR = false;
+  HasESP32S2Ops = false;
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);

llvm/lib/Target/Xtensa/XtensaSubtarget.h

@@ -119,6 +119,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   // Enable Xtensa Miscellaneous Special Reigsiters option
   bool HasMiscSR;
 
+  // Enable Xtensa esp32-s2 ISA extension
+  bool HasESP32S2Ops;
+
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
 public:
@@ -190,6 +193,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
 
   bool hasMiscSR() const { return HasMiscSR; }
 
+  bool hasESP32S2Ops() const { return HasESP32S2Ops; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 };