SPI3w seems to work fine

Author: soypat

rp2-pio/examples/ws2812/main.go

@@ -12,7 +12,7 @@ import (
 func main() {
 	const ws2812Pin = machine.GP16
 	sm, _ := pio.PIO0.ClaimStateMachine()
-	ws, err := piolib.NewWS2812(sm, ws2812Pin)
+	ws, err := piolib.NewWS2812(sm, ws2812Pin, 400_000)
 	if err != nil {
 		panic(err.Error())
 	}

rp2-pio/piolib/all_generate.go

@@ -10,8 +10,9 @@ import (
 const timeoutRetries = math.MaxUint16 * 8
 
 var (
-	errTimeout = errors.New("piolib:timeout")
-	errBusy    = errors.New("piolib:busy")
+	errTimeout           = errors.New("piolib:timeout")
+	errContentionTimeout = errors.New("piolib:contention timeout")
+	errBusy              = errors.New("piolib:busy")
 
 	errDMAUnavail = errors.New("piolib:DMA channel unavailable")
 )
@@ -26,11 +27,6 @@ func gosched() {
 	runtime.Gosched()
 }
 
-type deadliner struct {
-	// timeout is a bitshift value for the timeout.
-	timeout uint8
-}
-
 type deadline struct {
 	t time.Time
 }
@@ -42,16 +38,23 @@ func (dl deadline) expired() bool {
 	return time.Since(dl.t) > 0
 }
 
+type deadliner struct {
+	// timeout is a bitshift value for the timeout.
+	timeout uint8
+}
+
 func (ch deadliner) newDeadline() deadline {
 	var t time.Time
 	if ch.timeout != 0 {
-		t = time.Now().Add(time.Duration(1 << ch.timeout))
+		calc := time.Duration(1 << ch.timeout)
+		t = time.Now().Add(calc)
 	}
 	return deadline{t: t}
 }
 
 func (ch *deadliner) setTimeout(timeout time.Duration) {
 	if timeout <= 0 {
+		ch.timeout = 0
 		return // No timeout.
 	}
 	for i := uint8(0); i < 64; i++ {

rp2-pio/piolib/dma.go

@@ -86,6 +86,12 @@ func (ch dmaChannel) Init(cfg dmaChannelConfig) {
 	ch.HW().CTRL_TRIG.Set(cfg.CTRL)
 }
 
+// CurrentConfig copies the actual configuration of the DMA channel.
+func (ch dmaChannel) CurrentConfig() dmaChannelConfig {
+	ch.mustValid()
+	return dmaChannelConfig{CTRL: ch.HW().CTRL_TRIG.Get()}
+}
+
 func (ch dmaChannel) mustValid() {
 	if !ch.IsValid() {
 		panic("use of uninitialized DMA channel")
@@ -165,64 +171,135 @@ const (
 
 // Push32 writes each element of src slice into the memory location at dst.
 func (ch dmaChannel) Push32(dst *uint32, src []uint32, dreq uint32) error {
+	return dmaPush(ch, dst, src, dreq)
+}
+
+// Push16 writes each element of src slice into the memory location at dst.
+func (ch dmaChannel) Push16(dst *uint16, src []uint16, dreq uint32) error {
+	return dmaPush(ch, dst, src, dreq)
+}
+
+// Push8 writes each element of src slice into the memory location at dst.
+func (ch dmaChannel) Push8(dst *byte, src []byte, dreq uint32) error {
+	return dmaPush(ch, dst, src, dreq)
+}
+
+// Push32 writes each element of src slice into the memory location at dst.
+func dmaPush[T uint8 | uint16 | uint32](ch dmaChannel, dst *T, src []T, dreq uint32) error {
 	hw := ch.HW()
+	hw.CTRL_TRIG.ClearBits(rp.DMA_CH0_CTRL_TRIG_EN_Msk)
 	srcPtr := uint32(uintptr(unsafe.Pointer(&src[0])))
 	dstPtr := uint32(uintptr(unsafe.Pointer(dst)))
 	hw.READ_ADDR.Set(srcPtr)
 	hw.WRITE_ADDR.Set(dstPtr)
 	hw.TRANS_COUNT.Set(uint32(len(src)))
+
 	// memfence
-	var cc dmaChannelConfig
-	cc.CTRL = hw.CTRL_TRIG.Get()
+
+	cc := ch.CurrentConfig()
 	cc.setTREQ_SEL(dreq)
-	cc.setTransferDataSize(dmaTxSize32)
+	cc.setTransferDataSize(dmaSize[T]())
 	cc.setChainTo(ch.idx)
 	cc.setReadIncrement(true)
 	cc.setWriteIncrement(false)
 	cc.setEnable(true)
 
+	deadline := ch.dl.newDeadline()
+	// If currently busy we wait.
+	for ch.busy() {
+		if deadline.expired() {
+			return errContentionTimeout
+		}
+		gosched()
+	}
+
+	// We begin our DMA transfer here!
 	hw.CTRL_TRIG.Set(cc.CTRL)
 
-	deadline := ch.dl.newDeadline()
+	deadline = ch.dl.newDeadline()
 	for ch.busy() {
 		if deadline.expired() {
+			ch.abort()
 			return errTimeout
 		}
 		gosched()
 	}
+	hw.CTRL_TRIG.ClearBits(rp.DMA_CH0_CTRL_TRIG_EN_Msk)
 	return nil
 }
 
 // Pull32 reads the memory location at src into dst slice, incrementing dst pointer but not src.
 func (ch dmaChannel) Pull32(dst []uint32, src *uint32, dreq uint32) error {
+	return dmaPull(ch, dst, src, dreq)
+}
+
+// Pull16 reads the memory location at src into dst slice, incrementing dst pointer but not src.
+func (ch dmaChannel) Pull16(dst []uint16, src *uint16, dreq uint32) error {
+	return dmaPull(ch, dst, src, dreq)
+}
+
+// Pull8 reads the memory location at src into dst slice, incrementing dst pointer but not src.
+func (ch dmaChannel) Pull8(dst []byte, src *byte, dreq uint32) error {
+	return dmaPull(ch, dst, src, dreq)
+}
+
+// Pull32 reads the memory location at src into dst slice, incrementing dst pointer but not src.
+func dmaPull[T uint8 | uint16 | uint32](ch dmaChannel, dst []T, src *T, dreq uint32) error {
 	hw := ch.HW()
+	hw.CTRL_TRIG.ClearBits(rp.DMA_CH0_CTRL_TRIG_EN_Msk)
 	srcPtr := uint32(uintptr(unsafe.Pointer(src)))
 	dstPtr := uint32(uintptr(unsafe.Pointer(&dst[0])))
 	hw.READ_ADDR.Set(srcPtr)
 	hw.WRITE_ADDR.Set(dstPtr)
 	hw.TRANS_COUNT.Set(uint32(len(dst)))
+
 	// memfence
-	var cc dmaChannelConfig
-	cc.CTRL = hw.CTRL_TRIG.Get()
+
+	cc := ch.CurrentConfig()
 	cc.setTREQ_SEL(dreq)
-	cc.setTransferDataSize(dmaTxSize32)
+	cc.setTransferDataSize(dmaSize[T]())
 	cc.setChainTo(ch.idx)
 	cc.setReadIncrement(false)
 	cc.setWriteIncrement(true)
 	cc.setEnable(true)
 
+	// If currently busy we wait.
+	deadline := ch.dl.newDeadline()
+	for ch.busy() {
+		if deadline.expired() {
+			return errContentionTimeout
+		}
+		gosched()
+	}
+
+	// We begin our DMA transfer here!
 	hw.CTRL_TRIG.Set(cc.CTRL)
 
-	deadline := ch.dl.newDeadline()
+	deadline = ch.dl.newDeadline()
 	for ch.busy() {
 		if deadline.expired() {
+			ch.abort()
 			return errTimeout
 		}
 		gosched()
 	}
 	return nil
 }
 
+func dmaSize[T uint8 | uint16 | uint32]() dmaTxSize {
+	var a T
+	switch unsafe.Sizeof(a) {
+	case 1:
+		return dmaTxSize8
+	case 2:
+		return dmaTxSize16
+	case 4:
+		return dmaTxSize32
+	default:
+		panic("invalid DMA transfer size")
+	}
+}
+
 // abort aborts the current transfer sequence on the channel and blocks until
 // all in-flight transfers have been flushed through the address and data FIFOs.
 // After this, it is safe to restart the channel.
@@ -234,13 +311,14 @@ func (ch dmaChannel) abort() {
 	// Until this point, it is unsafe to restart the channel.
 	chMask := uint32(1 << ch.idx)
 	rp.DMA.CHAN_ABORT.Set(chMask)
-	retries := timeoutRetries
-	for rp.DMA.CHAN_ABORT.Get()&chMask != 0 && retries > 0 {
+
+	deadline := ch.dl.newDeadline()
+	for rp.DMA.CHAN_ABORT.Get()&chMask != 0 {
+		if deadline.expired() {
+			println("DMA abort timeout")
+			break
+		}
 		gosched()
-		retries--
-	}
-	if retries == 0 {
-		println("DMA abort timeout")
 	}
 }
 

rp2-pio/piolib/parallel8.go

@@ -5,15 +5,16 @@ package piolib
 import (
 	"errors"
 	"machine"
+	"unsafe"
 
 	pio "github.com/tinygo-org/pio/rp2-pio"
 )
 
 // Parallel8Tx is a 8-wire, only send Parallel implementation.
 type Parallel8Tx struct {
-	sm         pio.StateMachine
-	offset     uint8
-	dmaChannel uint32
+	sm     pio.StateMachine
+	offset uint8
+	dma    dmaChannel
 }
 
 // unused for now.
@@ -57,13 +58,12 @@ func NewParallel8Tx(sm pio.StateMachine, wr, dStart machine.Pin, baud uint32) (*
 	sm.Init(offset, cfg)
 	sm.SetEnabled(true)
 
-	return &Parallel8Tx{sm: sm, dmaChannel: noDMA, offset: offset}, nil
+	return &Parallel8Tx{sm: sm, offset: offset}, nil
 }
 
 func (pl *Parallel8Tx) Write(data []uint8) error {
-	if pl.dmaChannel != noDMA {
-		// pl.dmaWrite(data)
-		return nil
+	if pl.IsDMAEnabled() {
+		return pl.dmaWrite(data)
 	}
 	retries := int8(127)
 	for _, char := range data {
@@ -79,54 +79,48 @@ func (pl *Parallel8Tx) Write(data []uint8) error {
 	return nil
 }
 
-/*
-func (pl *Parallel8Tx) EnableDMA(dmaChan uint32) error {
+func (pl *Parallel8Tx) IsDMAEnabled() bool {
+	return pl.dma.IsValid()
+}
+
+func (pl *Parallel8Tx) EnableDMA(enabled bool) error {
 	if !pl.sm.IsValid() {
 		return errors.New("PIO Statemachine needs initializing") //Not initialized
 	}
-	pl.dmaChannel = dmaChan // DMA enabled
-	if dmaChan == noDMA {
+	dmaAlreadyEnabled := pl.IsDMAEnabled()
+	if !enabled || dmaAlreadyEnabled {
+		if !enabled && dmaAlreadyEnabled {
+			pl.dma.Unclaim()
+			pl.dma = dmaChannel{} // Invalidate DMA channel.
+		}
 		return nil
 	}
-	Pio := pl.sm.PIO()
-	dmaConfig := getDefaultDMAConfig(dmaChan)
-	setTransferDataSize(dmaConfig, DMA_SIZE_8)
-	setBSwap(dmaConfig, false)
-	setDREQ(dmaConfig, uint32(Pio.GetIRQ()))
-	dmaChannelConfigure(dmaChan, dmaConfig, pl.sm.TxReg(), nil, 0, false)
-	return nil
-}
 
-func (pl *Parallel8Tx) dmaWrite(data []byte) {
-	dmaChan := &dmaChannels[pl.dmaChannel]
-	for dmaChan.CTRL_TRIG.Get()&rp.DMA_CH0_CTRL_TRIG_BUSY != 0 {
-		runtime.Gosched()
+	channel, ok := _DMA.ClaimChannel()
+	if !ok {
+		return errDMAUnavail
 	}
 
-	readAddr := uint32(uintptr(unsafe.Pointer(&data[0])))
-	dmaChan.TRANS_COUNT.Set(uint32(len(data)))
-	dmaChan.READ_ADDR.Set(uint32(readAddr))
-	dmaChan.CTRL_TRIG.Set(dmaChan.CTRL_TRIG.Get() | rp.DMA_CH0_CTRL_TRIG_EN)
+	channel.dl = pl.dma.dl // Copy deadline.
+	pl.dma = channel
+	cc := pl.dma.CurrentConfig()
+	cc.setBSwap(false)
+	cc.setTransferDataSize(dmaTxSize8)
+	pl.dma.Init(cc)
+	return nil
+}
 
-	for dmaChan.CTRL_TRIG.Get()&rp.DMA_CH0_CTRL_TRIG_BUSY != 0 {
-		runtime.Gosched()
-	}
-	for !pl.sm.IsTxFIFOEmpty() {
-		runtime.Gosched()
+func (pl *Parallel8Tx) dmaWrite(data []byte) error {
+	dreq := dmaPIO_TxDREQ(pl.sm)
+	err := pl.dma.Push8((*byte)(unsafe.Pointer(&pl.sm.TxReg().Reg)), data, dreq)
+	if err != nil {
+		return err
 	}
-}
 
-func dmaChannelConfigure(channel, config uint32, writeAddr, readAddr *volatile.Register32, transferCount uint32, trigger bool) {
-	regAddr := func(reg *volatile.Register32) uint32 {
-		if reg == nil {
-			return 0
-		}
-		return uint32(uintptr(unsafe.Pointer(reg)))
+	// DMA is done after this point but we still have to wait for
+	// the FIFO to be empty
+	for !pl.sm.IsTxFIFOEmpty() {
+		gosched()
 	}
-	dmaChan := dmaChannels[channel]
-	dmaChan.READ_ADDR.Set(regAddr(readAddr))
-	dmaChan.WRITE_ADDR.Set(regAddr(writeAddr))
-	dmaChan.TRANS_COUNT.Set(transferCount)
-	dmaChan.CTRL_TRIG.Set(config | rp.DMA_CH0_CTRL_TRIG_EN)
+	return nil
 }
-*/