Skip to content

Commit a22ac45

Browse files
committed
spi3w: add Tx32 method
1 parent 6ebf4e2 commit a22ac45

File tree

1 file changed

+43
-7
lines changed

1 file changed

+43
-7
lines changed

rp2-pio/piolib/spi3w.go

Lines changed: 43 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,34 @@ func NewSPI3w(sm pio.StateMachine, dio, clk machine.Pin, baud uint32) (*SPI3w, e
8888
return spiw, nil
8989
}
9090

91+
// Tx32 first writes the data in w to the bus and waits until the data is fully sent
92+
// and then reads len(r) 32 bit words from the bus into r. The data exchange is half duplex.
93+
func (spi *SPI3w) Tx32(w, r []uint32) (err error) {
94+
var writeBits, readBits uint32
95+
if len(w) > 0 {
96+
writeBits = uint32(len(w)*32 - 1)
97+
}
98+
if len(r) > 0 {
99+
readBits = uint32(len(r)*32 - 1)
100+
}
101+
spi.prepTx(readBits, writeBits)
102+
deadline := spi.newDeadline()
103+
if len(w) > 0 {
104+
err = spi.write(w, deadline)
105+
if err != nil {
106+
return err
107+
}
108+
err = spi.waitWrite(deadline)
109+
if err != nil {
110+
return err
111+
}
112+
}
113+
if len(r) == 0 {
114+
return nil
115+
}
116+
return spi.read(r, deadline)
117+
}
118+
91119
func (spi *SPI3w) CmdWrite(cmd uint32, w []uint32) (err error) {
92120
writeBits := (1+len(w))*32 - 1
93121
var readBits uint32
@@ -102,13 +130,9 @@ func (spi *SPI3w) CmdWrite(cmd uint32, w []uint32) (err error) {
102130
if err != nil {
103131
return err
104132
}
105-
// DMA/TxPush is done after this point but we still have to wait for
106-
// the FIFO to be empty.
107-
for !spi.sm.IsTxFIFOEmpty() {
108-
if deadline.expired() {
109-
return errTimeout
110-
}
111-
gosched()
133+
err = spi.waitWrite(deadline)
134+
if err != nil {
135+
return err
112136
}
113137
if spi.statusEn {
114138
err = spi.getStatus(deadline)
@@ -177,6 +201,18 @@ func (spi *SPI3w) write(w []uint32, dl deadline) error {
177201
return nil
178202
}
179203

204+
func (spi *SPI3w) waitWrite(deadline deadline) error {
205+
// DMA/TxPush is done after this point but we still have to wait for
206+
// the FIFO to be empty.
207+
for !spi.sm.IsTxFIFOEmpty() {
208+
if deadline.expired() {
209+
return errTimeout
210+
}
211+
gosched()
212+
}
213+
return nil
214+
}
215+
180216
// LastStatus returns the latest status. This is only valid if EnableStatus(true) was called.
181217
func (spi *SPI3w) LastStatus() uint32 {
182218
return spi.lastStatus

0 commit comments

Comments
 (0)