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firelizzard18firelizzard18
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Working on NXP/Teensy support
1 parent f73d89b commit 05505e2

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11 files changed

+449
-84
lines changed

11 files changed

+449
-84
lines changed

‎src/device/arm/arm.go‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,11 @@ func EnableIRQ(irq uint32) {
174174
NVIC.ISER[irq>>5].Set(1 << (irq & 0x1F))
175175
}
176176

177+
// Disable the given interrupt number.
178+
func DisableIRQ(irq uint32) {
179+
NVIC.ICER[irq>>5].Set(1 << (irq & 0x1F))
180+
}
181+
177182
// Set the priority of the given interrupt number.
178183
// Note that the priority is given as a 0-255 number, where some of the lower
179184
// bits are not implemented by the hardware. For example, to set a low interrupt

‎src/machine/board_teensy36.go‎

Lines changed: 73 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,12 @@ import (
66
"device/nxp"
77
)
88

9-
//go:keep
10-
//go:section .flashconfig
11-
var FlashConfig = [16]byte{
12-
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
13-
0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xF9, 0xFF, 0xFF,
14-
}
9+
// //go:keep
10+
// //go:section .flash_config
11+
// var FlashControl = [16]byte{
12+
// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
13+
// 0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xF9, 0xFF, 0xFF,
14+
// }
1515

1616
func CPUFrequency() uint32 {
1717
return 180000000
@@ -20,20 +20,73 @@ func CPUFrequency() uint32 {
2020
// LED on the Teensy
2121
const LED Pin = 13
2222

23-
var _pinRegisters [64]pinRegisters
24-
25-
func init() {
26-
_pinRegisters[13].Bit = 5
27-
_pinRegisters[13].PCR = &nxp.PORTC.PCR5
28-
_pinRegisters[13].PDOR = nxp.GPIOC.PDOR.Bit(5)
29-
_pinRegisters[13].PSOR = nxp.GPIOC.PSOR.Bit(5)
30-
_pinRegisters[13].PCOR = nxp.GPIOC.PCOR.Bit(5)
31-
_pinRegisters[13].PTOR = nxp.GPIOC.PTOR.Bit(5)
32-
_pinRegisters[13].PDIR = nxp.GPIOC.PDIR.Bit(5)
33-
_pinRegisters[13].PDDR = nxp.GPIOC.PDDR.Bit(5)
23+
var pins = []pin{
24+
// {bit, control register, gpio register bank}
25+
0: {16, &nxp.PORTB.PCR16, nxp.GPIOB},
26+
1: {17, &nxp.PORTB.PCR17, nxp.GPIOB},
27+
2: {0, &nxp.PORTD.PCR0, nxp.GPIOD},
28+
3: {12, &nxp.PORTA.PCR12, nxp.GPIOA},
29+
4: {13, &nxp.PORTA.PCR13, nxp.GPIOA},
30+
5: {7, &nxp.PORTD.PCR7, nxp.GPIOD},
31+
6: {4, &nxp.PORTD.PCR4, nxp.GPIOD},
32+
7: {2, &nxp.PORTD.PCR2, nxp.GPIOD},
33+
8: {3, &nxp.PORTD.PCR3, nxp.GPIOD},
34+
9: {3, &nxp.PORTC.PCR3, nxp.GPIOC},
35+
10: {4, &nxp.PORTC.PCR4, nxp.GPIOC},
36+
11: {6, &nxp.PORTC.PCR6, nxp.GPIOC},
37+
12: {7, &nxp.PORTC.PCR7, nxp.GPIOC},
38+
13: {5, &nxp.PORTC.PCR5, nxp.GPIOC},
39+
14: {1, &nxp.PORTD.PCR1, nxp.GPIOD},
40+
15: {0, &nxp.PORTC.PCR0, nxp.GPIOC},
41+
16: {0, &nxp.PORTB.PCR0, nxp.GPIOB},
42+
17: {1, &nxp.PORTB.PCR1, nxp.GPIOB},
43+
18: {3, &nxp.PORTB.PCR3, nxp.GPIOB},
44+
19: {2, &nxp.PORTB.PCR2, nxp.GPIOB},
45+
20: {5, &nxp.PORTD.PCR5, nxp.GPIOD},
46+
21: {6, &nxp.PORTD.PCR6, nxp.GPIOD},
47+
22: {1, &nxp.PORTC.PCR1, nxp.GPIOC},
48+
23: {2, &nxp.PORTC.PCR2, nxp.GPIOC},
49+
24: {26, &nxp.PORTE.PCR26, nxp.GPIOE},
50+
25: {5, &nxp.PORTA.PCR5, nxp.GPIOA},
51+
26: {14, &nxp.PORTA.PCR14, nxp.GPIOA},
52+
27: {15, &nxp.PORTA.PCR15, nxp.GPIOA},
53+
28: {16, &nxp.PORTA.PCR16, nxp.GPIOA},
54+
29: {18, &nxp.PORTB.PCR18, nxp.GPIOB},
55+
30: {19, &nxp.PORTB.PCR19, nxp.GPIOB},
56+
31: {10, &nxp.PORTB.PCR10, nxp.GPIOB},
57+
32: {11, &nxp.PORTB.PCR11, nxp.GPIOB},
58+
33: {24, &nxp.PORTE.PCR24, nxp.GPIOE},
59+
34: {25, &nxp.PORTE.PCR25, nxp.GPIOE},
60+
35: {8, &nxp.PORTC.PCR8, nxp.GPIOC},
61+
36: {9, &nxp.PORTC.PCR9, nxp.GPIOC},
62+
37: {10, &nxp.PORTC.PCR10, nxp.GPIOC},
63+
38: {11, &nxp.PORTC.PCR11, nxp.GPIOC},
64+
39: {17, &nxp.PORTA.PCR17, nxp.GPIOA},
65+
40: {28, &nxp.PORTA.PCR28, nxp.GPIOA},
66+
41: {29, &nxp.PORTA.PCR29, nxp.GPIOA},
67+
42: {26, &nxp.PORTA.PCR26, nxp.GPIOA},
68+
43: {20, &nxp.PORTB.PCR20, nxp.GPIOB},
69+
44: {22, &nxp.PORTB.PCR22, nxp.GPIOB},
70+
45: {23, &nxp.PORTB.PCR23, nxp.GPIOB},
71+
46: {21, &nxp.PORTB.PCR21, nxp.GPIOB},
72+
47: {8, &nxp.PORTD.PCR8, nxp.GPIOD},
73+
48: {9, &nxp.PORTD.PCR9, nxp.GPIOD},
74+
49: {4, &nxp.PORTB.PCR4, nxp.GPIOB},
75+
50: {5, &nxp.PORTB.PCR5, nxp.GPIOB},
76+
51: {14, &nxp.PORTD.PCR14, nxp.GPIOD},
77+
52: {13, &nxp.PORTD.PCR13, nxp.GPIOD},
78+
53: {12, &nxp.PORTD.PCR12, nxp.GPIOD},
79+
54: {15, &nxp.PORTD.PCR15, nxp.GPIOD},
80+
55: {11, &nxp.PORTD.PCR11, nxp.GPIOD},
81+
56: {10, &nxp.PORTE.PCR10, nxp.GPIOE},
82+
57: {11, &nxp.PORTE.PCR11, nxp.GPIOE},
83+
58: {0, &nxp.PORTE.PCR0, nxp.GPIOE},
84+
59: {1, &nxp.PORTE.PCR1, nxp.GPIOE},
85+
60: {2, &nxp.PORTE.PCR2, nxp.GPIOE},
86+
61: {3, &nxp.PORTE.PCR3, nxp.GPIOE},
87+
62: {4, &nxp.PORTE.PCR4, nxp.GPIOE},
88+
63: {5, &nxp.PORTE.PCR5, nxp.GPIOE},
3489
}
3590

3691
//go:inline
37-
func (p Pin) registers() pinRegisters {
38-
return _pinRegisters[p]
39-
}
92+
func (p Pin) reg() pin { return pins[p] }

‎src/machine/buffer.go‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,3 +44,9 @@ func (rb *RingBuffer) Get() (byte, bool) {
4444
}
4545
return 0, false
4646
}
47+
48+
// Clear resets the head and tail pointer to zero.
49+
func (rb *RingBuffer) Clear() {
50+
rb.head.Set(0)
51+
rb.tail.Set(0)
52+
}

‎src/machine/machine_nxpmk66f18.go‎

Lines changed: 38 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -7,19 +7,7 @@ import (
77
"runtime/volatile"
88
)
99

10-
const (
11-
PortControlRegisterSRE = nxp.PORT_PCR0_SRE
12-
PortControlRegisterDSE = nxp.PORT_PCR0_DSE
13-
PortControlRegisterODE = nxp.PORT_PCR0_ODE
14-
)
15-
16-
func PortControlRegisterMUX(v uint8) uint32 {
17-
return (uint32(v) << nxp.PORT_PCR0_MUX_Pos) & nxp.PORT_PCR0_MUX_Msk
18-
}
19-
20-
type pinRegisters struct {
21-
Bit uintptr
22-
PCR *volatile.Register32
10+
type FastPin struct {
2311
PDOR *volatile.BitRegister
2412
PSOR *volatile.BitRegister
2513
PCOR *volatile.BitRegister
@@ -28,29 +16,60 @@ type pinRegisters struct {
2816
PDDR *volatile.BitRegister
2917
}
3018

19+
type pin struct {
20+
Bit uint8
21+
PCR *volatile.Register32
22+
GPIO *nxp.GPIO_Type
23+
}
24+
3125
// Configure this pin with the given configuration.
3226
func (p Pin) Configure(config PinConfig) {
3327
switch config.Mode {
3428
case PinInput:
3529
panic("todo")
3630

3731
case PinOutput:
38-
p.registers().PDDR.Set()
39-
p.registers().PCR.SetBits(PortControlRegisterSRE | PortControlRegisterDSE | PortControlRegisterMUX(1))
40-
p.registers().PCR.ClearBits(PortControlRegisterODE)
32+
r := p.reg()
33+
r.GPIO.PDDR.SetBits(1 << r.Bit)
34+
r.PCR.SetBits(nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_MUX(1))
35+
r.PCR.ClearBits(nxp.PORT_PCR0_ODE)
4136
}
4237
}
4338

4439
// Set changes the value of the GPIO pin. The pin must be configured as output.
4540
func (p Pin) Set(value bool) {
41+
r := p.reg()
4642
if value {
47-
p.registers().PSOR.Set()
43+
r.GPIO.PSOR.Set(1 << r.Bit)
4844
} else {
49-
p.registers().PCOR.Set()
45+
r.GPIO.PCOR.Set(1 << r.Bit)
5046
}
5147
}
5248

5349
// Get returns the current value of a GPIO pin.
5450
func (p Pin) Get() bool {
55-
return p.registers().PDIR.Get()
51+
r := p.reg()
52+
return r.GPIO.PDIR.HasBits(1 << r.Bit)
53+
}
54+
55+
func (p Pin) Control() *volatile.Register32 {
56+
return p.reg().PCR
5657
}
58+
59+
func (p Pin) Fast() FastPin {
60+
r := p.reg()
61+
return FastPin{
62+
PDOR: r.GPIO.PDOR.Bit(r.Bit),
63+
PSOR: r.GPIO.PSOR.Bit(r.Bit),
64+
PCOR: r.GPIO.PCOR.Bit(r.Bit),
65+
PTOR: r.GPIO.PTOR.Bit(r.Bit),
66+
PDIR: r.GPIO.PDIR.Bit(r.Bit),
67+
PDDR: r.GPIO.PDDR.Bit(r.Bit),
68+
}
69+
}
70+
71+
func (p FastPin) Set() { p.PSOR.Set(true) }
72+
func (p FastPin) Clear() { p.PCOR.Set(true) }
73+
func (p FastPin) Toggle() { p.PTOR.Set(true) }
74+
func (p FastPin) Write(v bool) { p.PDOR.Set(v) }
75+
func (p FastPin) Read() bool { return p.PDIR.Get() }

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